diff options
Diffstat (limited to 'lib/pico-sdk/rp2350/hardware/structs')
55 files changed, 9654 insertions, 0 deletions
diff --git a/lib/pico-sdk/rp2350/hardware/structs/accessctrl.h b/lib/pico-sdk/rp2350/hardware/structs/accessctrl.h new file mode 100644 index 00000000..5fd30cb2 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/accessctrl.h @@ -0,0 +1,519 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_ACCESSCTRL_H +#define _HARDWARE_STRUCTS_ACCESSCTRL_H + +/** + * \file rp2350/accessctrl.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/accessctrl.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_accessctrl +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/accessctrl.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(ACCESSCTRL_LOCK_OFFSET) // ACCESSCTRL_LOCK + // Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master + // 0x00000008 [3] DEBUG (0) + // 0x00000004 [2] DMA (1) + // 0x00000002 [1] CORE1 (0) + // 0x00000001 [0] CORE0 (0) + io_rw_32 lock; + + _REG_(ACCESSCTRL_FORCE_CORE_NS_OFFSET) // ACCESSCTRL_FORCE_CORE_NS + // Force core 1's bus accesses to always be Non-secure, no matter the core's internal state + // 0x00000002 [1] CORE1 (0) + io_rw_32 force_core_ns; + + _REG_(ACCESSCTRL_CFGRESET_OFFSET) // ACCESSCTRL_CFGRESET + // Write 1 to reset all ACCESSCTRL configuration, except for the LOCK and FORCE_CORE_NS registers + // 0x00000001 [0] CFGRESET (0) + io_wo_32 cfgreset; + + // (Description copied from array index 0 register ACCESSCTRL_GPIO_NSMASK0 applies similarly to other array indexes) + _REG_(ACCESSCTRL_GPIO_NSMASK0_OFFSET) // ACCESSCTRL_GPIO_NSMASK0 + // Control whether GPIO0 + // 0xffffffff [31:0] GPIO_NSMASK0 (0x00000000) + io_rw_32 gpio_nsmask[2]; + + _REG_(ACCESSCTRL_ROM_OFFSET) // ACCESSCTRL_ROM + // Control access to ROM. Defaults to fully open access. + // 0x00000080 [7] DBG (1) If 1, ROM can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, ROM can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, ROM can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, ROM can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, ROM can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, ROM can be accessed from a... + // 0x00000002 [1] NSP (1) If 1, ROM can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (1) If 1, and NSP is also set, ROM can be accessed from a... + io_rw_32 rom; + + _REG_(ACCESSCTRL_XIP_MAIN_OFFSET) // ACCESSCTRL_XIP_MAIN + // Control access to XIP_MAIN. Defaults to fully open access. + // 0x00000080 [7] DBG (1) If 1, XIP_MAIN can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, XIP_MAIN can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, XIP_MAIN can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, XIP_MAIN can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, XIP_MAIN can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, XIP_MAIN can be accessed from... + // 0x00000002 [1] NSP (1) If 1, XIP_MAIN can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (1) If 1, and NSP is also set, XIP_MAIN can be accessed from... + io_rw_32 xip_main; + + // (Description copied from array index 0 register ACCESSCTRL_SRAM0 applies similarly to other array indexes) + _REG_(ACCESSCTRL_SRAM0_OFFSET) // ACCESSCTRL_SRAM0 + // Control access to SRAM0. Defaults to fully open access. + // 0x00000080 [7] DBG (1) If 1, SRAM0 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, SRAM0 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, SRAM0 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, SRAM0 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, SRAM0 can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, SRAM0 can be accessed from a... + // 0x00000002 [1] NSP (1) If 1, SRAM0 can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (1) If 1, and NSP is also set, SRAM0 can be accessed from a... + io_rw_32 sram[10]; + + _REG_(ACCESSCTRL_DMA_OFFSET) // ACCESSCTRL_DMA + // Control access to DMA. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, DMA can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, DMA can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, DMA can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, DMA can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, DMA can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, DMA can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, DMA can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, DMA can be accessed from a... + io_rw_32 dma; + + _REG_(ACCESSCTRL_USBCTRL_OFFSET) // ACCESSCTRL_USBCTRL + // Control access to USBCTRL. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, USBCTRL can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, USBCTRL can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, USBCTRL can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, USBCTRL can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, USBCTRL can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, USBCTRL can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, USBCTRL can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, USBCTRL can be accessed from... + io_rw_32 usbctrl; + + // (Description copied from array index 0 register ACCESSCTRL_PIO0 applies similarly to other array indexes) + _REG_(ACCESSCTRL_PIO0_OFFSET) // ACCESSCTRL_PIO0 + // Control access to PIO0. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, PIO0 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, PIO0 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, PIO0 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, PIO0 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, PIO0 can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, PIO0 can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, PIO0 can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PIO0 can be accessed from a... + io_rw_32 pio[3]; + + _REG_(ACCESSCTRL_CORESIGHT_TRACE_OFFSET) // ACCESSCTRL_CORESIGHT_TRACE + // Control access to CORESIGHT_TRACE. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, CORESIGHT_TRACE can be accessed by the debugger,... + // 0x00000040 [6] DMA (0) If 1, CORESIGHT_TRACE can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, CORESIGHT_TRACE can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, CORESIGHT_TRACE can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, CORESIGHT_TRACE can be accessed from a Secure,... + // 0x00000004 [2] SU (0) If 1, and SP is also set, CORESIGHT_TRACE can be... + // 0x00000002 [1] NSP (0) If 1, CORESIGHT_TRACE can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, CORESIGHT_TRACE can be... + io_rw_32 coresight_trace; + + _REG_(ACCESSCTRL_CORESIGHT_PERIPH_OFFSET) // ACCESSCTRL_CORESIGHT_PERIPH + // Control access to CORESIGHT_PERIPH. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, CORESIGHT_PERIPH can be accessed by the debugger,... + // 0x00000040 [6] DMA (0) If 1, CORESIGHT_PERIPH can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, CORESIGHT_PERIPH can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, CORESIGHT_PERIPH can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, CORESIGHT_PERIPH can be accessed from a Secure,... + // 0x00000004 [2] SU (0) If 1, and SP is also set, CORESIGHT_PERIPH can be... + // 0x00000002 [1] NSP (0) If 1, CORESIGHT_PERIPH can be accessed from a... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, CORESIGHT_PERIPH can be... + io_rw_32 coresight_periph; + + _REG_(ACCESSCTRL_SYSINFO_OFFSET) // ACCESSCTRL_SYSINFO + // Control access to SYSINFO. Defaults to fully open access. + // 0x00000080 [7] DBG (1) If 1, SYSINFO can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, SYSINFO can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, SYSINFO can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, SYSINFO can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, SYSINFO can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, SYSINFO can be accessed from a... + // 0x00000002 [1] NSP (1) If 1, SYSINFO can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (1) If 1, and NSP is also set, SYSINFO can be accessed from... + io_rw_32 sysinfo; + + _REG_(ACCESSCTRL_RESETS_OFFSET) // ACCESSCTRL_RESETS + // Control access to RESETS. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, RESETS can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, RESETS can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, RESETS can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, RESETS can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, RESETS can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, RESETS can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, RESETS can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, RESETS can be accessed from a... + io_rw_32 resets; + + // (Description copied from array index 0 register ACCESSCTRL_IO_BANK0 applies similarly to other array indexes) + _REG_(ACCESSCTRL_IO_BANK0_OFFSET) // ACCESSCTRL_IO_BANK0 + // Control access to IO_BANK0. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, IO_BANK0 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, IO_BANK0 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, IO_BANK0 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, IO_BANK0 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, IO_BANK0 can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, IO_BANK0 can be accessed from... + // 0x00000002 [1] NSP (0) If 1, IO_BANK0 can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, IO_BANK0 can be accessed from... + io_rw_32 io_bank[2]; + + _REG_(ACCESSCTRL_PADS_BANK0_OFFSET) // ACCESSCTRL_PADS_BANK0 + // Control access to PADS_BANK0. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, PADS_BANK0 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, PADS_BANK0 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, PADS_BANK0 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, PADS_BANK0 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, PADS_BANK0 can be accessed from a Secure,... + // 0x00000004 [2] SU (1) If 1, and SP is also set, PADS_BANK0 can be accessed... + // 0x00000002 [1] NSP (0) If 1, PADS_BANK0 can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PADS_BANK0 can be accessed... + io_rw_32 pads_bank0; + + _REG_(ACCESSCTRL_PADS_QSPI_OFFSET) // ACCESSCTRL_PADS_QSPI + // Control access to PADS_QSPI. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, PADS_QSPI can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, PADS_QSPI can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, PADS_QSPI can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, PADS_QSPI can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, PADS_QSPI can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, PADS_QSPI can be accessed from... + // 0x00000002 [1] NSP (0) If 1, PADS_QSPI can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PADS_QSPI can be accessed... + io_rw_32 pads_qspi; + + _REG_(ACCESSCTRL_BUSCTRL_OFFSET) // ACCESSCTRL_BUSCTRL + // Control access to BUSCTRL. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, BUSCTRL can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, BUSCTRL can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, BUSCTRL can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, BUSCTRL can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, BUSCTRL can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, BUSCTRL can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, BUSCTRL can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, BUSCTRL can be accessed from... + io_rw_32 busctrl; + + _REG_(ACCESSCTRL_ADC0_OFFSET) // ACCESSCTRL_ADC0 + // Control access to ADC0. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, ADC0 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, ADC0 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, ADC0 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, ADC0 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, ADC0 can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, ADC0 can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, ADC0 can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, ADC0 can be accessed from a... + io_rw_32 adc0; + + _REG_(ACCESSCTRL_HSTX_OFFSET) // ACCESSCTRL_HSTX + // Control access to HSTX. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, HSTX can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, HSTX can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, HSTX can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, HSTX can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, HSTX can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, HSTX can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, HSTX can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, HSTX can be accessed from a... + io_rw_32 hstx; + + // (Description copied from array index 0 register ACCESSCTRL_I2C0 applies similarly to other array indexes) + _REG_(ACCESSCTRL_I2C0_OFFSET) // ACCESSCTRL_I2C0 + // Control access to I2C0. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, I2C0 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, I2C0 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, I2C0 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, I2C0 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, I2C0 can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, I2C0 can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, I2C0 can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, I2C0 can be accessed from a... + io_rw_32 i2c[2]; + + _REG_(ACCESSCTRL_PWM_OFFSET) // ACCESSCTRL_PWM + // Control access to PWM. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, PWM can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, PWM can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, PWM can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, PWM can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, PWM can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, PWM can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, PWM can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PWM can be accessed from a... + io_rw_32 pwm; + + // (Description copied from array index 0 register ACCESSCTRL_SPI0 applies similarly to other array indexes) + _REG_(ACCESSCTRL_SPI0_OFFSET) // ACCESSCTRL_SPI0 + // Control access to SPI0. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, SPI0 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, SPI0 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, SPI0 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, SPI0 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, SPI0 can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, SPI0 can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, SPI0 can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, SPI0 can be accessed from a... + io_rw_32 spi[2]; + + // (Description copied from array index 0 register ACCESSCTRL_TIMER0 applies similarly to other array indexes) + _REG_(ACCESSCTRL_TIMER0_OFFSET) // ACCESSCTRL_TIMER0 + // Control access to TIMER0. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, TIMER0 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, TIMER0 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, TIMER0 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, TIMER0 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, TIMER0 can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, TIMER0 can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, TIMER0 can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, TIMER0 can be accessed from a... + io_rw_32 timer[2]; + + // (Description copied from array index 0 register ACCESSCTRL_UART0 applies similarly to other array indexes) + _REG_(ACCESSCTRL_UART0_OFFSET) // ACCESSCTRL_UART0 + // Control access to UART0. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, UART0 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, UART0 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, UART0 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, UART0 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, UART0 can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, UART0 can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, UART0 can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, UART0 can be accessed from a... + io_rw_32 uart[2]; + + _REG_(ACCESSCTRL_OTP_OFFSET) // ACCESSCTRL_OTP + // Control access to OTP. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, OTP can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, OTP can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, OTP can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, OTP can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, OTP can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, OTP can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, OTP can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, OTP can be accessed from a... + io_rw_32 otp; + + _REG_(ACCESSCTRL_TBMAN_OFFSET) // ACCESSCTRL_TBMAN + // Control access to TBMAN. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, TBMAN can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, TBMAN can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, TBMAN can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, TBMAN can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, TBMAN can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, TBMAN can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, TBMAN can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, TBMAN can be accessed from a... + io_rw_32 tbman; + + _REG_(ACCESSCTRL_POWMAN_OFFSET) // ACCESSCTRL_POWMAN + // Control access to POWMAN. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, POWMAN can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, POWMAN can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, POWMAN can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, POWMAN can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, POWMAN can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, POWMAN can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, POWMAN can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, POWMAN can be accessed from a... + io_rw_32 powman; + + _REG_(ACCESSCTRL_TRNG_OFFSET) // ACCESSCTRL_TRNG + // Control access to TRNG. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, TRNG can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, TRNG can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, TRNG can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, TRNG can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, TRNG can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, TRNG can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, TRNG can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, TRNG can be accessed from a... + io_rw_32 trng; + + _REG_(ACCESSCTRL_SHA256_OFFSET) // ACCESSCTRL_SHA256 + // Control access to SHA256. Defaults to Secure, Privileged access only. + // 0x00000080 [7] DBG (1) If 1, SHA256 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, SHA256 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, SHA256 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, SHA256 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, SHA256 can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, SHA256 can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, SHA256 can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, SHA256 can be accessed from a... + io_rw_32 sha256; + + _REG_(ACCESSCTRL_SYSCFG_OFFSET) // ACCESSCTRL_SYSCFG + // Control access to SYSCFG. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, SYSCFG can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, SYSCFG can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, SYSCFG can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, SYSCFG can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, SYSCFG can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, SYSCFG can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, SYSCFG can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, SYSCFG can be accessed from a... + io_rw_32 syscfg; + + _REG_(ACCESSCTRL_CLOCKS_OFFSET) // ACCESSCTRL_CLOCKS + // Control access to CLOCKS. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, CLOCKS can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, CLOCKS can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, CLOCKS can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, CLOCKS can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, CLOCKS can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, CLOCKS can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, CLOCKS can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, CLOCKS can be accessed from a... + io_rw_32 clocks; + + _REG_(ACCESSCTRL_XOSC_OFFSET) // ACCESSCTRL_XOSC + // Control access to XOSC. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, XOSC can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, XOSC can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, XOSC can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, XOSC can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, XOSC can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, XOSC can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, XOSC can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, XOSC can be accessed from a... + io_rw_32 xosc; + + _REG_(ACCESSCTRL_ROSC_OFFSET) // ACCESSCTRL_ROSC + // Control access to ROSC. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, ROSC can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, ROSC can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, ROSC can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, ROSC can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, ROSC can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, ROSC can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, ROSC can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, ROSC can be accessed from a... + io_rw_32 rosc; + + _REG_(ACCESSCTRL_PLL_SYS_OFFSET) // ACCESSCTRL_PLL_SYS + // Control access to PLL_SYS. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, PLL_SYS can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, PLL_SYS can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, PLL_SYS can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, PLL_SYS can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, PLL_SYS can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, PLL_SYS can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, PLL_SYS can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PLL_SYS can be accessed from... + io_rw_32 pll_sys; + + _REG_(ACCESSCTRL_PLL_USB_OFFSET) // ACCESSCTRL_PLL_USB + // Control access to PLL_USB. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, PLL_USB can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, PLL_USB can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, PLL_USB can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, PLL_USB can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, PLL_USB can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, PLL_USB can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, PLL_USB can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PLL_USB can be accessed from... + io_rw_32 pll_usb; + + _REG_(ACCESSCTRL_TICKS_OFFSET) // ACCESSCTRL_TICKS + // Control access to TICKS. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, TICKS can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, TICKS can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, TICKS can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, TICKS can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, TICKS can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, TICKS can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, TICKS can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, TICKS can be accessed from a... + io_rw_32 ticks; + + _REG_(ACCESSCTRL_WATCHDOG_OFFSET) // ACCESSCTRL_WATCHDOG + // Control access to WATCHDOG. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, WATCHDOG can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, WATCHDOG can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, WATCHDOG can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, WATCHDOG can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, WATCHDOG can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, WATCHDOG can be accessed from... + // 0x00000002 [1] NSP (0) If 1, WATCHDOG can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, WATCHDOG can be accessed from... + io_rw_32 watchdog; + + _REG_(ACCESSCTRL_RSM_OFFSET) // ACCESSCTRL_RSM + // Control access to RSM. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, RSM can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, RSM can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, RSM can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, RSM can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, RSM can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, RSM can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, RSM can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, RSM can be accessed from a... + io_rw_32 rsm; + + _REG_(ACCESSCTRL_XIP_CTRL_OFFSET) // ACCESSCTRL_XIP_CTRL + // Control access to XIP_CTRL. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, XIP_CTRL can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, XIP_CTRL can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, XIP_CTRL can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, XIP_CTRL can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, XIP_CTRL can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, XIP_CTRL can be accessed from... + // 0x00000002 [1] NSP (0) If 1, XIP_CTRL can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, XIP_CTRL can be accessed from... + io_rw_32 xip_ctrl; + + _REG_(ACCESSCTRL_XIP_QMI_OFFSET) // ACCESSCTRL_XIP_QMI + // Control access to XIP_QMI. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, XIP_QMI can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, XIP_QMI can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, XIP_QMI can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, XIP_QMI can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, XIP_QMI can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, XIP_QMI can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, XIP_QMI can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, XIP_QMI can be accessed from... + io_rw_32 xip_qmi; + + _REG_(ACCESSCTRL_XIP_AUX_OFFSET) // ACCESSCTRL_XIP_AUX + // Control access to XIP_AUX. Defaults to Secure, Privileged access only. + // 0x00000080 [7] DBG (1) If 1, XIP_AUX can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, XIP_AUX can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, XIP_AUX can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, XIP_AUX can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, XIP_AUX can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, XIP_AUX can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, XIP_AUX can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, XIP_AUX can be accessed from... + io_rw_32 xip_aux; +} accessctrl_hw_t; + +#define accessctrl_hw ((accessctrl_hw_t *)ACCESSCTRL_BASE) +static_assert(sizeof (accessctrl_hw_t) == 0x00ec, ""); + +#endif // _HARDWARE_STRUCTS_ACCESSCTRL_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/adc.h b/lib/pico-sdk/rp2350/hardware/structs/adc.h new file mode 100644 index 00000000..687128eb --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/adc.h @@ -0,0 +1,96 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_ADC_H +#define _HARDWARE_STRUCTS_ADC_H + +/** + * \file rp2350/adc.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/adc.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_adc +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/adc.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(ADC_CS_OFFSET) // ADC_CS + // ADC Control and Status + // 0x01ff0000 [24:16] RROBIN (0x000) Round-robin sampling + // 0x0000f000 [15:12] AINSEL (0x0) Select analog mux input + // 0x00000400 [10] ERR_STICKY (0) Some past ADC conversion encountered an error + // 0x00000200 [9] ERR (0) The most recent ADC conversion encountered an error;... + // 0x00000100 [8] READY (0) 1 if the ADC is ready to start a new conversion + // 0x00000008 [3] START_MANY (0) Continuously perform conversions whilst this bit is 1 + // 0x00000004 [2] START_ONCE (0) Start a single conversion + // 0x00000002 [1] TS_EN (0) Power on temperature sensor + // 0x00000001 [0] EN (0) Power on ADC and enable its clock + io_rw_32 cs; + + _REG_(ADC_RESULT_OFFSET) // ADC_RESULT + // Result of most recent ADC conversion + // 0x00000fff [11:0] RESULT (0x000) + io_ro_32 result; + + _REG_(ADC_FCS_OFFSET) // ADC_FCS + // FIFO control and status + // 0x0f000000 [27:24] THRESH (0x0) DREQ/IRQ asserted when level >= threshold + // 0x000f0000 [19:16] LEVEL (0x0) The number of conversion results currently waiting in the FIFO + // 0x00000800 [11] OVER (0) 1 if the FIFO has been overflowed + // 0x00000400 [10] UNDER (0) 1 if the FIFO has been underflowed + // 0x00000200 [9] FULL (0) + // 0x00000100 [8] EMPTY (0) + // 0x00000008 [3] DREQ_EN (0) If 1: assert DMA requests when FIFO contains data + // 0x00000004 [2] ERR (0) If 1: conversion error bit appears in the FIFO alongside... + // 0x00000002 [1] SHIFT (0) If 1: FIFO results are right-shifted to be one byte in size + // 0x00000001 [0] EN (0) If 1: write result to the FIFO after each conversion + io_rw_32 fcs; + + _REG_(ADC_FIFO_OFFSET) // ADC_FIFO + // Conversion result FIFO + // 0x00008000 [15] ERR (-) 1 if this particular sample experienced a conversion error + // 0x00000fff [11:0] VAL (-) + io_ro_32 fifo; + + _REG_(ADC_DIV_OFFSET) // ADC_DIV + // Clock divider + // 0x00ffff00 [23:8] INT (0x0000) Integer part of clock divisor + // 0x000000ff [7:0] FRAC (0x00) Fractional part of clock divisor + io_rw_32 div; + + _REG_(ADC_INTR_OFFSET) // ADC_INTR + // Raw Interrupts + // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level + io_ro_32 intr; + + _REG_(ADC_INTE_OFFSET) // ADC_INTE + // Interrupt Enable + // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level + io_rw_32 inte; + + _REG_(ADC_INTF_OFFSET) // ADC_INTF + // Interrupt Force + // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level + io_rw_32 intf; + + _REG_(ADC_INTS_OFFSET) // ADC_INTS + // Interrupt status after masking & forcing + // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level + io_ro_32 ints; +} adc_hw_t; + +#define adc_hw ((adc_hw_t *)ADC_BASE) +static_assert(sizeof (adc_hw_t) == 0x0024, ""); + +#endif // _HARDWARE_STRUCTS_ADC_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/bootram.h b/lib/pico-sdk/rp2350/hardware/structs/bootram.h new file mode 100644 index 00000000..b40a0393 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/bootram.h @@ -0,0 +1,49 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_BOOTRAM_H +#define _HARDWARE_STRUCTS_BOOTRAM_H + +/** + * \file rp2350/bootram.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/bootram.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_bootram +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/bootram.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + // (Description copied from array index 0 register BOOTRAM_WRITE_ONCE0 applies similarly to other array indexes) + _REG_(BOOTRAM_WRITE_ONCE0_OFFSET) // BOOTRAM_WRITE_ONCE0 + // This registers always ORs writes into its current contents + // 0xffffffff [31:0] WRITE_ONCE0 (0x00000000) + io_rw_32 write_once[2]; + + _REG_(BOOTRAM_BOOTLOCK_STAT_OFFSET) // BOOTRAM_BOOTLOCK_STAT + // Bootlock status register + // 0x000000ff [7:0] BOOTLOCK_STAT (0xff) + io_rw_32 bootlock_stat; + + // (Description copied from array index 0 register BOOTRAM_BOOTLOCK0 applies similarly to other array indexes) + _REG_(BOOTRAM_BOOTLOCK0_OFFSET) // BOOTRAM_BOOTLOCK0 + // Read to claim and check + // 0xffffffff [31:0] BOOTLOCK0 (0x00000000) + io_rw_32 bootlock[8]; +} bootram_hw_t; + +#define bootram_hw ((bootram_hw_t *)(BOOTRAM_BASE + BOOTRAM_WRITE_ONCE0_OFFSET)) +static_assert(sizeof (bootram_hw_t) == 0x002c, ""); + +#endif // _HARDWARE_STRUCTS_BOOTRAM_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/bus_ctrl.h b/lib/pico-sdk/rp2350/hardware/structs/bus_ctrl.h new file mode 100644 index 00000000..b94a4045 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/bus_ctrl.h @@ -0,0 +1,9 @@ +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// Support old header for compatibility (and if included, support old variable name) +#include "hardware/structs/busctrl.h" +#define bus_ctrl_hw busctrl_hw
\ No newline at end of file diff --git a/lib/pico-sdk/rp2350/hardware/structs/busctrl.h b/lib/pico-sdk/rp2350/hardware/structs/busctrl.h new file mode 100644 index 00000000..2eb83a99 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/busctrl.h @@ -0,0 +1,90 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_BUSCTRL_H +#define _HARDWARE_STRUCTS_BUSCTRL_H + +/** + * \file rp2350/busctrl.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/busctrl.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_busctrl +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/busctrl.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/** \brief Bus fabric performance counters on RP2350 (used as typedef \ref bus_ctrl_perf_counter_t) + * \ingroup hardware_busctrl + */ +typedef enum bus_ctrl_perf_counter_rp2350 { + arbiter_rom_perf_event_access = 19, + arbiter_rom_perf_event_access_contested = 18, + arbiter_xip_main_perf_event_access = 17, + arbiter_xip_main_perf_event_access_contested = 16, + arbiter_sram0_perf_event_access = 15, + arbiter_sram0_perf_event_access_contested = 14, + arbiter_sram1_perf_event_access = 13, + arbiter_sram1_perf_event_access_contested = 12, + arbiter_sram2_perf_event_access = 11, + arbiter_sram2_perf_event_access_contested = 10, + arbiter_sram3_perf_event_access = 9, + arbiter_sram3_perf_event_access_contested = 8, + arbiter_sram4_perf_event_access = 7, + arbiter_sram4_perf_event_access_contested = 6, + arbiter_sram5_perf_event_access = 5, + arbiter_sram5_perf_event_access_contested = 4, + arbiter_fastperi_perf_event_access = 3, + arbiter_fastperi_perf_event_access_contested = 2, + arbiter_apb_perf_event_access = 1, + arbiter_apb_perf_event_access_contested = 0 +} bus_ctrl_perf_counter_t; + +typedef struct { + _REG_(BUSCTRL_PERFCTR0_OFFSET) // BUSCTRL_PERFCTR0 + // Bus fabric performance counter 0 + // 0x00ffffff [23:0] PERFCTR0 (0x000000) Busfabric saturating performance counter 0 + + io_rw_32 value; + + _REG_(BUSCTRL_PERFSEL0_OFFSET) // BUSCTRL_PERFSEL0 + // Bus fabric performance event select for PERFCTR0 + // 0x0000007f [6:0] PERFSEL0 (0x1f) Select an event for PERFCTR0 + io_rw_32 sel; +} bus_ctrl_perf_hw_t; + +typedef struct { + _REG_(BUSCTRL_BUS_PRIORITY_OFFSET) // BUSCTRL_BUS_PRIORITY + // Set the priority of each master for bus arbitration + // 0x00001000 [12] DMA_W (0) 0 - low priority, 1 - high priority + // 0x00000100 [8] DMA_R (0) 0 - low priority, 1 - high priority + // 0x00000010 [4] PROC1 (0) 0 - low priority, 1 - high priority + // 0x00000001 [0] PROC0 (0) 0 - low priority, 1 - high priority + io_rw_32 priority; + + _REG_(BUSCTRL_BUS_PRIORITY_ACK_OFFSET) // BUSCTRL_BUS_PRIORITY_ACK + // Bus priority acknowledge + // 0x00000001 [0] BUS_PRIORITY_ACK (0) Goes to 1 once all arbiters have registered the new... + io_ro_32 priority_ack; + + _REG_(BUSCTRL_PERFCTR_EN_OFFSET) // BUSCTRL_PERFCTR_EN + // Enable the performance counters + // 0x00000001 [0] PERFCTR_EN (0) + io_rw_32 perfctr_en; + + bus_ctrl_perf_hw_t counter[4]; +} busctrl_hw_t; + +#define busctrl_hw ((busctrl_hw_t *)BUSCTRL_BASE) +static_assert(sizeof (busctrl_hw_t) == 0x002c, ""); + +#endif // _HARDWARE_STRUCTS_BUSCTRL_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/clocks.h b/lib/pico-sdk/rp2350/hardware/structs/clocks.h new file mode 100644 index 00000000..2cdc1b82 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/clocks.h @@ -0,0 +1,580 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_CLOCKS_H +#define _HARDWARE_STRUCTS_CLOCKS_H + +/** + * \file rp2350/clocks.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/clocks.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_clocks +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/clocks.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/** \brief Clock numbers on RP2350 (used as typedef \ref clock_num_t) + * \ingroup hardware_clocks + */ +/// \tag::clkenum[] +typedef enum clock_num_rp2350 { + clk_gpout0 = 0, ///< Select CLK_GPOUT0 as clock source + clk_gpout1 = 1, ///< Select CLK_GPOUT1 as clock source + clk_gpout2 = 2, ///< Select CLK_GPOUT2 as clock source + clk_gpout3 = 3, ///< Select CLK_GPOUT3 as clock source + clk_ref = 4, ///< Select CLK_REF as clock source + clk_sys = 5, ///< Select CLK_SYS as clock source + clk_peri = 6, ///< Select CLK_PERI as clock source + clk_hstx = 7, ///< Select CLK_HSTX as clock source + clk_usb = 8, ///< Select CLK_USB as clock source + clk_adc = 9, ///< Select CLK_ADC as clock source + CLK_COUNT +} clock_num_t; +/// \end::clkenum[] + +/** \brief Clock destination numbers on RP2350 (used as typedef \ref clock_dest_num_t) + * \ingroup hardware_clocks + */ +typedef enum clock_dest_num_rp2350 { + CLK_DEST_SYS_CLOCKS = 0, ///< Select SYS_CLOCKS as clock destination + CLK_DEST_SYS_ACCESSCTRL = 1, ///< Select SYS_ACCESSCTRL as clock destination + CLK_DEST_ADC = 2, ///< Select ADC as clock destination + CLK_DEST_SYS_ADC = 3, ///< Select SYS_ADC as clock destination + CLK_DEST_SYS_BOOTRAM = 4, ///< Select SYS_BOOTRAM as clock destination + CLK_DEST_SYS_BUSCTRL = 5, ///< Select SYS_BUSCTRL as clock destination + CLK_DEST_SYS_BUSFABRIC = 6, ///< Select SYS_BUSFABRIC as clock destination + CLK_DEST_SYS_DMA = 7, ///< Select SYS_DMA as clock destination + CLK_DEST_SYS_GLITCH_DETECTOR = 8, ///< Select SYS_GLITCH_DETECTOR as clock destination + CLK_DEST_HSTX = 9, ///< Select HSTX as clock destination + CLK_DEST_SYS_HSTX = 10, ///< Select SYS_HSTX as clock destination + CLK_DEST_SYS_I2C0 = 11, ///< Select SYS_I2C0 as clock destination + CLK_DEST_SYS_I2C1 = 12, ///< Select SYS_I2C1 as clock destination + CLK_DEST_SYS_IO = 13, ///< Select SYS_IO as clock destination + CLK_DEST_SYS_JTAG = 14, ///< Select SYS_JTAG as clock destination + CLK_DEST_REF_OTP = 15, ///< Select REF_OTP as clock destination + CLK_DEST_SYS_OTP = 16, ///< Select SYS_OTP as clock destination + CLK_DEST_SYS_PADS = 17, ///< Select SYS_PADS as clock destination + CLK_DEST_SYS_PIO0 = 18, ///< Select SYS_PIO0 as clock destination + CLK_DEST_SYS_PIO1 = 19, ///< Select SYS_PIO1 as clock destination + CLK_DEST_SYS_PIO2 = 20, ///< Select SYS_PIO2 as clock destination + CLK_DEST_SYS_PLL_SYS = 21, ///< Select SYS_PLL_SYS as clock destination + CLK_DEST_SYS_PLL_USB = 22, ///< Select SYS_PLL_USB as clock destination + CLK_DEST_REF_POWMAN = 23, ///< Select REF_POWMAN as clock destination + CLK_DEST_SYS_POWMAN = 24, ///< Select SYS_POWMAN as clock destination + CLK_DEST_SYS_PWM = 25, ///< Select SYS_PWM as clock destination + CLK_DEST_SYS_RESETS = 26, ///< Select SYS_RESETS as clock destination + CLK_DEST_SYS_ROM = 27, ///< Select SYS_ROM as clock destination + CLK_DEST_SYS_ROSC = 28, ///< Select SYS_ROSC as clock destination + CLK_DEST_SYS_PSM = 29, ///< Select SYS_PSM as clock destination + CLK_DEST_SYS_SHA256 = 30, ///< Select SYS_SHA256 as clock destination + CLK_DEST_SYS_SIO = 31, ///< Select SYS_SIO as clock destination + CLK_DEST_PERI_SPI0 = 32, ///< Select PERI_SPI0 as clock destination + CLK_DEST_SYS_SPI0 = 33, ///< Select SYS_SPI0 as clock destination + CLK_DEST_PERI_SPI1 = 34, ///< Select PERI_SPI1 as clock destination + CLK_DEST_SYS_SPI1 = 35, ///< Select SYS_SPI1 as clock destination + CLK_DEST_SYS_SRAM0 = 36, ///< Select SYS_SRAM0 as clock destination + CLK_DEST_SYS_SRAM1 = 37, ///< Select SYS_SRAM1 as clock destination + CLK_DEST_SYS_SRAM2 = 38, ///< Select SYS_SRAM2 as clock destination + CLK_DEST_SYS_SRAM3 = 39, ///< Select SYS_SRAM3 as clock destination + CLK_DEST_SYS_SRAM4 = 40, ///< Select SYS_SRAM4 as clock destination + CLK_DEST_SYS_SRAM5 = 41, ///< Select SYS_SRAM5 as clock destination + CLK_DEST_SYS_SRAM6 = 42, ///< Select SYS_SRAM6 as clock destination + CLK_DEST_SYS_SRAM7 = 43, ///< Select SYS_SRAM7 as clock destination + CLK_DEST_SYS_SRAM8 = 44, ///< Select SYS_SRAM8 as clock destination + CLK_DEST_SYS_SRAM9 = 45, ///< Select SYS_SRAM9 as clock destination + CLK_DEST_SYS_SYSCFG = 46, ///< Select SYS_SYSCFG as clock destination + CLK_DEST_SYS_SYSINFO = 47, ///< Select SYS_SYSINFO as clock destination + CLK_DEST_SYS_TBMAN = 48, ///< Select SYS_TBMAN as clock destination + CLK_DEST_REF_TICKS = 49, ///< Select REF_TICKS as clock destination + CLK_DEST_SYS_TICKS = 50, ///< Select SYS_TICKS as clock destination + CLK_DEST_SYS_TIMER0 = 51, ///< Select SYS_TIMER0 as clock destination + CLK_DEST_SYS_TIMER1 = 52, ///< Select SYS_TIMER1 as clock destination + CLK_DEST_SYS_TRNG = 53, ///< Select SYS_TRNG as clock destination + CLK_DEST_PERI_UART0 = 54, ///< Select PERI_UART0 as clock destination + CLK_DEST_SYS_UART0 = 55, ///< Select SYS_UART0 as clock destination + CLK_DEST_PERI_UART1 = 56, ///< Select PERI_UART1 as clock destination + CLK_DEST_SYS_UART1 = 57, ///< Select SYS_UART1 as clock destination + CLK_DEST_SYS_USBCTRL = 58, ///< Select SYS_USBCTRL as clock destination + CLK_DEST_USB = 59, ///< Select USB as clock destination + CLK_DEST_SYS_WATCHDOG = 60, ///< Select SYS_WATCHDOG as clock destination + CLK_DEST_SYS_XIP = 61, ///< Select SYS_XIP as clock destination + CLK_DEST_SYS_XOSC = 62, ///< Select SYS_XOSC as clock destination + NUM_CLOCK_DESTINATIONS +} clock_dest_num_t; + +/// \tag::clock_hw[] +typedef struct { + _REG_(CLOCKS_CLK_GPOUT0_CTRL_OFFSET) // CLOCKS_CLK_GPOUT0_CTRL + // Clock control, can be changed on-the-fly (except for auxsrc) + // 0x10000000 [28] ENABLED (0) clock generator is enabled + // 0x00100000 [20] NUDGE (0) An edge on this signal shifts the phase of the output by... + // 0x00030000 [17:16] PHASE (0x0) This delays the enable signal by up to 3 cycles of the... + // 0x00001000 [12] DC50 (0) Enables duty cycle correction for odd divisors, can be... + // 0x00000800 [11] ENABLE (0) Starts and stops the clock generator cleanly + // 0x00000400 [10] KILL (0) Asynchronously kills the clock generator, enable must be... + // 0x000001e0 [8:5] AUXSRC (0x0) Selects the auxiliary clock source, will glitch when switching + io_rw_32 ctrl; + + _REG_(CLOCKS_CLK_GPOUT0_DIV_OFFSET) // CLOCKS_CLK_GPOUT0_DIV + // 0xffff0000 [31:16] INT (0x0001) Integer part of clock divisor, 0 -> max+1, can be... + // 0x0000ffff [15:0] FRAC (0x0000) Fractional component of the divisor, can be changed on-the-fly + io_rw_32 div; + + _REG_(CLOCKS_CLK_GPOUT0_SELECTED_OFFSET) // CLOCKS_CLK_GPOUT0_SELECTED + // Indicates which src is currently selected (one-hot) + // 0x00000001 [0] CLK_GPOUT0_SELECTED (1) This slice does not have a glitchless mux (only the... + io_ro_32 selected; +} clock_hw_t; +/// \end::clock_hw[] + +typedef struct { + _REG_(CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET) // CLOCKS_CLK_SYS_RESUS_CTRL + // 0x00010000 [16] CLEAR (0) For clearing the resus after the fault that triggered it... + // 0x00001000 [12] FRCE (0) Force a resus, for test purposes only + // 0x00000100 [8] ENABLE (0) Enable resus + // 0x000000ff [7:0] TIMEOUT (0xff) This is expressed as a number of clk_ref cycles + + io_rw_32 ctrl; + + _REG_(CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET) // CLOCKS_CLK_SYS_RESUS_STATUS + // 0x00000001 [0] RESUSSED (0) Clock has been resuscitated, correct the error then send... + io_ro_32 status; +} clock_resus_hw_t; + +typedef struct { + _REG_(CLOCKS_FC0_REF_KHZ_OFFSET) // CLOCKS_FC0_REF_KHZ + // Reference clock frequency in kHz + // 0x000fffff [19:0] FC0_REF_KHZ (0x00000) + io_rw_32 ref_khz; + + _REG_(CLOCKS_FC0_MIN_KHZ_OFFSET) // CLOCKS_FC0_MIN_KHZ + // Minimum pass frequency in kHz + // 0x01ffffff [24:0] FC0_MIN_KHZ (0x0000000) + io_rw_32 min_khz; + + _REG_(CLOCKS_FC0_MAX_KHZ_OFFSET) // CLOCKS_FC0_MAX_KHZ + // Maximum pass frequency in kHz + // 0x01ffffff [24:0] FC0_MAX_KHZ (0x1ffffff) + io_rw_32 max_khz; + + _REG_(CLOCKS_FC0_DELAY_OFFSET) // CLOCKS_FC0_DELAY + // Delays the start of frequency counting to allow the mux to settle + + // 0x00000007 [2:0] FC0_DELAY (0x1) + io_rw_32 delay; + + _REG_(CLOCKS_FC0_INTERVAL_OFFSET) // CLOCKS_FC0_INTERVAL + // The test interval is 0 + // 0x0000000f [3:0] FC0_INTERVAL (0x8) + io_rw_32 interval; + + _REG_(CLOCKS_FC0_SRC_OFFSET) // CLOCKS_FC0_SRC + // Clock sent to frequency counter, set to 0 when not required + + // 0x000000ff [7:0] FC0_SRC (0x00) + io_rw_32 src; + + _REG_(CLOCKS_FC0_STATUS_OFFSET) // CLOCKS_FC0_STATUS + // Frequency counter status + // 0x10000000 [28] DIED (0) Test clock stopped during test + // 0x01000000 [24] FAST (0) Test clock faster than expected, only valid when status_done=1 + // 0x00100000 [20] SLOW (0) Test clock slower than expected, only valid when status_done=1 + // 0x00010000 [16] FAIL (0) Test failed + // 0x00001000 [12] WAITING (0) Waiting for test clock to start + // 0x00000100 [8] RUNNING (0) Test running + // 0x00000010 [4] DONE (0) Test complete + // 0x00000001 [0] PASS (0) Test passed + io_ro_32 status; + + _REG_(CLOCKS_FC0_RESULT_OFFSET) // CLOCKS_FC0_RESULT + // Result of frequency measurement, only valid when status_done=1 + // 0x3fffffe0 [29:5] KHZ (0x0000000) + // 0x0000001f [4:0] FRAC (0x00) + io_ro_32 result; +} fc_hw_t; + +typedef struct { + clock_hw_t clk[10]; + + _REG_(CLOCKS_DFTCLK_XOSC_CTRL_OFFSET) // CLOCKS_DFTCLK_XOSC_CTRL + // 0x00000003 [1:0] SRC (0x0) + io_rw_32 dftclk_xosc_ctrl; + + _REG_(CLOCKS_DFTCLK_ROSC_CTRL_OFFSET) // CLOCKS_DFTCLK_ROSC_CTRL + // 0x00000003 [1:0] SRC (0x0) + io_rw_32 dftclk_rosc_ctrl; + + _REG_(CLOCKS_DFTCLK_LPOSC_CTRL_OFFSET) // CLOCKS_DFTCLK_LPOSC_CTRL + // 0x00000003 [1:0] SRC (0x0) + io_rw_32 dftclk_lposc_ctrl; + + clock_resus_hw_t resus; + + fc_hw_t fc0; + + union { + struct { + _REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0 + // enable clock in wake mode + // 0x80000000 [31] CLK_SYS_SIOB (1) + // 0x40000000 [30] CLK_SYS_SHA256 (1) + // 0x20000000 [29] CLK_SYS_RSM (1) + // 0x10000000 [28] CLK_SYS_ROSC (1) + // 0x08000000 [27] CLK_SYS_ROM (1) + // 0x04000000 [26] CLK_SYS_RESETS (1) + // 0x02000000 [25] CLK_SYS_PWM (1) + // 0x01000000 [24] CLK_SYS_POWMAN (1) + // 0x00800000 [23] CLK_REF_POWMAN (1) + // 0x00400000 [22] CLK_SYS_PLL_USB (1) + // 0x00200000 [21] CLK_SYS_PLL_SYS (1) + // 0x00100000 [20] CLK_SYS_PIO2 (1) + // 0x00080000 [19] CLK_SYS_PIO1 (1) + // 0x00040000 [18] CLK_SYS_PIO0 (1) + // 0x00020000 [17] CLK_SYS_PADS (1) + // 0x00010000 [16] CLK_SYS_OTP (1) + // 0x00008000 [15] CLK_REF_OTP (1) + // 0x00004000 [14] CLK_SYS_JTAG (1) + // 0x00002000 [13] CLK_SYS_IO (1) + // 0x00001000 [12] CLK_SYS_I2C1 (1) + // 0x00000800 [11] CLK_SYS_I2C0 (1) + // 0x00000400 [10] CLK_SYS_HSTX (1) + // 0x00000200 [9] CLK_HSTX (1) + // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (1) + // 0x00000080 [7] CLK_SYS_DMA (1) + // 0x00000040 [6] CLK_SYS_BUSFABRIC (1) + // 0x00000020 [5] CLK_SYS_BUSCTRL (1) + // 0x00000010 [4] CLK_SYS_BOOTRAM (1) + // 0x00000008 [3] CLK_SYS_ADC (1) + // 0x00000004 [2] CLK_ADC (1) + // 0x00000002 [1] CLK_SYS_ACCESSCTRL (1) + // 0x00000001 [0] CLK_SYS_CLOCKS (1) + io_rw_32 wake_en0; + + _REG_(CLOCKS_WAKE_EN1_OFFSET) // CLOCKS_WAKE_EN1 + // enable clock in wake mode + // 0x40000000 [30] CLK_SYS_XOSC (1) + // 0x20000000 [29] CLK_SYS_XIP (1) + // 0x10000000 [28] CLK_SYS_WATCHDOG (1) + // 0x08000000 [27] CLK_USB (1) + // 0x04000000 [26] CLK_SYS_USBCTRL (1) + // 0x02000000 [25] CLK_SYS_UART1 (1) + // 0x01000000 [24] CLK_PERI_UART1 (1) + // 0x00800000 [23] CLK_SYS_UART0 (1) + // 0x00400000 [22] CLK_PERI_UART0 (1) + // 0x00200000 [21] CLK_SYS_TRNG (1) + // 0x00100000 [20] CLK_SYS_TIMER1 (1) + // 0x00080000 [19] CLK_SYS_TIMER0 (1) + // 0x00040000 [18] CLK_SYS_TICKS (1) + // 0x00020000 [17] CLK_REF_TICKS (1) + // 0x00010000 [16] CLK_SYS_TBMAN (1) + // 0x00008000 [15] CLK_SYS_SYSINFO (1) + // 0x00004000 [14] CLK_SYS_SYSCFG (1) + // 0x00002000 [13] CLK_SYS_SRAM9 (1) + // 0x00001000 [12] CLK_SYS_SRAM8 (1) + // 0x00000800 [11] CLK_SYS_SRAM7 (1) + // 0x00000400 [10] CLK_SYS_SRAM6 (1) + // 0x00000200 [9] CLK_SYS_SRAM5 (1) + // 0x00000100 [8] CLK_SYS_SRAM4 (1) + // 0x00000080 [7] CLK_SYS_SRAM3 (1) + // 0x00000040 [6] CLK_SYS_SRAM2 (1) + // 0x00000020 [5] CLK_SYS_SRAM1 (1) + // 0x00000010 [4] CLK_SYS_SRAM0 (1) + // 0x00000008 [3] CLK_SYS_SPI1 (1) + // 0x00000004 [2] CLK_PERI_SPI1 (1) + // 0x00000002 [1] CLK_SYS_SPI0 (1) + // 0x00000001 [0] CLK_PERI_SPI0 (1) + io_rw_32 wake_en1; + }; + // (Description copied from array index 0 register CLOCKS_WAKE_EN0 applies similarly to other array indexes) + _REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0 + // enable clock in wake mode + // 0x80000000 [31] CLK_SYS_SIO (1) + // 0x40000000 [30] CLK_SYS_SHA256 (1) + // 0x20000000 [29] CLK_SYS_PSM (1) + // 0x10000000 [28] CLK_SYS_ROSC (1) + // 0x08000000 [27] CLK_SYS_ROM (1) + // 0x04000000 [26] CLK_SYS_RESETS (1) + // 0x02000000 [25] CLK_SYS_PWM (1) + // 0x01000000 [24] CLK_SYS_POWMAN (1) + // 0x00800000 [23] CLK_REF_POWMAN (1) + // 0x00400000 [22] CLK_SYS_PLL_USB (1) + // 0x00200000 [21] CLK_SYS_PLL_SYS (1) + // 0x00100000 [20] CLK_SYS_PIO2 (1) + // 0x00080000 [19] CLK_SYS_PIO1 (1) + // 0x00040000 [18] CLK_SYS_PIO0 (1) + // 0x00020000 [17] CLK_SYS_PADS (1) + // 0x00010000 [16] CLK_SYS_OTP (1) + // 0x00008000 [15] CLK_REF_OTP (1) + // 0x00004000 [14] CLK_SYS_JTAG (1) + // 0x00002000 [13] CLK_SYS_IO (1) + // 0x00001000 [12] CLK_SYS_I2C1 (1) + // 0x00000800 [11] CLK_SYS_I2C0 (1) + // 0x00000400 [10] CLK_SYS_HSTX (1) + // 0x00000200 [9] CLK_HSTX (1) + // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (1) + // 0x00000080 [7] CLK_SYS_DMA (1) + // 0x00000040 [6] CLK_SYS_BUSFABRIC (1) + // 0x00000020 [5] CLK_SYS_BUSCTRL (1) + // 0x00000010 [4] CLK_SYS_BOOTRAM (1) + // 0x00000008 [3] CLK_SYS_ADC (1) + // 0x00000004 [2] CLK_ADC (1) + // 0x00000002 [1] CLK_SYS_ACCESSCTRL (1) + // 0x00000001 [0] CLK_SYS_CLOCKS (1) + io_rw_32 wake_en[2]; + }; + + union { + struct { + _REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0 + // enable clock in sleep mode + // 0x80000000 [31] CLK_SYS_SIOB (1) + // 0x40000000 [30] CLK_SYS_SHA256 (1) + // 0x20000000 [29] CLK_SYS_RSM (1) + // 0x10000000 [28] CLK_SYS_ROSC (1) + // 0x08000000 [27] CLK_SYS_ROM (1) + // 0x04000000 [26] CLK_SYS_RESETS (1) + // 0x02000000 [25] CLK_SYS_PWM (1) + // 0x01000000 [24] CLK_SYS_POWMAN (1) + // 0x00800000 [23] CLK_REF_POWMAN (1) + // 0x00400000 [22] CLK_SYS_PLL_USB (1) + // 0x00200000 [21] CLK_SYS_PLL_SYS (1) + // 0x00100000 [20] CLK_SYS_PIO2 (1) + // 0x00080000 [19] CLK_SYS_PIO1 (1) + // 0x00040000 [18] CLK_SYS_PIO0 (1) + // 0x00020000 [17] CLK_SYS_PADS (1) + // 0x00010000 [16] CLK_SYS_OTP (1) + // 0x00008000 [15] CLK_REF_OTP (1) + // 0x00004000 [14] CLK_SYS_JTAG (1) + // 0x00002000 [13] CLK_SYS_IO (1) + // 0x00001000 [12] CLK_SYS_I2C1 (1) + // 0x00000800 [11] CLK_SYS_I2C0 (1) + // 0x00000400 [10] CLK_SYS_HSTX (1) + // 0x00000200 [9] CLK_HSTX (1) + // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (1) + // 0x00000080 [7] CLK_SYS_DMA (1) + // 0x00000040 [6] CLK_SYS_BUSFABRIC (1) + // 0x00000020 [5] CLK_SYS_BUSCTRL (1) + // 0x00000010 [4] CLK_SYS_BOOTRAM (1) + // 0x00000008 [3] CLK_SYS_ADC (1) + // 0x00000004 [2] CLK_ADC (1) + // 0x00000002 [1] CLK_SYS_ACCESSCTRL (1) + // 0x00000001 [0] CLK_SYS_CLOCKS (1) + io_rw_32 sleep_en0; + + _REG_(CLOCKS_SLEEP_EN1_OFFSET) // CLOCKS_SLEEP_EN1 + // enable clock in sleep mode + // 0x40000000 [30] CLK_SYS_XOSC (1) + // 0x20000000 [29] CLK_SYS_XIP (1) + // 0x10000000 [28] CLK_SYS_WATCHDOG (1) + // 0x08000000 [27] CLK_USB (1) + // 0x04000000 [26] CLK_SYS_USBCTRL (1) + // 0x02000000 [25] CLK_SYS_UART1 (1) + // 0x01000000 [24] CLK_PERI_UART1 (1) + // 0x00800000 [23] CLK_SYS_UART0 (1) + // 0x00400000 [22] CLK_PERI_UART0 (1) + // 0x00200000 [21] CLK_SYS_TRNG (1) + // 0x00100000 [20] CLK_SYS_TIMER1 (1) + // 0x00080000 [19] CLK_SYS_TIMER0 (1) + // 0x00040000 [18] CLK_SYS_TICKS (1) + // 0x00020000 [17] CLK_REF_TICKS (1) + // 0x00010000 [16] CLK_SYS_TBMAN (1) + // 0x00008000 [15] CLK_SYS_SYSINFO (1) + // 0x00004000 [14] CLK_SYS_SYSCFG (1) + // 0x00002000 [13] CLK_SYS_SRAM9 (1) + // 0x00001000 [12] CLK_SYS_SRAM8 (1) + // 0x00000800 [11] CLK_SYS_SRAM7 (1) + // 0x00000400 [10] CLK_SYS_SRAM6 (1) + // 0x00000200 [9] CLK_SYS_SRAM5 (1) + // 0x00000100 [8] CLK_SYS_SRAM4 (1) + // 0x00000080 [7] CLK_SYS_SRAM3 (1) + // 0x00000040 [6] CLK_SYS_SRAM2 (1) + // 0x00000020 [5] CLK_SYS_SRAM1 (1) + // 0x00000010 [4] CLK_SYS_SRAM0 (1) + // 0x00000008 [3] CLK_SYS_SPI1 (1) + // 0x00000004 [2] CLK_PERI_SPI1 (1) + // 0x00000002 [1] CLK_SYS_SPI0 (1) + // 0x00000001 [0] CLK_PERI_SPI0 (1) + io_rw_32 sleep_en1; + }; + // (Description copied from array index 0 register CLOCKS_SLEEP_EN0 applies similarly to other array indexes) + _REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0 + // enable clock in sleep mode + // 0x80000000 [31] CLK_SYS_SIO (1) + // 0x40000000 [30] CLK_SYS_SHA256 (1) + // 0x20000000 [29] CLK_SYS_PSM (1) + // 0x10000000 [28] CLK_SYS_ROSC (1) + // 0x08000000 [27] CLK_SYS_ROM (1) + // 0x04000000 [26] CLK_SYS_RESETS (1) + // 0x02000000 [25] CLK_SYS_PWM (1) + // 0x01000000 [24] CLK_SYS_POWMAN (1) + // 0x00800000 [23] CLK_REF_POWMAN (1) + // 0x00400000 [22] CLK_SYS_PLL_USB (1) + // 0x00200000 [21] CLK_SYS_PLL_SYS (1) + // 0x00100000 [20] CLK_SYS_PIO2 (1) + // 0x00080000 [19] CLK_SYS_PIO1 (1) + // 0x00040000 [18] CLK_SYS_PIO0 (1) + // 0x00020000 [17] CLK_SYS_PADS (1) + // 0x00010000 [16] CLK_SYS_OTP (1) + // 0x00008000 [15] CLK_REF_OTP (1) + // 0x00004000 [14] CLK_SYS_JTAG (1) + // 0x00002000 [13] CLK_SYS_IO (1) + // 0x00001000 [12] CLK_SYS_I2C1 (1) + // 0x00000800 [11] CLK_SYS_I2C0 (1) + // 0x00000400 [10] CLK_SYS_HSTX (1) + // 0x00000200 [9] CLK_HSTX (1) + // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (1) + // 0x00000080 [7] CLK_SYS_DMA (1) + // 0x00000040 [6] CLK_SYS_BUSFABRIC (1) + // 0x00000020 [5] CLK_SYS_BUSCTRL (1) + // 0x00000010 [4] CLK_SYS_BOOTRAM (1) + // 0x00000008 [3] CLK_SYS_ADC (1) + // 0x00000004 [2] CLK_ADC (1) + // 0x00000002 [1] CLK_SYS_ACCESSCTRL (1) + // 0x00000001 [0] CLK_SYS_CLOCKS (1) + io_rw_32 sleep_en[2]; + }; + + union { + struct { + _REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0 + // indicates the state of the clock enable + // 0x80000000 [31] CLK_SYS_SIOB (0) + // 0x40000000 [30] CLK_SYS_SHA256 (0) + // 0x20000000 [29] CLK_SYS_RSM (0) + // 0x10000000 [28] CLK_SYS_ROSC (0) + // 0x08000000 [27] CLK_SYS_ROM (0) + // 0x04000000 [26] CLK_SYS_RESETS (0) + // 0x02000000 [25] CLK_SYS_PWM (0) + // 0x01000000 [24] CLK_SYS_POWMAN (0) + // 0x00800000 [23] CLK_REF_POWMAN (0) + // 0x00400000 [22] CLK_SYS_PLL_USB (0) + // 0x00200000 [21] CLK_SYS_PLL_SYS (0) + // 0x00100000 [20] CLK_SYS_PIO2 (0) + // 0x00080000 [19] CLK_SYS_PIO1 (0) + // 0x00040000 [18] CLK_SYS_PIO0 (0) + // 0x00020000 [17] CLK_SYS_PADS (0) + // 0x00010000 [16] CLK_SYS_OTP (0) + // 0x00008000 [15] CLK_REF_OTP (0) + // 0x00004000 [14] CLK_SYS_JTAG (0) + // 0x00002000 [13] CLK_SYS_IO (0) + // 0x00001000 [12] CLK_SYS_I2C1 (0) + // 0x00000800 [11] CLK_SYS_I2C0 (0) + // 0x00000400 [10] CLK_SYS_HSTX (0) + // 0x00000200 [9] CLK_HSTX (0) + // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (0) + // 0x00000080 [7] CLK_SYS_DMA (0) + // 0x00000040 [6] CLK_SYS_BUSFABRIC (0) + // 0x00000020 [5] CLK_SYS_BUSCTRL (0) + // 0x00000010 [4] CLK_SYS_BOOTRAM (0) + // 0x00000008 [3] CLK_SYS_ADC (0) + // 0x00000004 [2] CLK_ADC (0) + // 0x00000002 [1] CLK_SYS_ACCESSCTRL (0) + // 0x00000001 [0] CLK_SYS_CLOCKS (0) + io_ro_32 enabled0; + + _REG_(CLOCKS_ENABLED1_OFFSET) // CLOCKS_ENABLED1 + // indicates the state of the clock enable + // 0x40000000 [30] CLK_SYS_XOSC (0) + // 0x20000000 [29] CLK_SYS_XIP (0) + // 0x10000000 [28] CLK_SYS_WATCHDOG (0) + // 0x08000000 [27] CLK_USB (0) + // 0x04000000 [26] CLK_SYS_USBCTRL (0) + // 0x02000000 [25] CLK_SYS_UART1 (0) + // 0x01000000 [24] CLK_PERI_UART1 (0) + // 0x00800000 [23] CLK_SYS_UART0 (0) + // 0x00400000 [22] CLK_PERI_UART0 (0) + // 0x00200000 [21] CLK_SYS_TRNG (0) + // 0x00100000 [20] CLK_SYS_TIMER1 (0) + // 0x00080000 [19] CLK_SYS_TIMER0 (0) + // 0x00040000 [18] CLK_SYS_TICKS (0) + // 0x00020000 [17] CLK_REF_TICKS (0) + // 0x00010000 [16] CLK_SYS_TBMAN (0) + // 0x00008000 [15] CLK_SYS_SYSINFO (0) + // 0x00004000 [14] CLK_SYS_SYSCFG (0) + // 0x00002000 [13] CLK_SYS_SRAM9 (0) + // 0x00001000 [12] CLK_SYS_SRAM8 (0) + // 0x00000800 [11] CLK_SYS_SRAM7 (0) + // 0x00000400 [10] CLK_SYS_SRAM6 (0) + // 0x00000200 [9] CLK_SYS_SRAM5 (0) + // 0x00000100 [8] CLK_SYS_SRAM4 (0) + // 0x00000080 [7] CLK_SYS_SRAM3 (0) + // 0x00000040 [6] CLK_SYS_SRAM2 (0) + // 0x00000020 [5] CLK_SYS_SRAM1 (0) + // 0x00000010 [4] CLK_SYS_SRAM0 (0) + // 0x00000008 [3] CLK_SYS_SPI1 (0) + // 0x00000004 [2] CLK_PERI_SPI1 (0) + // 0x00000002 [1] CLK_SYS_SPI0 (0) + // 0x00000001 [0] CLK_PERI_SPI0 (0) + io_ro_32 enabled1; + }; + // (Description copied from array index 0 register CLOCKS_ENABLED0 applies similarly to other array indexes) + _REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0 + // indicates the state of the clock enable + // 0x80000000 [31] CLK_SYS_SIO (0) + // 0x40000000 [30] CLK_SYS_SHA256 (0) + // 0x20000000 [29] CLK_SYS_PSM (0) + // 0x10000000 [28] CLK_SYS_ROSC (0) + // 0x08000000 [27] CLK_SYS_ROM (0) + // 0x04000000 [26] CLK_SYS_RESETS (0) + // 0x02000000 [25] CLK_SYS_PWM (0) + // 0x01000000 [24] CLK_SYS_POWMAN (0) + // 0x00800000 [23] CLK_REF_POWMAN (0) + // 0x00400000 [22] CLK_SYS_PLL_USB (0) + // 0x00200000 [21] CLK_SYS_PLL_SYS (0) + // 0x00100000 [20] CLK_SYS_PIO2 (0) + // 0x00080000 [19] CLK_SYS_PIO1 (0) + // 0x00040000 [18] CLK_SYS_PIO0 (0) + // 0x00020000 [17] CLK_SYS_PADS (0) + // 0x00010000 [16] CLK_SYS_OTP (0) + // 0x00008000 [15] CLK_REF_OTP (0) + // 0x00004000 [14] CLK_SYS_JTAG (0) + // 0x00002000 [13] CLK_SYS_IO (0) + // 0x00001000 [12] CLK_SYS_I2C1 (0) + // 0x00000800 [11] CLK_SYS_I2C0 (0) + // 0x00000400 [10] CLK_SYS_HSTX (0) + // 0x00000200 [9] CLK_HSTX (0) + // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (0) + // 0x00000080 [7] CLK_SYS_DMA (0) + // 0x00000040 [6] CLK_SYS_BUSFABRIC (0) + // 0x00000020 [5] CLK_SYS_BUSCTRL (0) + // 0x00000010 [4] CLK_SYS_BOOTRAM (0) + // 0x00000008 [3] CLK_SYS_ADC (0) + // 0x00000004 [2] CLK_ADC (0) + // 0x00000002 [1] CLK_SYS_ACCESSCTRL (0) + // 0x00000001 [0] CLK_SYS_CLOCKS (0) + io_ro_32 enabled[2]; + }; + + _REG_(CLOCKS_INTR_OFFSET) // CLOCKS_INTR + // Raw Interrupts + // 0x00000001 [0] CLK_SYS_RESUS (0) + io_ro_32 intr; + + _REG_(CLOCKS_INTE_OFFSET) // CLOCKS_INTE + // Interrupt Enable + // 0x00000001 [0] CLK_SYS_RESUS (0) + io_rw_32 inte; + + _REG_(CLOCKS_INTF_OFFSET) // CLOCKS_INTF + // Interrupt Force + // 0x00000001 [0] CLK_SYS_RESUS (0) + io_rw_32 intf; + + _REG_(CLOCKS_INTS_OFFSET) // CLOCKS_INTS + // Interrupt status after masking & forcing + // 0x00000001 [0] CLK_SYS_RESUS (0) + io_ro_32 ints; +} clocks_hw_t; + +#define clocks_hw ((clocks_hw_t *)CLOCKS_BASE) +static_assert(sizeof (clocks_hw_t) == 0x00d4, ""); + +#endif // _HARDWARE_STRUCTS_CLOCKS_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/coresight_trace.h b/lib/pico-sdk/rp2350/hardware/structs/coresight_trace.h new file mode 100644 index 00000000..61ffb062 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/coresight_trace.h @@ -0,0 +1,43 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_CORESIGHT_TRACE_H +#define _HARDWARE_STRUCTS_CORESIGHT_TRACE_H + +/** + * \file rp2350/coresight_trace.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/coresight_trace.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_coresight_trace +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/coresight_trace.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(CORESIGHT_TRACE_CTRL_STATUS_OFFSET) // CORESIGHT_TRACE_CTRL_STATUS + // Control and status register + // 0x00000002 [1] TRACE_CAPTURE_FIFO_OVERFLOW (0) This status flag is set high when trace data has been... + // 0x00000001 [0] TRACE_CAPTURE_FIFO_FLUSH (1) Set to 1 to continuously hold the trace FIFO in a... + io_rw_32 ctrl_status; + + _REG_(CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_OFFSET) // CORESIGHT_TRACE_TRACE_CAPTURE_FIFO + // FIFO for trace data captured from the TPIU + // 0xffffffff [31:0] RDATA (0x00000000) Read from an 8 x 32-bit FIFO containing trace data... + io_ro_32 trace_capture_fifo; +} coresight_trace_hw_t; + +#define coresight_trace_hw ((coresight_trace_hw_t *)CORESIGHT_TRACE_BASE) +static_assert(sizeof (coresight_trace_hw_t) == 0x0008, ""); + +#endif // _HARDWARE_STRUCTS_CORESIGHT_TRACE_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/dma.h b/lib/pico-sdk/rp2350/hardware/structs/dma.h new file mode 100644 index 00000000..6097a984 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/dma.h @@ -0,0 +1,336 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_DMA_H +#define _HARDWARE_STRUCTS_DMA_H + +/** + * \file rp2350/dma.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/dma.h" +#include "hardware/structs/dma_debug.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_dma +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/dma.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(DMA_CH0_READ_ADDR_OFFSET) // DMA_CH0_READ_ADDR + // DMA Channel 0 Read Address pointer + // 0xffffffff [31:0] CH0_READ_ADDR (0x00000000) This register updates automatically each time a read completes + io_rw_32 read_addr; + + _REG_(DMA_CH0_WRITE_ADDR_OFFSET) // DMA_CH0_WRITE_ADDR + // DMA Channel 0 Write Address pointer + // 0xffffffff [31:0] CH0_WRITE_ADDR (0x00000000) This register updates automatically each time a write completes + io_rw_32 write_addr; + + _REG_(DMA_CH0_TRANS_COUNT_OFFSET) // DMA_CH0_TRANS_COUNT + // DMA Channel 0 Transfer Count + // 0xf0000000 [31:28] MODE (0x0) When MODE is 0x0, the transfer count decrements with... + // 0x0fffffff [27:0] COUNT (0x0000000) 28-bit transfer count (256 million transfers maximum) + io_rw_32 transfer_count; + + _REG_(DMA_CH0_CTRL_TRIG_OFFSET) // DMA_CH0_CTRL_TRIG + // DMA Channel 0 Control and Status + // 0x80000000 [31] AHB_ERROR (0) Logical OR of the READ_ERROR and WRITE_ERROR flags + // 0x40000000 [30] READ_ERROR (0) If 1, the channel received a read bus error + // 0x20000000 [29] WRITE_ERROR (0) If 1, the channel received a write bus error + // 0x04000000 [26] BUSY (0) This flag goes high when the channel starts a new... + // 0x02000000 [25] SNIFF_EN (0) If 1, this channel's data transfers are visible to the... + // 0x01000000 [24] BSWAP (0) Apply byte-swap transformation to DMA data + // 0x00800000 [23] IRQ_QUIET (0) In QUIET mode, the channel does not generate IRQs at the... + // 0x007e0000 [22:17] TREQ_SEL (0x00) Select a Transfer Request signal + // 0x0001e000 [16:13] CHAIN_TO (0x0) When this channel completes, it will trigger the channel... + // 0x00001000 [12] RING_SEL (0) Select whether RING_SIZE applies to read or write addresses + // 0x00000f00 [11:8] RING_SIZE (0x0) Size of address wrap region + // 0x00000080 [7] INCR_WRITE_REV (0) If 1, and INCR_WRITE is 1, the write address is... + // 0x00000040 [6] INCR_WRITE (0) If 1, the write address increments with each transfer + // 0x00000020 [5] INCR_READ_REV (0) If 1, and INCR_READ is 1, the read address is... + // 0x00000010 [4] INCR_READ (0) If 1, the read address increments with each transfer + // 0x0000000c [3:2] DATA_SIZE (0x0) Set the size of each bus transfer (byte/halfword/word) + // 0x00000002 [1] HIGH_PRIORITY (0) HIGH_PRIORITY gives a channel preferential treatment in... + // 0x00000001 [0] EN (0) DMA Channel Enable + io_rw_32 ctrl_trig; + + _REG_(DMA_CH0_AL1_CTRL_OFFSET) // DMA_CH0_AL1_CTRL + // Alias for channel 0 CTRL register + // 0xffffffff [31:0] CH0_AL1_CTRL (-) + io_rw_32 al1_ctrl; + + _REG_(DMA_CH0_AL1_READ_ADDR_OFFSET) // DMA_CH0_AL1_READ_ADDR + // Alias for channel 0 READ_ADDR register + // 0xffffffff [31:0] CH0_AL1_READ_ADDR (-) + io_rw_32 al1_read_addr; + + _REG_(DMA_CH0_AL1_WRITE_ADDR_OFFSET) // DMA_CH0_AL1_WRITE_ADDR + // Alias for channel 0 WRITE_ADDR register + // 0xffffffff [31:0] CH0_AL1_WRITE_ADDR (-) + io_rw_32 al1_write_addr; + + _REG_(DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET) // DMA_CH0_AL1_TRANS_COUNT_TRIG + // Alias for channel 0 TRANS_COUNT register + + // 0xffffffff [31:0] CH0_AL1_TRANS_COUNT_TRIG (-) + io_rw_32 al1_transfer_count_trig; + + _REG_(DMA_CH0_AL2_CTRL_OFFSET) // DMA_CH0_AL2_CTRL + // Alias for channel 0 CTRL register + // 0xffffffff [31:0] CH0_AL2_CTRL (-) + io_rw_32 al2_ctrl; + + _REG_(DMA_CH0_AL2_TRANS_COUNT_OFFSET) // DMA_CH0_AL2_TRANS_COUNT + // Alias for channel 0 TRANS_COUNT register + // 0xffffffff [31:0] CH0_AL2_TRANS_COUNT (-) + io_rw_32 al2_transfer_count; + + _REG_(DMA_CH0_AL2_READ_ADDR_OFFSET) // DMA_CH0_AL2_READ_ADDR + // Alias for channel 0 READ_ADDR register + // 0xffffffff [31:0] CH0_AL2_READ_ADDR (-) + io_rw_32 al2_read_addr; + + _REG_(DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET) // DMA_CH0_AL2_WRITE_ADDR_TRIG + // Alias for channel 0 WRITE_ADDR register + + // 0xffffffff [31:0] CH0_AL2_WRITE_ADDR_TRIG (-) + io_rw_32 al2_write_addr_trig; + + _REG_(DMA_CH0_AL3_CTRL_OFFSET) // DMA_CH0_AL3_CTRL + // Alias for channel 0 CTRL register + // 0xffffffff [31:0] CH0_AL3_CTRL (-) + io_rw_32 al3_ctrl; + + _REG_(DMA_CH0_AL3_WRITE_ADDR_OFFSET) // DMA_CH0_AL3_WRITE_ADDR + // Alias for channel 0 WRITE_ADDR register + // 0xffffffff [31:0] CH0_AL3_WRITE_ADDR (-) + io_rw_32 al3_write_addr; + + _REG_(DMA_CH0_AL3_TRANS_COUNT_OFFSET) // DMA_CH0_AL3_TRANS_COUNT + // Alias for channel 0 TRANS_COUNT register + // 0xffffffff [31:0] CH0_AL3_TRANS_COUNT (-) + io_rw_32 al3_transfer_count; + + _REG_(DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET) // DMA_CH0_AL3_READ_ADDR_TRIG + // Alias for channel 0 READ_ADDR register + + // 0xffffffff [31:0] CH0_AL3_READ_ADDR_TRIG (-) + io_rw_32 al3_read_addr_trig; +} dma_channel_hw_t; + +typedef struct { + _REG_(DMA_MPU_BAR0_OFFSET) // DMA_MPU_BAR0 + // Base address register for MPU region 0 + // 0xffffffe0 [31:5] ADDR (0x0000000) This MPU region matches addresses where addr[31:5] (the... + io_rw_32 bar; + + _REG_(DMA_MPU_LAR0_OFFSET) // DMA_MPU_LAR0 + // Limit address register for MPU region 0 + // 0xffffffe0 [31:5] ADDR (0x0000000) Limit address bits 31:5 + // 0x00000004 [2] S (0) Determines the Secure/Non-secure (=1/0) status of... + // 0x00000002 [1] P (0) Determines the Privileged/Unprivileged (=1/0) status of... + // 0x00000001 [0] EN (0) Region enable + io_rw_32 lar; +} dma_mpu_region_hw_t; + +typedef struct { + _REG_(DMA_INTR_OFFSET) // DMA_INTR + // Interrupt Status (raw) + // 0x0000ffff [15:0] INTR (0x0000) Raw interrupt status for DMA Channels 0 + io_rw_32 intr; + + _REG_(DMA_INTE0_OFFSET) // DMA_INTE0 + // Interrupt Enables for IRQ 0 + // 0x0000ffff [15:0] INTE0 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0 + io_rw_32 inte; + + _REG_(DMA_INTF0_OFFSET) // DMA_INTF0 + // Force Interrupts + // 0x0000ffff [15:0] INTF0 (0x0000) Write 1s to force the corresponding bits in INTS0 + io_rw_32 intf; + + _REG_(DMA_INTS0_OFFSET) // DMA_INTS0 + // Interrupt Status for IRQ 0 + // 0x0000ffff [15:0] INTS0 (0x0000) Indicates active channel interrupt requests which are... + io_rw_32 ints; +} dma_irq_ctrl_hw_t; + +typedef struct { + dma_channel_hw_t ch[16]; + + union { + struct { + _REG_(DMA_INTR_OFFSET) // DMA_INTR + // Interrupt Status (raw) + // 0x0000ffff [15:0] INTR (0x0000) Raw interrupt status for DMA Channels 0 + io_rw_32 intr; + + _REG_(DMA_INTE0_OFFSET) // DMA_INTE0 + // Interrupt Enables for IRQ 0 + // 0x0000ffff [15:0] INTE0 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0 + io_rw_32 inte0; + + _REG_(DMA_INTF0_OFFSET) // DMA_INTF0 + // Force Interrupts + // 0x0000ffff [15:0] INTF0 (0x0000) Write 1s to force the corresponding bits in INTE0 + io_rw_32 intf0; + + _REG_(DMA_INTS0_OFFSET) // DMA_INTS0 + // Interrupt Status for IRQ 0 + // 0x0000ffff [15:0] INTS0 (0x0000) Indicates active channel interrupt requests which are... + io_rw_32 ints0; + + uint32_t __pad0; + + _REG_(DMA_INTE1_OFFSET) // DMA_INTE1 + // Interrupt Enables for IRQ 1 + // 0x0000ffff [15:0] INTE1 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 1 + io_rw_32 inte1; + + _REG_(DMA_INTF1_OFFSET) // DMA_INTF1 + // Force Interrupts for IRQ 1 + // 0x0000ffff [15:0] INTF1 (0x0000) Write 1s to force the corresponding bits in INTF1 + io_rw_32 intf1; + + _REG_(DMA_INTS1_OFFSET) // DMA_INTS1 + // Interrupt Status (masked) for IRQ 1 + // 0x0000ffff [15:0] INTS1 (0x0000) Indicates active channel interrupt requests which are... + io_rw_32 ints1; + + uint32_t __pad1; + + _REG_(DMA_INTE2_OFFSET) // DMA_INTE2 + // Interrupt Enables for IRQ 2 + // 0x0000ffff [15:0] INTE2 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 2 + io_rw_32 inte2; + + _REG_(DMA_INTF2_OFFSET) // DMA_INTF2 + // Force Interrupts for IRQ 2 + // 0x0000ffff [15:0] INTF2 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 2 + io_rw_32 intf2; + + _REG_(DMA_INTS2_OFFSET) // DMA_INTS2 + // Interrupt Status (masked) for IRQ 2 + // 0x0000ffff [15:0] INTS2 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 2 + io_rw_32 ints2; + + uint32_t __pad2; + + _REG_(DMA_INTE3_OFFSET) // DMA_INTE3 + // Interrupt Enables for IRQ 3 + // 0x0000ffff [15:0] INTE3 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 3 + io_rw_32 inte3; + + _REG_(DMA_INTF3_OFFSET) // DMA_INTF3 + // Force Interrupts for IRQ 3 + // 0x0000ffff [15:0] INTF3 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 3 + io_rw_32 intf3; + + _REG_(DMA_INTS3_OFFSET) // DMA_INTS3 + // Interrupt Status (masked) for IRQ 3 + // 0x0000ffff [15:0] INTS3 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 3 + io_rw_32 ints3; + }; + dma_irq_ctrl_hw_t irq_ctrl[4]; + }; + + // (Description copied from array index 0 register DMA_TIMER0 applies similarly to other array indexes) + _REG_(DMA_TIMER0_OFFSET) // DMA_TIMER0 + // Pacing timer (generate periodic TREQs) + // 0xffff0000 [31:16] X (0x0000) Pacing Timer Dividend + // 0x0000ffff [15:0] Y (0x0000) Pacing Timer Divisor + io_rw_32 timer[4]; + + _REG_(DMA_MULTI_CHAN_TRIGGER_OFFSET) // DMA_MULTI_CHAN_TRIGGER + // Trigger one or more channels simultaneously + // 0x0000ffff [15:0] MULTI_CHAN_TRIGGER (0x0000) Each bit in this register corresponds to a DMA channel + io_wo_32 multi_channel_trigger; + + _REG_(DMA_SNIFF_CTRL_OFFSET) // DMA_SNIFF_CTRL + // Sniffer Control + // 0x00000800 [11] OUT_INV (0) If set, the result appears inverted (bitwise complement)... + // 0x00000400 [10] OUT_REV (0) If set, the result appears bit-reversed when read + // 0x00000200 [9] BSWAP (0) Locally perform a byte reverse on the sniffed data,... + // 0x000001e0 [8:5] CALC (0x0) + // 0x0000001e [4:1] DMACH (0x0) DMA channel for Sniffer to observe + // 0x00000001 [0] EN (0) Enable sniffer + io_rw_32 sniff_ctrl; + + _REG_(DMA_SNIFF_DATA_OFFSET) // DMA_SNIFF_DATA + // Data accumulator for sniff hardware + // 0xffffffff [31:0] SNIFF_DATA (0x00000000) Write an initial seed value here before starting a DMA... + io_rw_32 sniff_data; + + uint32_t _pad0; + + _REG_(DMA_FIFO_LEVELS_OFFSET) // DMA_FIFO_LEVELS + // Debug RAF, WAF, TDF levels + // 0x00ff0000 [23:16] RAF_LVL (0x00) Current Read-Address-FIFO fill level + // 0x0000ff00 [15:8] WAF_LVL (0x00) Current Write-Address-FIFO fill level + // 0x000000ff [7:0] TDF_LVL (0x00) Current Transfer-Data-FIFO fill level + io_ro_32 fifo_levels; + + _REG_(DMA_CHAN_ABORT_OFFSET) // DMA_CHAN_ABORT + // Abort an in-progress transfer sequence on one or more channels + // 0x0000ffff [15:0] CHAN_ABORT (0x0000) Each bit corresponds to a channel + io_wo_32 abort; + + _REG_(DMA_N_CHANNELS_OFFSET) // DMA_N_CHANNELS + // The number of channels this DMA instance is equipped with + // 0x0000001f [4:0] N_CHANNELS (-) + io_ro_32 n_channels; + + uint32_t _pad1[5]; + + // (Description copied from array index 0 register DMA_SECCFG_CH0 applies similarly to other array indexes) + _REG_(DMA_SECCFG_CH0_OFFSET) // DMA_SECCFG_CH0 + // Security level configuration for channel 0. + // 0x00000004 [2] LOCK (0) LOCK is 0 at reset, and is set to 1 automatically upon a... + // 0x00000002 [1] S (1) Secure channel + // 0x00000001 [0] P (1) Privileged channel + io_rw_32 seccfg_ch[16]; + + // (Description copied from array index 0 register DMA_SECCFG_IRQ0 applies similarly to other array indexes) + _REG_(DMA_SECCFG_IRQ0_OFFSET) // DMA_SECCFG_IRQ0 + // Security configuration for IRQ 0 + // 0x00000002 [1] S (1) Secure IRQ + // 0x00000001 [0] P (1) Privileged IRQ + io_rw_32 seccfg_irq[4]; + + _REG_(DMA_SECCFG_MISC_OFFSET) // DMA_SECCFG_MISC + // Miscellaneous security configuration + // 0x00000200 [9] TIMER3_S (1) If 1, the TIMER3 register is only accessible from a... + // 0x00000100 [8] TIMER3_P (1) If 1, the TIMER3 register is only accessible from a... + // 0x00000080 [7] TIMER2_S (1) If 1, the TIMER2 register is only accessible from a... + // 0x00000040 [6] TIMER2_P (1) If 1, the TIMER2 register is only accessible from a... + // 0x00000020 [5] TIMER1_S (1) If 1, the TIMER1 register is only accessible from a... + // 0x00000010 [4] TIMER1_P (1) If 1, the TIMER1 register is only accessible from a... + // 0x00000008 [3] TIMER0_S (1) If 1, the TIMER0 register is only accessible from a... + // 0x00000004 [2] TIMER0_P (1) If 1, the TIMER0 register is only accessible from a... + // 0x00000002 [1] SNIFF_S (1) If 1, the sniffer can see data transfers from Secure... + // 0x00000001 [0] SNIFF_P (1) If 1, the sniffer can see data transfers from Privileged... + io_rw_32 seccfg_misc; + + uint32_t _pad2[11]; + + _REG_(DMA_MPU_CTRL_OFFSET) // DMA_MPU_CTRL + // Control register for DMA MPU + // 0x00000008 [3] NS_HIDE_ADDR (0) By default, when a region's S bit is clear,... + // 0x00000004 [2] S (0) Determine whether an address not covered by an active... + // 0x00000002 [1] P (0) Determine whether an address not covered by an active... + io_rw_32 mpu_ctrl; + + dma_mpu_region_hw_t mpu_region[8]; +} dma_hw_t; + +#define dma_hw ((dma_hw_t *)DMA_BASE) +static_assert(sizeof (dma_hw_t) == 0x0544, ""); + +#endif // _HARDWARE_STRUCTS_DMA_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/dma_debug.h b/lib/pico-sdk/rp2350/hardware/structs/dma_debug.h new file mode 100644 index 00000000..73c8bf43 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/dma_debug.h @@ -0,0 +1,47 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_DMA_DEBUG_H +#define _HARDWARE_STRUCTS_DMA_DEBUG_H + +/** + * \file rp2350/dma_debug.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/dma.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_dma +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/dma.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(DMA_CH0_DBG_CTDREQ_OFFSET) // DMA_CH0_DBG_CTDREQ + // Read: get channel DREQ counter (i + // 0x0000003f [5:0] CH0_DBG_CTDREQ (0x00) + io_rw_32 dbg_ctdreq; + + _REG_(DMA_CH0_DBG_TCR_OFFSET) // DMA_CH0_DBG_TCR + // Read to get channel TRANS_COUNT reload value, i + // 0xffffffff [31:0] CH0_DBG_TCR (0x00000000) + io_ro_32 dbg_tcr; + + uint32_t _pad0[14]; +} dma_debug_channel_hw_t; + +typedef struct { + dma_debug_channel_hw_t ch[16]; +} dma_debug_hw_t; + +#define dma_debug_hw ((dma_debug_hw_t *)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET)) + +#endif // _HARDWARE_STRUCTS_DMA_DEBUG_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/glitch_detector.h b/lib/pico-sdk/rp2350/hardware/structs/glitch_detector.h new file mode 100644 index 00000000..f25ebb23 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/glitch_detector.h @@ -0,0 +1,71 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_GLITCH_DETECTOR_H +#define _HARDWARE_STRUCTS_GLITCH_DETECTOR_H + +/** + * \file rp2350/glitch_detector.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/glitch_detector.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_glitch_detector +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/glitch_detector.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(GLITCH_DETECTOR_ARM_OFFSET) // GLITCH_DETECTOR_ARM + // Forcibly arm the glitch detectors, if they are not already armed by OTP + // 0x0000ffff [15:0] ARM (0x5bad) + io_rw_32 arm; + + _REG_(GLITCH_DETECTOR_DISARM_OFFSET) // GLITCH_DETECTOR_DISARM + // 0x0000ffff [15:0] DISARM (0x0000) Forcibly disarm the glitch detectors, if they are armed by OTP + io_rw_32 disarm; + + _REG_(GLITCH_DETECTOR_SENSITIVITY_OFFSET) // GLITCH_DETECTOR_SENSITIVITY + // Adjust the sensitivity of glitch detectors to values other than their OTP-provided defaults + // 0xff000000 [31:24] DEFAULT (0x00) + // 0x0000c000 [15:14] DET3_INV (0x0) Must be the inverse of DET3, else the default value is used + // 0x00003000 [13:12] DET2_INV (0x0) Must be the inverse of DET2, else the default value is used + // 0x00000c00 [11:10] DET1_INV (0x0) Must be the inverse of DET1, else the default value is used + // 0x00000300 [9:8] DET0_INV (0x0) Must be the inverse of DET0, else the default value is used + // 0x000000c0 [7:6] DET3 (0x0) Set sensitivity for detector 3 + // 0x00000030 [5:4] DET2 (0x0) Set sensitivity for detector 2 + // 0x0000000c [3:2] DET1 (0x0) Set sensitivity for detector 1 + // 0x00000003 [1:0] DET0 (0x0) Set sensitivity for detector 0 + io_rw_32 sensitivity; + + _REG_(GLITCH_DETECTOR_LOCK_OFFSET) // GLITCH_DETECTOR_LOCK + // 0x000000ff [7:0] LOCK (0x00) Write any nonzero value to disable writes to ARM,... + io_rw_32 lock; + + _REG_(GLITCH_DETECTOR_TRIG_STATUS_OFFSET) // GLITCH_DETECTOR_TRIG_STATUS + // Set when a detector output triggers + // 0x00000008 [3] DET3 (0) + // 0x00000004 [2] DET2 (0) + // 0x00000002 [1] DET1 (0) + // 0x00000001 [0] DET0 (0) + io_rw_32 trig_status; + + _REG_(GLITCH_DETECTOR_TRIG_FORCE_OFFSET) // GLITCH_DETECTOR_TRIG_FORCE + // Simulate the firing of one or more detectors + // 0x0000000f [3:0] TRIG_FORCE (0x0) + io_wo_32 trig_force; +} glitch_detector_hw_t; + +#define glitch_detector_hw ((glitch_detector_hw_t *)GLITCH_DETECTOR_BASE) +static_assert(sizeof (glitch_detector_hw_t) == 0x0018, ""); + +#endif // _HARDWARE_STRUCTS_GLITCH_DETECTOR_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/hstx_ctrl.h b/lib/pico-sdk/rp2350/hardware/structs/hstx_ctrl.h new file mode 100644 index 00000000..735ecee7 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/hstx_ctrl.h @@ -0,0 +1,70 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_HSTX_CTRL_H +#define _HARDWARE_STRUCTS_HSTX_CTRL_H + +/** + * \file rp2350/hstx_ctrl.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/hstx_ctrl.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_hstx_ctrl +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/hstx_ctrl.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(HSTX_CTRL_CSR_OFFSET) // HSTX_CTRL_CSR + // 0xf0000000 [31:28] CLKDIV (0x1) Clock period of the generated clock, measured in HSTX... + // 0x0f000000 [27:24] CLKPHASE (0x0) Set the initial phase of the generated clock + // 0x001f0000 [20:16] N_SHIFTS (0x05) Number of times to shift the shift register before... + // 0x00001f00 [12:8] SHIFT (0x06) How many bits to right-rotate the shift register by each cycle + // 0x00000060 [6:5] COUPLED_SEL (0x0) Select which PIO to use for coupled mode operation + // 0x00000010 [4] COUPLED_MODE (0) Enable the PIO-to-HSTX 1:1 connection + // 0x00000002 [1] EXPAND_EN (0) Enable the command expander + // 0x00000001 [0] EN (0) When EN is 1, the HSTX will shift out data as it appears... + io_rw_32 csr; + + // (Description copied from array index 0 register HSTX_CTRL_BIT0 applies similarly to other array indexes) + _REG_(HSTX_CTRL_BIT0_OFFSET) // HSTX_CTRL_BIT0 + // Data control register for output bit 0 + // 0x00020000 [17] CLK (0) Connect this output to the generated clock, rather than... + // 0x00010000 [16] INV (0) Invert this data output (logical NOT) + // 0x00001f00 [12:8] SEL_N (0x00) Shift register data bit select for the second half of... + // 0x0000001f [4:0] SEL_P (0x00) Shift register data bit select for the first half of the... + io_rw_32 bit[8]; + + _REG_(HSTX_CTRL_EXPAND_SHIFT_OFFSET) // HSTX_CTRL_EXPAND_SHIFT + // Configure the optional shifter inside the command expander + // 0x1f000000 [28:24] ENC_N_SHIFTS (0x01) Number of times to consume from the shift register... + // 0x001f0000 [20:16] ENC_SHIFT (0x00) How many bits to right-rotate the shift register by each... + // 0x00001f00 [12:8] RAW_N_SHIFTS (0x01) Number of times to consume from the shift register... + // 0x0000001f [4:0] RAW_SHIFT (0x00) How many bits to right-rotate the shift register by each... + io_rw_32 expand_shift; + + _REG_(HSTX_CTRL_EXPAND_TMDS_OFFSET) // HSTX_CTRL_EXPAND_TMDS + // Configure the optional TMDS encoder inside the command expander + // 0x00e00000 [23:21] L2_NBITS (0x0) Number of valid data bits for the lane 2 TMDS encoder,... + // 0x001f0000 [20:16] L2_ROT (0x00) Right-rotate applied to the current shifter data before... + // 0x0000e000 [15:13] L1_NBITS (0x0) Number of valid data bits for the lane 1 TMDS encoder,... + // 0x00001f00 [12:8] L1_ROT (0x00) Right-rotate applied to the current shifter data before... + // 0x000000e0 [7:5] L0_NBITS (0x0) Number of valid data bits for the lane 0 TMDS encoder,... + // 0x0000001f [4:0] L0_ROT (0x00) Right-rotate applied to the current shifter data before... + io_rw_32 expand_tmds; +} hstx_ctrl_hw_t; + +#define hstx_ctrl_hw ((hstx_ctrl_hw_t *)HSTX_CTRL_BASE) +static_assert(sizeof (hstx_ctrl_hw_t) == 0x002c, ""); + +#endif // _HARDWARE_STRUCTS_HSTX_CTRL_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/hstx_fifo.h b/lib/pico-sdk/rp2350/hardware/structs/hstx_fifo.h new file mode 100644 index 00000000..a8399fad --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/hstx_fifo.h @@ -0,0 +1,45 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_HSTX_FIFO_H +#define _HARDWARE_STRUCTS_HSTX_FIFO_H + +/** + * \file rp2350/hstx_fifo.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/hstx_fifo.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_hstx_fifo +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/hstx_fifo.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(HSTX_FIFO_STAT_OFFSET) // HSTX_FIFO_STAT + // FIFO status + // 0x00000400 [10] WOF (0) FIFO was written when full + // 0x00000200 [9] EMPTY (-) + // 0x00000100 [8] FULL (-) + // 0x000000ff [7:0] LEVEL (0x00) + io_rw_32 stat; + + _REG_(HSTX_FIFO_FIFO_OFFSET) // HSTX_FIFO_FIFO + // Write access to FIFO + // 0xffffffff [31:0] FIFO (0x00000000) + io_wo_32 fifo; +} hstx_fifo_hw_t; + +#define hstx_fifo_hw ((hstx_fifo_hw_t *)HSTX_FIFO_BASE) +static_assert(sizeof (hstx_fifo_hw_t) == 0x0008, ""); + +#endif // _HARDWARE_STRUCTS_HSTX_FIFO_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/i2c.h b/lib/pico-sdk/rp2350/hardware/structs/i2c.h new file mode 100644 index 00000000..7cd990db --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/i2c.h @@ -0,0 +1,338 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_I2C_H +#define _HARDWARE_STRUCTS_I2C_H + +/** + * \file rp2350/i2c.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/i2c.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_i2c +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/i2c.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(I2C_IC_CON_OFFSET) // I2C_IC_CON + // I2C Control Register + // 0x00000400 [10] STOP_DET_IF_MASTER_ACTIVE (0) Master issues the STOP_DET interrupt irrespective of... + // 0x00000200 [9] RX_FIFO_FULL_HLD_CTRL (0) This bit controls whether DW_apb_i2c should hold the bus... + // 0x00000100 [8] TX_EMPTY_CTRL (0) This bit controls the generation of the TX_EMPTY... + // 0x00000080 [7] STOP_DET_IFADDRESSED (0) In slave mode: - 1'b1: issues the STOP_DET interrupt... + // 0x00000040 [6] IC_SLAVE_DISABLE (1) This bit controls whether I2C has its slave disabled,... + // 0x00000020 [5] IC_RESTART_EN (1) Determines whether RESTART conditions may be sent when... + // 0x00000010 [4] IC_10BITADDR_MASTER (0) Controls whether the DW_apb_i2c starts its transfers in... + // 0x00000008 [3] IC_10BITADDR_SLAVE (0) When acting as a slave, this bit controls whether the... + // 0x00000006 [2:1] SPEED (0x2) These bits control at which speed the DW_apb_i2c... + // 0x00000001 [0] MASTER_MODE (1) This bit controls whether the DW_apb_i2c master is enabled + io_rw_32 con; + + _REG_(I2C_IC_TAR_OFFSET) // I2C_IC_TAR + // I2C Target Address Register + // 0x00000800 [11] SPECIAL (0) This bit indicates whether software performs a Device-ID... + // 0x00000400 [10] GC_OR_START (0) If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is... + // 0x000003ff [9:0] IC_TAR (0x055) This is the target address for any master transaction + io_rw_32 tar; + + _REG_(I2C_IC_SAR_OFFSET) // I2C_IC_SAR + // I2C Slave Address Register + // 0x000003ff [9:0] IC_SAR (0x055) The IC_SAR holds the slave address when the I2C is... + io_rw_32 sar; + + uint32_t _pad0; + + _REG_(I2C_IC_DATA_CMD_OFFSET) // I2C_IC_DATA_CMD + // I2C Rx/Tx Data Buffer and Command Register + // 0x00000800 [11] FIRST_DATA_BYTE (0) Indicates the first data byte received after the address... + // 0x00000400 [10] RESTART (0) This bit controls whether a RESTART is issued before the... + // 0x00000200 [9] STOP (0) This bit controls whether a STOP is issued after the... + // 0x00000100 [8] CMD (0) This bit controls whether a read or a write is performed + // 0x000000ff [7:0] DAT (0x00) This register contains the data to be transmitted or... + io_rw_32 data_cmd; + + _REG_(I2C_IC_SS_SCL_HCNT_OFFSET) // I2C_IC_SS_SCL_HCNT + // Standard Speed I2C Clock SCL High Count Register + // 0x0000ffff [15:0] IC_SS_SCL_HCNT (0x0028) This register must be set before any I2C bus transaction... + io_rw_32 ss_scl_hcnt; + + _REG_(I2C_IC_SS_SCL_LCNT_OFFSET) // I2C_IC_SS_SCL_LCNT + // Standard Speed I2C Clock SCL Low Count Register + // 0x0000ffff [15:0] IC_SS_SCL_LCNT (0x002f) This register must be set before any I2C bus transaction... + io_rw_32 ss_scl_lcnt; + + _REG_(I2C_IC_FS_SCL_HCNT_OFFSET) // I2C_IC_FS_SCL_HCNT + // Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register + // 0x0000ffff [15:0] IC_FS_SCL_HCNT (0x0006) This register must be set before any I2C bus transaction... + io_rw_32 fs_scl_hcnt; + + _REG_(I2C_IC_FS_SCL_LCNT_OFFSET) // I2C_IC_FS_SCL_LCNT + // Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register + // 0x0000ffff [15:0] IC_FS_SCL_LCNT (0x000d) This register must be set before any I2C bus transaction... + io_rw_32 fs_scl_lcnt; + + uint32_t _pad1[2]; + + _REG_(I2C_IC_INTR_STAT_OFFSET) // I2C_IC_INTR_STAT + // I2C Interrupt Status Register + // 0x00001000 [12] R_RESTART_DET (0) See IC_RAW_INTR_STAT for a detailed description of... + // 0x00000800 [11] R_GEN_CALL (0) See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit + // 0x00000400 [10] R_START_DET (0) See IC_RAW_INTR_STAT for a detailed description of... + // 0x00000200 [9] R_STOP_DET (0) See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit + // 0x00000100 [8] R_ACTIVITY (0) See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit + // 0x00000080 [7] R_RX_DONE (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit + // 0x00000040 [6] R_TX_ABRT (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit + // 0x00000020 [5] R_RD_REQ (0) See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit + // 0x00000010 [4] R_TX_EMPTY (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit + // 0x00000008 [3] R_TX_OVER (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit + // 0x00000004 [2] R_RX_FULL (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit + // 0x00000002 [1] R_RX_OVER (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit + // 0x00000001 [0] R_RX_UNDER (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit + io_ro_32 intr_stat; + + _REG_(I2C_IC_INTR_MASK_OFFSET) // I2C_IC_INTR_MASK + // I2C Interrupt Mask Register + // 0x00001000 [12] M_RESTART_DET (0) This bit masks the R_RESTART_DET interrupt in... + // 0x00000800 [11] M_GEN_CALL (1) This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register + // 0x00000400 [10] M_START_DET (0) This bit masks the R_START_DET interrupt in IC_INTR_STAT register + // 0x00000200 [9] M_STOP_DET (0) This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register + // 0x00000100 [8] M_ACTIVITY (0) This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register + // 0x00000080 [7] M_RX_DONE (1) This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register + // 0x00000040 [6] M_TX_ABRT (1) This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register + // 0x00000020 [5] M_RD_REQ (1) This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register + // 0x00000010 [4] M_TX_EMPTY (1) This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register + // 0x00000008 [3] M_TX_OVER (1) This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register + // 0x00000004 [2] M_RX_FULL (1) This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register + // 0x00000002 [1] M_RX_OVER (1) This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register + // 0x00000001 [0] M_RX_UNDER (1) This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register + io_rw_32 intr_mask; + + _REG_(I2C_IC_RAW_INTR_STAT_OFFSET) // I2C_IC_RAW_INTR_STAT + // I2C Raw Interrupt Status Register + // 0x00001000 [12] RESTART_DET (0) Indicates whether a RESTART condition has occurred on... + // 0x00000800 [11] GEN_CALL (0) Set only when a General Call address is received and it... + // 0x00000400 [10] START_DET (0) Indicates whether a START or RESTART condition has... + // 0x00000200 [9] STOP_DET (0) Indicates whether a STOP condition has occurred on the... + // 0x00000100 [8] ACTIVITY (0) This bit captures DW_apb_i2c activity and stays set... + // 0x00000080 [7] RX_DONE (0) When the DW_apb_i2c is acting as a slave-transmitter,... + // 0x00000040 [6] TX_ABRT (0) This bit indicates if DW_apb_i2c, as an I2C transmitter,... + // 0x00000020 [5] RD_REQ (0) This bit is set to 1 when DW_apb_i2c is acting as a... + // 0x00000010 [4] TX_EMPTY (0) The behavior of the TX_EMPTY interrupt status differs... + // 0x00000008 [3] TX_OVER (0) Set during transmit if the transmit buffer is filled to... + // 0x00000004 [2] RX_FULL (0) Set when the receive buffer reaches or goes above the... + // 0x00000002 [1] RX_OVER (0) Set if the receive buffer is completely filled to... + // 0x00000001 [0] RX_UNDER (0) Set if the processor attempts to read the receive buffer... + io_ro_32 raw_intr_stat; + + _REG_(I2C_IC_RX_TL_OFFSET) // I2C_IC_RX_TL + // I2C Receive FIFO Threshold Register + // 0x000000ff [7:0] RX_TL (0x00) Receive FIFO Threshold Level + io_rw_32 rx_tl; + + _REG_(I2C_IC_TX_TL_OFFSET) // I2C_IC_TX_TL + // I2C Transmit FIFO Threshold Register + // 0x000000ff [7:0] TX_TL (0x00) Transmit FIFO Threshold Level + io_rw_32 tx_tl; + + _REG_(I2C_IC_CLR_INTR_OFFSET) // I2C_IC_CLR_INTR + // Clear Combined and Individual Interrupt Register + // 0x00000001 [0] CLR_INTR (0) Read this register to clear the combined interrupt, all... + io_ro_32 clr_intr; + + _REG_(I2C_IC_CLR_RX_UNDER_OFFSET) // I2C_IC_CLR_RX_UNDER + // Clear RX_UNDER Interrupt Register + // 0x00000001 [0] CLR_RX_UNDER (0) Read this register to clear the RX_UNDER interrupt (bit... + io_ro_32 clr_rx_under; + + _REG_(I2C_IC_CLR_RX_OVER_OFFSET) // I2C_IC_CLR_RX_OVER + // Clear RX_OVER Interrupt Register + // 0x00000001 [0] CLR_RX_OVER (0) Read this register to clear the RX_OVER interrupt (bit... + io_ro_32 clr_rx_over; + + _REG_(I2C_IC_CLR_TX_OVER_OFFSET) // I2C_IC_CLR_TX_OVER + // Clear TX_OVER Interrupt Register + // 0x00000001 [0] CLR_TX_OVER (0) Read this register to clear the TX_OVER interrupt (bit... + io_ro_32 clr_tx_over; + + _REG_(I2C_IC_CLR_RD_REQ_OFFSET) // I2C_IC_CLR_RD_REQ + // Clear RD_REQ Interrupt Register + // 0x00000001 [0] CLR_RD_REQ (0) Read this register to clear the RD_REQ interrupt (bit 5)... + io_ro_32 clr_rd_req; + + _REG_(I2C_IC_CLR_TX_ABRT_OFFSET) // I2C_IC_CLR_TX_ABRT + // Clear TX_ABRT Interrupt Register + // 0x00000001 [0] CLR_TX_ABRT (0) Read this register to clear the TX_ABRT interrupt (bit... + io_ro_32 clr_tx_abrt; + + _REG_(I2C_IC_CLR_RX_DONE_OFFSET) // I2C_IC_CLR_RX_DONE + // Clear RX_DONE Interrupt Register + // 0x00000001 [0] CLR_RX_DONE (0) Read this register to clear the RX_DONE interrupt (bit... + io_ro_32 clr_rx_done; + + _REG_(I2C_IC_CLR_ACTIVITY_OFFSET) // I2C_IC_CLR_ACTIVITY + // Clear ACTIVITY Interrupt Register + // 0x00000001 [0] CLR_ACTIVITY (0) Reading this register clears the ACTIVITY interrupt if... + io_ro_32 clr_activity; + + _REG_(I2C_IC_CLR_STOP_DET_OFFSET) // I2C_IC_CLR_STOP_DET + // Clear STOP_DET Interrupt Register + // 0x00000001 [0] CLR_STOP_DET (0) Read this register to clear the STOP_DET interrupt (bit... + io_ro_32 clr_stop_det; + + _REG_(I2C_IC_CLR_START_DET_OFFSET) // I2C_IC_CLR_START_DET + // Clear START_DET Interrupt Register + // 0x00000001 [0] CLR_START_DET (0) Read this register to clear the START_DET interrupt (bit... + io_ro_32 clr_start_det; + + _REG_(I2C_IC_CLR_GEN_CALL_OFFSET) // I2C_IC_CLR_GEN_CALL + // Clear GEN_CALL Interrupt Register + // 0x00000001 [0] CLR_GEN_CALL (0) Read this register to clear the GEN_CALL interrupt (bit... + io_ro_32 clr_gen_call; + + _REG_(I2C_IC_ENABLE_OFFSET) // I2C_IC_ENABLE + // I2C ENABLE Register + // 0x00000004 [2] TX_CMD_BLOCK (0) In Master mode: - 1'b1: Blocks the transmission of data... + // 0x00000002 [1] ABORT (0) When set, the controller initiates the transfer abort + // 0x00000001 [0] ENABLE (0) Controls whether the DW_apb_i2c is enabled + io_rw_32 enable; + + _REG_(I2C_IC_STATUS_OFFSET) // I2C_IC_STATUS + // I2C STATUS Register + // 0x00000040 [6] SLV_ACTIVITY (0) Slave FSM Activity Status + // 0x00000020 [5] MST_ACTIVITY (0) Master FSM Activity Status + // 0x00000010 [4] RFF (0) Receive FIFO Completely Full + // 0x00000008 [3] RFNE (0) Receive FIFO Not Empty + // 0x00000004 [2] TFE (1) Transmit FIFO Completely Empty + // 0x00000002 [1] TFNF (1) Transmit FIFO Not Full + // 0x00000001 [0] ACTIVITY (0) I2C Activity Status + io_ro_32 status; + + _REG_(I2C_IC_TXFLR_OFFSET) // I2C_IC_TXFLR + // I2C Transmit FIFO Level Register + // 0x0000001f [4:0] TXFLR (0x00) Transmit FIFO Level + io_ro_32 txflr; + + _REG_(I2C_IC_RXFLR_OFFSET) // I2C_IC_RXFLR + // I2C Receive FIFO Level Register + // 0x0000001f [4:0] RXFLR (0x00) Receive FIFO Level + io_ro_32 rxflr; + + _REG_(I2C_IC_SDA_HOLD_OFFSET) // I2C_IC_SDA_HOLD + // I2C SDA Hold Time Length Register + // 0x00ff0000 [23:16] IC_SDA_RX_HOLD (0x00) Sets the required SDA hold time in units of ic_clk... + // 0x0000ffff [15:0] IC_SDA_TX_HOLD (0x0001) Sets the required SDA hold time in units of ic_clk... + io_rw_32 sda_hold; + + _REG_(I2C_IC_TX_ABRT_SOURCE_OFFSET) // I2C_IC_TX_ABRT_SOURCE + // I2C Transmit Abort Source Register + // 0xff800000 [31:23] TX_FLUSH_CNT (0x000) This field indicates the number of Tx FIFO Data Commands... + // 0x00010000 [16] ABRT_USER_ABRT (0) This is a master-mode-only bit + // 0x00008000 [15] ABRT_SLVRD_INTX (0) 1: When the processor side responds to a slave mode... + // 0x00004000 [14] ABRT_SLV_ARBLOST (0) This field indicates that a Slave has lost the bus while... + // 0x00002000 [13] ABRT_SLVFLUSH_TXFIFO (0) This field specifies that the Slave has received a read... + // 0x00001000 [12] ARB_LOST (0) This field specifies that the Master has lost... + // 0x00000800 [11] ABRT_MASTER_DIS (0) This field indicates that the User tries to initiate a... + // 0x00000400 [10] ABRT_10B_RD_NORSTRT (0) This field indicates that the restart is disabled... + // 0x00000200 [9] ABRT_SBYTE_NORSTRT (0) To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT... + // 0x00000100 [8] ABRT_HS_NORSTRT (0) This field indicates that the restart is disabled... + // 0x00000080 [7] ABRT_SBYTE_ACKDET (0) This field indicates that the Master has sent a START... + // 0x00000040 [6] ABRT_HS_ACKDET (0) This field indicates that the Master is in High Speed... + // 0x00000020 [5] ABRT_GCALL_READ (0) This field indicates that DW_apb_i2c in the master mode... + // 0x00000010 [4] ABRT_GCALL_NOACK (0) This field indicates that DW_apb_i2c in master mode has... + // 0x00000008 [3] ABRT_TXDATA_NOACK (0) This field indicates the master-mode only bit + // 0x00000004 [2] ABRT_10ADDR2_NOACK (0) This field indicates that the Master is in 10-bit... + // 0x00000002 [1] ABRT_10ADDR1_NOACK (0) This field indicates that the Master is in 10-bit... + // 0x00000001 [0] ABRT_7B_ADDR_NOACK (0) This field indicates that the Master is in 7-bit... + io_ro_32 tx_abrt_source; + + _REG_(I2C_IC_SLV_DATA_NACK_ONLY_OFFSET) // I2C_IC_SLV_DATA_NACK_ONLY + // Generate Slave Data NACK Register + // 0x00000001 [0] NACK (0) Generate NACK + io_rw_32 slv_data_nack_only; + + _REG_(I2C_IC_DMA_CR_OFFSET) // I2C_IC_DMA_CR + // DMA Control Register + // 0x00000002 [1] TDMAE (0) Transmit DMA Enable + // 0x00000001 [0] RDMAE (0) Receive DMA Enable + io_rw_32 dma_cr; + + _REG_(I2C_IC_DMA_TDLR_OFFSET) // I2C_IC_DMA_TDLR + // DMA Transmit Data Level Register + // 0x0000000f [3:0] DMATDL (0x0) Transmit Data Level + io_rw_32 dma_tdlr; + + _REG_(I2C_IC_DMA_RDLR_OFFSET) // I2C_IC_DMA_RDLR + // DMA Transmit Data Level Register + // 0x0000000f [3:0] DMARDL (0x0) Receive Data Level + io_rw_32 dma_rdlr; + + _REG_(I2C_IC_SDA_SETUP_OFFSET) // I2C_IC_SDA_SETUP + // I2C SDA Setup Register + // 0x000000ff [7:0] SDA_SETUP (0x64) SDA Setup + io_rw_32 sda_setup; + + _REG_(I2C_IC_ACK_GENERAL_CALL_OFFSET) // I2C_IC_ACK_GENERAL_CALL + // I2C ACK General Call Register + // 0x00000001 [0] ACK_GEN_CALL (1) ACK General Call + io_rw_32 ack_general_call; + + _REG_(I2C_IC_ENABLE_STATUS_OFFSET) // I2C_IC_ENABLE_STATUS + // I2C Enable Status Register + // 0x00000004 [2] SLV_RX_DATA_LOST (0) Slave Received Data Lost + // 0x00000002 [1] SLV_DISABLED_WHILE_BUSY (0) Slave Disabled While Busy (Transmit, Receive) + // 0x00000001 [0] IC_EN (0) ic_en Status + io_ro_32 enable_status; + + _REG_(I2C_IC_FS_SPKLEN_OFFSET) // I2C_IC_FS_SPKLEN + // I2C SS, FS or FM+ spike suppression limit + // 0x000000ff [7:0] IC_FS_SPKLEN (0x07) This register must be set before any I2C bus transaction... + io_rw_32 fs_spklen; + + uint32_t _pad2; + + _REG_(I2C_IC_CLR_RESTART_DET_OFFSET) // I2C_IC_CLR_RESTART_DET + // Clear RESTART_DET Interrupt Register + // 0x00000001 [0] CLR_RESTART_DET (0) Read this register to clear the RESTART_DET interrupt... + io_ro_32 clr_restart_det; + + uint32_t _pad3[18]; + + _REG_(I2C_IC_COMP_PARAM_1_OFFSET) // I2C_IC_COMP_PARAM_1 + // Component Parameter Register 1 + // 0x00ff0000 [23:16] TX_BUFFER_DEPTH (0x00) TX Buffer Depth = 16 + // 0x0000ff00 [15:8] RX_BUFFER_DEPTH (0x00) RX Buffer Depth = 16 + // 0x00000080 [7] ADD_ENCODED_PARAMS (0) Encoded parameters not visible + // 0x00000040 [6] HAS_DMA (0) DMA handshaking signals are enabled + // 0x00000020 [5] INTR_IO (0) COMBINED Interrupt outputs + // 0x00000010 [4] HC_COUNT_VALUES (0) Programmable count values for each mode + // 0x0000000c [3:2] MAX_SPEED_MODE (0x0) MAX SPEED MODE = FAST MODE + // 0x00000003 [1:0] APB_DATA_WIDTH (0x0) APB data bus width is 32 bits + io_ro_32 comp_param_1; + + _REG_(I2C_IC_COMP_VERSION_OFFSET) // I2C_IC_COMP_VERSION + // I2C Component Version Register + // 0xffffffff [31:0] IC_COMP_VERSION (0x3230312a) + io_ro_32 comp_version; + + _REG_(I2C_IC_COMP_TYPE_OFFSET) // I2C_IC_COMP_TYPE + // I2C Component Type Register + // 0xffffffff [31:0] IC_COMP_TYPE (0x44570140) Designware Component Type number = 0x44_57_01_40 + io_ro_32 comp_type; +} i2c_hw_t; + +#define i2c0_hw ((i2c_hw_t *)I2C0_BASE) +#define i2c1_hw ((i2c_hw_t *)I2C1_BASE) +static_assert(sizeof (i2c_hw_t) == 0x0100, ""); + +#endif // _HARDWARE_STRUCTS_I2C_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/interp.h b/lib/pico-sdk/rp2350/hardware/structs/interp.h new file mode 100644 index 00000000..eec0e3da --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/interp.h @@ -0,0 +1,87 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_INTERP_H +#define _HARDWARE_STRUCTS_INTERP_H + +/** + * \file rp2350/interp.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/sio.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sio +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/sio.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + // (Description copied from array index 0 register SIO_INTERP0_ACCUM0 applies similarly to other array indexes) + _REG_(SIO_INTERP0_ACCUM0_OFFSET) // SIO_INTERP0_ACCUM0 + // Read/write access to accumulator 0 + // 0xffffffff [31:0] INTERP0_ACCUM0 (0x00000000) + io_rw_32 accum[2]; + + // (Description copied from array index 0 register SIO_INTERP0_BASE0 applies similarly to other array indexes) + _REG_(SIO_INTERP0_BASE0_OFFSET) // SIO_INTERP0_BASE0 + // Read/write access to BASE0 register + // 0xffffffff [31:0] INTERP0_BASE0 (0x00000000) + io_rw_32 base[3]; + + // (Description copied from array index 0 register SIO_INTERP0_POP_LANE0 applies similarly to other array indexes) + _REG_(SIO_INTERP0_POP_LANE0_OFFSET) // SIO_INTERP0_POP_LANE0 + // Read LANE0 result, and simultaneously write lane results to both accumulators (POP) + // 0xffffffff [31:0] INTERP0_POP_LANE0 (0x00000000) + io_ro_32 pop[3]; + + // (Description copied from array index 0 register SIO_INTERP0_PEEK_LANE0 applies similarly to other array indexes) + _REG_(SIO_INTERP0_PEEK_LANE0_OFFSET) // SIO_INTERP0_PEEK_LANE0 + // Read LANE0 result, without altering any internal state (PEEK) + // 0xffffffff [31:0] INTERP0_PEEK_LANE0 (0x00000000) + io_ro_32 peek[3]; + + // (Description copied from array index 0 register SIO_INTERP0_CTRL_LANE0 applies similarly to other array indexes) + _REG_(SIO_INTERP0_CTRL_LANE0_OFFSET) // SIO_INTERP0_CTRL_LANE0 + // Control register for lane 0 + // 0x02000000 [25] OVERF (0) Set if either OVERF0 or OVERF1 is set + // 0x01000000 [24] OVERF1 (0) Indicates if any masked-off MSBs in ACCUM1 are set + // 0x00800000 [23] OVERF0 (0) Indicates if any masked-off MSBs in ACCUM0 are set + // 0x00200000 [21] BLEND (0) Only present on INTERP0 on each core + // 0x00180000 [20:19] FORCE_MSB (0x0) ORed into bits 29:28 of the lane result presented to the... + // 0x00040000 [18] ADD_RAW (0) If 1, mask + shift is bypassed for LANE0 result + // 0x00020000 [17] CROSS_RESULT (0) If 1, feed the opposite lane's result into this lane's... + // 0x00010000 [16] CROSS_INPUT (0) If 1, feed the opposite lane's accumulator into this... + // 0x00008000 [15] SIGNED (0) If SIGNED is set, the shifted and masked accumulator... + // 0x00007c00 [14:10] MASK_MSB (0x00) The most-significant bit allowed to pass by the mask... + // 0x000003e0 [9:5] MASK_LSB (0x00) The least-significant bit allowed to pass by the mask (inclusive) + // 0x0000001f [4:0] SHIFT (0x00) Right-rotate applied to accumulator before masking + io_rw_32 ctrl[2]; + + // (Description copied from array index 0 register SIO_INTERP0_ACCUM0_ADD applies similarly to other array indexes) + _REG_(SIO_INTERP0_ACCUM0_ADD_OFFSET) // SIO_INTERP0_ACCUM0_ADD + // Values written here are atomically added to ACCUM0 + // 0x00ffffff [23:0] INTERP0_ACCUM0_ADD (0x000000) + io_rw_32 add_raw[2]; + + _REG_(SIO_INTERP0_BASE_1AND0_OFFSET) // SIO_INTERP0_BASE_1AND0 + // On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. + // 0xffffffff [31:0] INTERP0_BASE_1AND0 (0x00000000) + io_wo_32 base01; +} interp_hw_t; + +#define interp_hw_array ((interp_hw_t *)(SIO_BASE + SIO_INTERP0_ACCUM0_OFFSET)) +#define interp_hw_array_ns ((interp_hw_t *)(SIO_NONSEC_BASE + SIO_INTERP0_ACCUM0_OFFSET)) +static_assert(sizeof (interp_hw_t) == 0x0040, ""); +#define interp0_hw (&interp_hw_array[0]) +#define interp1_hw (&interp_hw_array[1]) + +#endif // _HARDWARE_STRUCTS_INTERP_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/io_bank0.h b/lib/pico-sdk/rp2350/hardware/structs/io_bank0.h new file mode 100644 index 00000000..c5020e23 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/io_bank0.h @@ -0,0 +1,452 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_IO_BANK0_H +#define _HARDWARE_STRUCTS_IO_BANK0_H + +/** + * \file rp2350/io_bank0.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/io_bank0.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_io_bank0 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/io_bank0.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/** + * \brief GPIO pin function selectors on RP2350 (used as typedef \ref gpio_function_t) + * \ingroup hardware_gpio + */ +typedef enum gpio_function_rp2350 { + GPIO_FUNC_HSTX = 0, ///< Select HSTX as GPIO pin function + GPIO_FUNC_SPI = 1, ///< Select SPI as GPIO pin function + GPIO_FUNC_UART = 2, ///< Select UART as GPIO pin function + GPIO_FUNC_I2C = 3, ///< Select I2C as GPIO pin function + GPIO_FUNC_PWM = 4, ///< Select PWM as GPIO pin function + GPIO_FUNC_SIO = 5, ///< Select SIO as GPIO pin function + GPIO_FUNC_PIO0 = 6, ///< Select PIO0 as GPIO pin function + GPIO_FUNC_PIO1 = 7, ///< Select PIO1 as GPIO pin function + GPIO_FUNC_PIO2 = 8, ///< Select PIO2 as GPIO pin function + GPIO_FUNC_GPCK = 9, ///< Select GPCK as GPIO pin function + GPIO_FUNC_XIP_CS1 = 9, ///< Select XIP CS1 as GPIO pin function + GPIO_FUNC_CORESIGHT_TRACE = 9, ///< Select CORESIGHT TRACE as GPIO pin function + GPIO_FUNC_USB = 10, ///< Select USB as GPIO pin function + GPIO_FUNC_UART_AUX = 11, ///< Select UART_AUX as GPIO pin function + GPIO_FUNC_NULL = 0x1f, ///< Select NULL as GPIO pin function +} gpio_function_t; + +typedef struct { + _REG_(IO_BANK0_GPIO0_STATUS_OFFSET) // IO_BANK0_GPIO0_STATUS + // 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied + // 0x00020000 [17] INFROMPAD (0) input signal from pad, before filtering and override are applied + // 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied + // 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied + io_ro_32 status; + + _REG_(IO_BANK0_GPIO0_CTRL_OFFSET) // IO_BANK0_GPIO0_CTRL + // 0x30000000 [29:28] IRQOVER (0x0) + // 0x00030000 [17:16] INOVER (0x0) + // 0x0000c000 [15:14] OEOVER (0x0) + // 0x00003000 [13:12] OUTOVER (0x0) + // 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table + + io_rw_32 ctrl; +} io_bank0_status_ctrl_hw_t; + +typedef struct { + // (Description copied from array index 0 register IO_BANK0_PROC0_INTE0 applies similarly to other array indexes) + _REG_(IO_BANK0_PROC0_INTE0_OFFSET) // IO_BANK0_PROC0_INTE0 + // Interrupt Enable for proc0 + // 0x80000000 [31] GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] GPIO7_EDGE_LOW (0) + // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] GPIO6_EDGE_LOW (0) + // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] GPIO5_EDGE_LOW (0) + // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] GPIO4_EDGE_LOW (0) + // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] GPIO3_EDGE_LOW (0) + // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] GPIO2_EDGE_LOW (0) + // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] GPIO1_EDGE_LOW (0) + // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] GPIO0_EDGE_LOW (0) + // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO0_LEVEL_LOW (0) + io_rw_32 inte[6]; + + // (Description copied from array index 0 register IO_BANK0_PROC0_INTF0 applies similarly to other array indexes) + _REG_(IO_BANK0_PROC0_INTF0_OFFSET) // IO_BANK0_PROC0_INTF0 + // Interrupt Force for proc0 + // 0x80000000 [31] GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] GPIO7_EDGE_LOW (0) + // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] GPIO6_EDGE_LOW (0) + // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] GPIO5_EDGE_LOW (0) + // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] GPIO4_EDGE_LOW (0) + // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] GPIO3_EDGE_LOW (0) + // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] GPIO2_EDGE_LOW (0) + // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] GPIO1_EDGE_LOW (0) + // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] GPIO0_EDGE_LOW (0) + // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO0_LEVEL_LOW (0) + io_rw_32 intf[6]; + + // (Description copied from array index 0 register IO_BANK0_PROC0_INTS0 applies similarly to other array indexes) + _REG_(IO_BANK0_PROC0_INTS0_OFFSET) // IO_BANK0_PROC0_INTS0 + // Interrupt status after masking & forcing for proc0 + // 0x80000000 [31] GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] GPIO7_EDGE_LOW (0) + // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] GPIO6_EDGE_LOW (0) + // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] GPIO5_EDGE_LOW (0) + // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] GPIO4_EDGE_LOW (0) + // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] GPIO3_EDGE_LOW (0) + // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] GPIO2_EDGE_LOW (0) + // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] GPIO1_EDGE_LOW (0) + // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] GPIO0_EDGE_LOW (0) + // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO0_LEVEL_LOW (0) + io_ro_32 ints[6]; +} io_bank0_irq_ctrl_hw_t; + +/// \tag::io_bank0_hw[] +typedef struct { + io_bank0_status_ctrl_hw_t io[48]; + + uint32_t _pad0[32]; + + // (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_PROC0_SECURE0 applies similarly to other array indexes) + _REG_(IO_BANK0_IRQSUMMARY_PROC0_SECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_PROC0_SECURE0 + // 0x80000000 [31] GPIO31 (0) + // 0x40000000 [30] GPIO30 (0) + // 0x20000000 [29] GPIO29 (0) + // 0x10000000 [28] GPIO28 (0) + // 0x08000000 [27] GPIO27 (0) + // 0x04000000 [26] GPIO26 (0) + // 0x02000000 [25] GPIO25 (0) + // 0x01000000 [24] GPIO24 (0) + // 0x00800000 [23] GPIO23 (0) + // 0x00400000 [22] GPIO22 (0) + // 0x00200000 [21] GPIO21 (0) + // 0x00100000 [20] GPIO20 (0) + // 0x00080000 [19] GPIO19 (0) + // 0x00040000 [18] GPIO18 (0) + // 0x00020000 [17] GPIO17 (0) + // 0x00010000 [16] GPIO16 (0) + // 0x00008000 [15] GPIO15 (0) + // 0x00004000 [14] GPIO14 (0) + // 0x00002000 [13] GPIO13 (0) + // 0x00001000 [12] GPIO12 (0) + // 0x00000800 [11] GPIO11 (0) + // 0x00000400 [10] GPIO10 (0) + // 0x00000200 [9] GPIO9 (0) + // 0x00000100 [8] GPIO8 (0) + // 0x00000080 [7] GPIO7 (0) + // 0x00000040 [6] GPIO6 (0) + // 0x00000020 [5] GPIO5 (0) + // 0x00000010 [4] GPIO4 (0) + // 0x00000008 [3] GPIO3 (0) + // 0x00000004 [2] GPIO2 (0) + // 0x00000002 [1] GPIO1 (0) + // 0x00000001 [0] GPIO0 (0) + io_ro_32 irqsummary_proc0_secure[2]; + + // (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0 applies similarly to other array indexes) + _REG_(IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0 + // 0x80000000 [31] GPIO31 (0) + // 0x40000000 [30] GPIO30 (0) + // 0x20000000 [29] GPIO29 (0) + // 0x10000000 [28] GPIO28 (0) + // 0x08000000 [27] GPIO27 (0) + // 0x04000000 [26] GPIO26 (0) + // 0x02000000 [25] GPIO25 (0) + // 0x01000000 [24] GPIO24 (0) + // 0x00800000 [23] GPIO23 (0) + // 0x00400000 [22] GPIO22 (0) + // 0x00200000 [21] GPIO21 (0) + // 0x00100000 [20] GPIO20 (0) + // 0x00080000 [19] GPIO19 (0) + // 0x00040000 [18] GPIO18 (0) + // 0x00020000 [17] GPIO17 (0) + // 0x00010000 [16] GPIO16 (0) + // 0x00008000 [15] GPIO15 (0) + // 0x00004000 [14] GPIO14 (0) + // 0x00002000 [13] GPIO13 (0) + // 0x00001000 [12] GPIO12 (0) + // 0x00000800 [11] GPIO11 (0) + // 0x00000400 [10] GPIO10 (0) + // 0x00000200 [9] GPIO9 (0) + // 0x00000100 [8] GPIO8 (0) + // 0x00000080 [7] GPIO7 (0) + // 0x00000040 [6] GPIO6 (0) + // 0x00000020 [5] GPIO5 (0) + // 0x00000010 [4] GPIO4 (0) + // 0x00000008 [3] GPIO3 (0) + // 0x00000004 [2] GPIO2 (0) + // 0x00000002 [1] GPIO1 (0) + // 0x00000001 [0] GPIO0 (0) + io_ro_32 irqsummary_proc0_nonsecure[2]; + + // (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_PROC1_SECURE0 applies similarly to other array indexes) + _REG_(IO_BANK0_IRQSUMMARY_PROC1_SECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_PROC1_SECURE0 + // 0x80000000 [31] GPIO31 (0) + // 0x40000000 [30] GPIO30 (0) + // 0x20000000 [29] GPIO29 (0) + // 0x10000000 [28] GPIO28 (0) + // 0x08000000 [27] GPIO27 (0) + // 0x04000000 [26] GPIO26 (0) + // 0x02000000 [25] GPIO25 (0) + // 0x01000000 [24] GPIO24 (0) + // 0x00800000 [23] GPIO23 (0) + // 0x00400000 [22] GPIO22 (0) + // 0x00200000 [21] GPIO21 (0) + // 0x00100000 [20] GPIO20 (0) + // 0x00080000 [19] GPIO19 (0) + // 0x00040000 [18] GPIO18 (0) + // 0x00020000 [17] GPIO17 (0) + // 0x00010000 [16] GPIO16 (0) + // 0x00008000 [15] GPIO15 (0) + // 0x00004000 [14] GPIO14 (0) + // 0x00002000 [13] GPIO13 (0) + // 0x00001000 [12] GPIO12 (0) + // 0x00000800 [11] GPIO11 (0) + // 0x00000400 [10] GPIO10 (0) + // 0x00000200 [9] GPIO9 (0) + // 0x00000100 [8] GPIO8 (0) + // 0x00000080 [7] GPIO7 (0) + // 0x00000040 [6] GPIO6 (0) + // 0x00000020 [5] GPIO5 (0) + // 0x00000010 [4] GPIO4 (0) + // 0x00000008 [3] GPIO3 (0) + // 0x00000004 [2] GPIO2 (0) + // 0x00000002 [1] GPIO1 (0) + // 0x00000001 [0] GPIO0 (0) + io_ro_32 irqsummary_proc1_secure[2]; + + // (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0 applies similarly to other array indexes) + _REG_(IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0 + // 0x80000000 [31] GPIO31 (0) + // 0x40000000 [30] GPIO30 (0) + // 0x20000000 [29] GPIO29 (0) + // 0x10000000 [28] GPIO28 (0) + // 0x08000000 [27] GPIO27 (0) + // 0x04000000 [26] GPIO26 (0) + // 0x02000000 [25] GPIO25 (0) + // 0x01000000 [24] GPIO24 (0) + // 0x00800000 [23] GPIO23 (0) + // 0x00400000 [22] GPIO22 (0) + // 0x00200000 [21] GPIO21 (0) + // 0x00100000 [20] GPIO20 (0) + // 0x00080000 [19] GPIO19 (0) + // 0x00040000 [18] GPIO18 (0) + // 0x00020000 [17] GPIO17 (0) + // 0x00010000 [16] GPIO16 (0) + // 0x00008000 [15] GPIO15 (0) + // 0x00004000 [14] GPIO14 (0) + // 0x00002000 [13] GPIO13 (0) + // 0x00001000 [12] GPIO12 (0) + // 0x00000800 [11] GPIO11 (0) + // 0x00000400 [10] GPIO10 (0) + // 0x00000200 [9] GPIO9 (0) + // 0x00000100 [8] GPIO8 (0) + // 0x00000080 [7] GPIO7 (0) + // 0x00000040 [6] GPIO6 (0) + // 0x00000020 [5] GPIO5 (0) + // 0x00000010 [4] GPIO4 (0) + // 0x00000008 [3] GPIO3 (0) + // 0x00000004 [2] GPIO2 (0) + // 0x00000002 [1] GPIO1 (0) + // 0x00000001 [0] GPIO0 (0) + io_ro_32 irqsummary_proc1_nonsecure[2]; + + // (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0 applies similarly to other array indexes) + _REG_(IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0 + // 0x80000000 [31] GPIO31 (0) + // 0x40000000 [30] GPIO30 (0) + // 0x20000000 [29] GPIO29 (0) + // 0x10000000 [28] GPIO28 (0) + // 0x08000000 [27] GPIO27 (0) + // 0x04000000 [26] GPIO26 (0) + // 0x02000000 [25] GPIO25 (0) + // 0x01000000 [24] GPIO24 (0) + // 0x00800000 [23] GPIO23 (0) + // 0x00400000 [22] GPIO22 (0) + // 0x00200000 [21] GPIO21 (0) + // 0x00100000 [20] GPIO20 (0) + // 0x00080000 [19] GPIO19 (0) + // 0x00040000 [18] GPIO18 (0) + // 0x00020000 [17] GPIO17 (0) + // 0x00010000 [16] GPIO16 (0) + // 0x00008000 [15] GPIO15 (0) + // 0x00004000 [14] GPIO14 (0) + // 0x00002000 [13] GPIO13 (0) + // 0x00001000 [12] GPIO12 (0) + // 0x00000800 [11] GPIO11 (0) + // 0x00000400 [10] GPIO10 (0) + // 0x00000200 [9] GPIO9 (0) + // 0x00000100 [8] GPIO8 (0) + // 0x00000080 [7] GPIO7 (0) + // 0x00000040 [6] GPIO6 (0) + // 0x00000020 [5] GPIO5 (0) + // 0x00000010 [4] GPIO4 (0) + // 0x00000008 [3] GPIO3 (0) + // 0x00000004 [2] GPIO2 (0) + // 0x00000002 [1] GPIO1 (0) + // 0x00000001 [0] GPIO0 (0) + io_ro_32 irqsummary_dormant_wake_secure[2]; + + // (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0 applies similarly to other array indexes) + _REG_(IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0 + // 0x80000000 [31] GPIO31 (0) + // 0x40000000 [30] GPIO30 (0) + // 0x20000000 [29] GPIO29 (0) + // 0x10000000 [28] GPIO28 (0) + // 0x08000000 [27] GPIO27 (0) + // 0x04000000 [26] GPIO26 (0) + // 0x02000000 [25] GPIO25 (0) + // 0x01000000 [24] GPIO24 (0) + // 0x00800000 [23] GPIO23 (0) + // 0x00400000 [22] GPIO22 (0) + // 0x00200000 [21] GPIO21 (0) + // 0x00100000 [20] GPIO20 (0) + // 0x00080000 [19] GPIO19 (0) + // 0x00040000 [18] GPIO18 (0) + // 0x00020000 [17] GPIO17 (0) + // 0x00010000 [16] GPIO16 (0) + // 0x00008000 [15] GPIO15 (0) + // 0x00004000 [14] GPIO14 (0) + // 0x00002000 [13] GPIO13 (0) + // 0x00001000 [12] GPIO12 (0) + // 0x00000800 [11] GPIO11 (0) + // 0x00000400 [10] GPIO10 (0) + // 0x00000200 [9] GPIO9 (0) + // 0x00000100 [8] GPIO8 (0) + // 0x00000080 [7] GPIO7 (0) + // 0x00000040 [6] GPIO6 (0) + // 0x00000020 [5] GPIO5 (0) + // 0x00000010 [4] GPIO4 (0) + // 0x00000008 [3] GPIO3 (0) + // 0x00000004 [2] GPIO2 (0) + // 0x00000002 [1] GPIO1 (0) + // 0x00000001 [0] GPIO0 (0) + io_ro_32 irqsummary_dormant_wake_nonsecure[2]; + + // (Description copied from array index 0 register IO_BANK0_INTR0 applies similarly to other array indexes) + _REG_(IO_BANK0_INTR0_OFFSET) // IO_BANK0_INTR0 + // Raw Interrupts + // 0x80000000 [31] GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] GPIO7_EDGE_LOW (0) + // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] GPIO6_EDGE_LOW (0) + // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] GPIO5_EDGE_LOW (0) + // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] GPIO4_EDGE_LOW (0) + // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] GPIO3_EDGE_LOW (0) + // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] GPIO2_EDGE_LOW (0) + // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] GPIO1_EDGE_LOW (0) + // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] GPIO0_EDGE_LOW (0) + // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO0_LEVEL_LOW (0) + io_rw_32 intr[6]; + + union { + struct { + io_bank0_irq_ctrl_hw_t proc0_irq_ctrl; + io_bank0_irq_ctrl_hw_t proc1_irq_ctrl; + io_bank0_irq_ctrl_hw_t dormant_wake_irq_ctrl; + }; + io_bank0_irq_ctrl_hw_t irq_ctrl[3]; + }; +} io_bank0_hw_t; +/// \end::io_bank0_hw[] + +#define io_bank0_hw ((io_bank0_hw_t *)IO_BANK0_BASE) +static_assert(sizeof (io_bank0_hw_t) == 0x0320, ""); + +#endif // _HARDWARE_STRUCTS_IO_BANK0_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/io_qspi.h b/lib/pico-sdk/rp2350/hardware/structs/io_qspi.h new file mode 100644 index 00000000..cec2bba6 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/io_qspi.h @@ -0,0 +1,316 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_IO_QSPI_H +#define _HARDWARE_STRUCTS_IO_QSPI_H + +/** + * \file rp2350/io_qspi.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/io_qspi.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_io_qspi +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/io_qspi.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/** + * \brief QSPI pin function selectors on RP2350 (used as typedef \ref gpio_function1_t) + */ +typedef enum gpio_function1_rp2350 { + GPIO_FUNC1_XIP = 0, ///< Select XIP as QSPI pin function + GPIO_FUNC1_UART = 2, ///< Select UART as QSPI pin function + GPIO_FUNC1_I2C = 3, ///< Select I2C as QSPI pin function + GPIO_FUNC1_SIO = 5, ///< Select SIO as QSPI pin function + GPIO_FUNC1_UART_AUX = 11, ///< Select UART_AUX as QSPI pin function + GPIO_FUNC1_NULL = 0x1f, ///< Select NULL as QSPI pin function +} gpio_function1_t; + +typedef struct { + _REG_(IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_STATUS + // 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied + // 0x00020000 [17] INFROMPAD (0) input signal from pad, before filtering and override are applied + // 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied + // 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied + io_ro_32 status; + + _REG_(IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_CTRL + // 0x30000000 [29:28] IRQOVER (0x0) + // 0x00030000 [17:16] INOVER (0x0) + // 0x0000c000 [15:14] OEOVER (0x0) + // 0x00003000 [13:12] OUTOVER (0x0) + // 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table + + io_rw_32 ctrl; +} io_qspi_status_ctrl_hw_t; + +typedef struct { + _REG_(IO_QSPI_PROC0_INTE_OFFSET) // IO_QSPI_PROC0_INTE + // Interrupt Enable for proc0 + // 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0) + // 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0) + // 0x00000040 [6] USBPHY_DM_EDGE_LOW (0) + // 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0) + // 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0) + // 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0) + // 0x00000004 [2] USBPHY_DP_EDGE_LOW (0) + // 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0) + // 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0) + io_rw_32 inte; + + _REG_(IO_QSPI_PROC0_INTF_OFFSET) // IO_QSPI_PROC0_INTF + // Interrupt Force for proc0 + // 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0) + // 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0) + // 0x00000040 [6] USBPHY_DM_EDGE_LOW (0) + // 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0) + // 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0) + // 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0) + // 0x00000004 [2] USBPHY_DP_EDGE_LOW (0) + // 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0) + // 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0) + io_rw_32 intf; + + _REG_(IO_QSPI_PROC0_INTS_OFFSET) // IO_QSPI_PROC0_INTS + // Interrupt status after masking & forcing for proc0 + // 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0) + // 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0) + // 0x00000040 [6] USBPHY_DM_EDGE_LOW (0) + // 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0) + // 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0) + // 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0) + // 0x00000004 [2] USBPHY_DP_EDGE_LOW (0) + // 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0) + // 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0) + io_ro_32 ints; +} io_qspi_irq_ctrl_hw_t; + +typedef struct { + _REG_(IO_QSPI_USBPHY_DP_STATUS_OFFSET) // IO_QSPI_USBPHY_DP_STATUS + // 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied + // 0x00020000 [17] INFROMPAD (0) input signal from pad, before filtering and override are applied + // 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied + // 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied + io_ro_32 usbphy_dp_status; + + _REG_(IO_QSPI_USBPHY_DP_CTRL_OFFSET) // IO_QSPI_USBPHY_DP_CTRL + // 0x30000000 [29:28] IRQOVER (0x0) + // 0x00030000 [17:16] INOVER (0x0) + // 0x0000c000 [15:14] OEOVER (0x0) + // 0x00003000 [13:12] OUTOVER (0x0) + // 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table + + io_rw_32 usbphy_dp_ctrl; + + _REG_(IO_QSPI_USBPHY_DM_STATUS_OFFSET) // IO_QSPI_USBPHY_DM_STATUS + // 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied + // 0x00020000 [17] INFROMPAD (0) input signal from pad, before filtering and override are applied + // 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied + // 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied + io_ro_32 usbphy_dm_status; + + _REG_(IO_QSPI_USBPHY_DM_CTRL_OFFSET) // IO_QSPI_USBPHY_DM_CTRL + // 0x30000000 [29:28] IRQOVER (0x0) + // 0x00030000 [17:16] INOVER (0x0) + // 0x0000c000 [15:14] OEOVER (0x0) + // 0x00003000 [13:12] OUTOVER (0x0) + // 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table + + io_rw_32 usbphy_dm_ctrl; + + io_qspi_status_ctrl_hw_t io[6]; + + uint32_t _pad0[112]; + + _REG_(IO_QSPI_IRQSUMMARY_PROC0_SECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC0_SECURE + // 0x00000080 [7] GPIO_QSPI_SD3 (0) + // 0x00000040 [6] GPIO_QSPI_SD2 (0) + // 0x00000020 [5] GPIO_QSPI_SD1 (0) + // 0x00000010 [4] GPIO_QSPI_SD0 (0) + // 0x00000008 [3] GPIO_QSPI_SS (0) + // 0x00000004 [2] GPIO_QSPI_SCLK (0) + // 0x00000002 [1] USBPHY_DM (0) + // 0x00000001 [0] USBPHY_DP (0) + io_ro_32 irqsummary_proc0_secure; + + _REG_(IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC0_NONSECURE + // 0x00000080 [7] GPIO_QSPI_SD3 (0) + // 0x00000040 [6] GPIO_QSPI_SD2 (0) + // 0x00000020 [5] GPIO_QSPI_SD1 (0) + // 0x00000010 [4] GPIO_QSPI_SD0 (0) + // 0x00000008 [3] GPIO_QSPI_SS (0) + // 0x00000004 [2] GPIO_QSPI_SCLK (0) + // 0x00000002 [1] USBPHY_DM (0) + // 0x00000001 [0] USBPHY_DP (0) + io_ro_32 irqsummary_proc0_nonsecure; + + _REG_(IO_QSPI_IRQSUMMARY_PROC1_SECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC1_SECURE + // 0x00000080 [7] GPIO_QSPI_SD3 (0) + // 0x00000040 [6] GPIO_QSPI_SD2 (0) + // 0x00000020 [5] GPIO_QSPI_SD1 (0) + // 0x00000010 [4] GPIO_QSPI_SD0 (0) + // 0x00000008 [3] GPIO_QSPI_SS (0) + // 0x00000004 [2] GPIO_QSPI_SCLK (0) + // 0x00000002 [1] USBPHY_DM (0) + // 0x00000001 [0] USBPHY_DP (0) + io_ro_32 irqsummary_proc1_secure; + + _REG_(IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC1_NONSECURE + // 0x00000080 [7] GPIO_QSPI_SD3 (0) + // 0x00000040 [6] GPIO_QSPI_SD2 (0) + // 0x00000020 [5] GPIO_QSPI_SD1 (0) + // 0x00000010 [4] GPIO_QSPI_SD0 (0) + // 0x00000008 [3] GPIO_QSPI_SS (0) + // 0x00000004 [2] GPIO_QSPI_SCLK (0) + // 0x00000002 [1] USBPHY_DM (0) + // 0x00000001 [0] USBPHY_DP (0) + io_ro_32 irqsummary_proc1_nonsecure; + + _REG_(IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_OFFSET) // IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE + // 0x00000080 [7] GPIO_QSPI_SD3 (0) + // 0x00000040 [6] GPIO_QSPI_SD2 (0) + // 0x00000020 [5] GPIO_QSPI_SD1 (0) + // 0x00000010 [4] GPIO_QSPI_SD0 (0) + // 0x00000008 [3] GPIO_QSPI_SS (0) + // 0x00000004 [2] GPIO_QSPI_SCLK (0) + // 0x00000002 [1] USBPHY_DM (0) + // 0x00000001 [0] USBPHY_DP (0) + io_ro_32 irqsummary_dormant_wake_secure; + + _REG_(IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_OFFSET) // IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE + // 0x00000080 [7] GPIO_QSPI_SD3 (0) + // 0x00000040 [6] GPIO_QSPI_SD2 (0) + // 0x00000020 [5] GPIO_QSPI_SD1 (0) + // 0x00000010 [4] GPIO_QSPI_SD0 (0) + // 0x00000008 [3] GPIO_QSPI_SS (0) + // 0x00000004 [2] GPIO_QSPI_SCLK (0) + // 0x00000002 [1] USBPHY_DM (0) + // 0x00000001 [0] USBPHY_DP (0) + io_ro_32 irqsummary_dormant_wake_nonsecure; + + _REG_(IO_QSPI_INTR_OFFSET) // IO_QSPI_INTR + // Raw Interrupts + // 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0) + // 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0) + // 0x00000040 [6] USBPHY_DM_EDGE_LOW (0) + // 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0) + // 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0) + // 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0) + // 0x00000004 [2] USBPHY_DP_EDGE_LOW (0) + // 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0) + // 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0) + io_rw_32 intr; + + union { + struct { + io_qspi_irq_ctrl_hw_t proc0_irq_ctrl; + io_qspi_irq_ctrl_hw_t proc1_irq_ctrl; + io_qspi_irq_ctrl_hw_t dormant_wake_irq_ctrl; + }; + io_qspi_irq_ctrl_hw_t irq_ctrl[3]; + }; +} io_qspi_hw_t; + +#define io_qspi_hw ((io_qspi_hw_t *)IO_QSPI_BASE) +static_assert(sizeof (io_qspi_hw_t) == 0x0240, ""); + +#endif // _HARDWARE_STRUCTS_IO_QSPI_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/iobank0.h b/lib/pico-sdk/rp2350/hardware/structs/iobank0.h new file mode 100644 index 00000000..2dc31e38 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/iobank0.h @@ -0,0 +1,9 @@ +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// Support old header for compatibility (and if included, support old variable name) +#include "hardware/structs/io_bank0.h" +#define iobank0_hw io_bank0_hw
\ No newline at end of file diff --git a/lib/pico-sdk/rp2350/hardware/structs/ioqspi.h b/lib/pico-sdk/rp2350/hardware/structs/ioqspi.h new file mode 100644 index 00000000..20cc74c7 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/ioqspi.h @@ -0,0 +1,9 @@ +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// Support old header for compatibility (and if included, support old variable name) +#include "hardware/structs/io_qspi.h" +#define ioqspi_hw io_qspi_hw
\ No newline at end of file diff --git a/lib/pico-sdk/rp2350/hardware/structs/m33.h b/lib/pico-sdk/rp2350/hardware/structs/m33.h new file mode 100644 index 00000000..d527c917 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/m33.h @@ -0,0 +1,1651 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_M33_H +#define _HARDWARE_STRUCTS_M33_H + +/** + * \file rp2350/m33.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/m33.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m33.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV +#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" +#endif + +typedef struct { + // (Description copied from array index 0 register M33_ITM_STIM0 applies similarly to other array indexes) + _REG_(M33_ITM_STIM0_OFFSET) // M33_ITM_STIM0 + // ITM Stimulus Port Register 0 + // 0xffffffff [31:0] STIMULUS (0x00000000) Data to write to the Stimulus Port FIFO, for forwarding... + io_rw_32 itm_stim[32]; + + uint32_t _pad0[864]; + + _REG_(M33_ITM_TER0_OFFSET) // M33_ITM_TER0 + // Provide an individual enable bit for each ITM_STIM register + // 0xffffffff [31:0] STIMENA (0x00000000) For STIMENA[m] in ITM_TER*n, controls whether... + io_rw_32 itm_ter0; + + uint32_t _pad1[15]; + + _REG_(M33_ITM_TPR_OFFSET) // M33_ITM_TPR + // Controls which stimulus ports can be accessed by unprivileged code + // 0x0000000f [3:0] PRIVMASK (0x0) Bit mask to enable tracing on ITM stimulus ports + io_rw_32 itm_tpr; + + uint32_t _pad2[15]; + + _REG_(M33_ITM_TCR_OFFSET) // M33_ITM_TCR + // Configures and controls transfers through the ITM interface + // 0x00800000 [23] BUSY (0) Indicates whether the ITM is currently processing events + // 0x007f0000 [22:16] TRACEBUSID (0x00) Identifier for multi-source trace stream formatting + // 0x00000c00 [11:10] GTSFREQ (0x0) Defines how often the ITM generates a global timestamp,... + // 0x00000300 [9:8] TSPRESCALE (0x0) Local timestamp prescaler, used with the trace packet... + // 0x00000020 [5] STALLENA (0) Stall the PE to guarantee delivery of Data Trace packets + // 0x00000010 [4] SWOENA (0) Enables asynchronous clocking of the timestamp counter + // 0x00000008 [3] TXENA (0) Enables forwarding of hardware event packet from the DWT... + // 0x00000004 [2] SYNCENA (0) Enables Synchronization packet transmission for a... + // 0x00000002 [1] TSENA (0) Enables Local timestamp generation + // 0x00000001 [0] ITMENA (0) Enables the ITM + io_rw_32 itm_tcr; + + uint32_t _pad3[27]; + + _REG_(M33_INT_ATREADY_OFFSET) // M33_INT_ATREADY + // Integration Mode: Read ATB Ready + // 0x00000002 [1] AFVALID (0) A read of this bit returns the value of AFVALID + // 0x00000001 [0] ATREADY (0) A read of this bit returns the value of ATREADY + io_ro_32 int_atready; + + uint32_t _pad4; + + _REG_(M33_INT_ATVALID_OFFSET) // M33_INT_ATVALID + // Integration Mode: Write ATB Valid + // 0x00000002 [1] AFREADY (0) A write to this bit gives the value of AFREADY + // 0x00000001 [0] ATREADY (0) A write to this bit gives the value of ATVALID + io_rw_32 int_atvalid; + + uint32_t _pad5; + + _REG_(M33_ITM_ITCTRL_OFFSET) // M33_ITM_ITCTRL + // Integration Mode Control Register + // 0x00000001 [0] IME (0) Integration mode enable bit - The possible values are: ... + io_rw_32 itm_itctrl; + + uint32_t _pad6[46]; + + _REG_(M33_ITM_DEVARCH_OFFSET) // M33_ITM_DEVARCH + // Provides CoreSight discovery information for the ITM + // 0xffe00000 [31:21] ARCHITECT (0x23b) Defines the architect of the component + // 0x00100000 [20] PRESENT (1) Defines that the DEVARCH register is present + // 0x000f0000 [19:16] REVISION (0x0) Defines the architecture revision of the component + // 0x0000f000 [15:12] ARCHVER (0x1) Defines the architecture version of the component + // 0x00000fff [11:0] ARCHPART (0xa01) Defines the architecture of the component + io_ro_32 itm_devarch; + + uint32_t _pad7[3]; + + _REG_(M33_ITM_DEVTYPE_OFFSET) // M33_ITM_DEVTYPE + // Provides CoreSight discovery information for the ITM + // 0x000000f0 [7:4] SUB (0x4) Component sub-type + // 0x0000000f [3:0] MAJOR (0x3) Component major type + io_ro_32 itm_devtype; + + _REG_(M33_ITM_PIDR4_OFFSET) // M33_ITM_PIDR4 + // Provides CoreSight discovery information for the ITM + // 0x000000f0 [7:4] SIZE (0x0) See CoreSight Architecture Specification + // 0x0000000f [3:0] DES_2 (0x4) See CoreSight Architecture Specification + io_ro_32 itm_pidr4; + + _REG_(M33_ITM_PIDR5_OFFSET) // M33_ITM_PIDR5 + // Provides CoreSight discovery information for the ITM + // 0x00000000 [31:0] ITM_PIDR5 (0x00000000) + io_rw_32 itm_pidr5; + + _REG_(M33_ITM_PIDR6_OFFSET) // M33_ITM_PIDR6 + // Provides CoreSight discovery information for the ITM + // 0x00000000 [31:0] ITM_PIDR6 (0x00000000) + io_rw_32 itm_pidr6; + + _REG_(M33_ITM_PIDR7_OFFSET) // M33_ITM_PIDR7 + // Provides CoreSight discovery information for the ITM + // 0x00000000 [31:0] ITM_PIDR7 (0x00000000) + io_rw_32 itm_pidr7; + + _REG_(M33_ITM_PIDR0_OFFSET) // M33_ITM_PIDR0 + // Provides CoreSight discovery information for the ITM + // 0x000000ff [7:0] PART_0 (0x21) See CoreSight Architecture Specification + io_ro_32 itm_pidr0; + + _REG_(M33_ITM_PIDR1_OFFSET) // M33_ITM_PIDR1 + // Provides CoreSight discovery information for the ITM + // 0x000000f0 [7:4] DES_0 (0xb) See CoreSight Architecture Specification + // 0x0000000f [3:0] PART_1 (0xd) See CoreSight Architecture Specification + io_ro_32 itm_pidr1; + + _REG_(M33_ITM_PIDR2_OFFSET) // M33_ITM_PIDR2 + // Provides CoreSight discovery information for the ITM + // 0x000000f0 [7:4] REVISION (0x0) See CoreSight Architecture Specification + // 0x00000008 [3] JEDEC (1) See CoreSight Architecture Specification + // 0x00000007 [2:0] DES_1 (0x3) See CoreSight Architecture Specification + io_ro_32 itm_pidr2; + + _REG_(M33_ITM_PIDR3_OFFSET) // M33_ITM_PIDR3 + // Provides CoreSight discovery information for the ITM + // 0x000000f0 [7:4] REVAND (0x0) See CoreSight Architecture Specification + // 0x0000000f [3:0] CMOD (0x0) See CoreSight Architecture Specification + io_ro_32 itm_pidr3; + + // (Description copied from array index 0 register M33_ITM_CIDR0 applies similarly to other array indexes) + _REG_(M33_ITM_CIDR0_OFFSET) // M33_ITM_CIDR0 + // Provides CoreSight discovery information for the ITM + // 0x000000ff [7:0] PRMBL_0 (0x0d) See CoreSight Architecture Specification + io_ro_32 itm_cidr[4]; + + _REG_(M33_DWT_CTRL_OFFSET) // M33_DWT_CTRL + // Provides configuration and status information for the DWT unit, and used to control features of the unit + // 0xf0000000 [31:28] NUMCOMP (0x7) Number of DWT comparators implemented + // 0x08000000 [27] NOTRCPKT (0) Indicates whether the implementation does not support trace + // 0x04000000 [26] NOEXTTRIG (0) Reserved, RAZ + // 0x02000000 [25] NOCYCCNT (1) Indicates whether the implementation does not include a... + // 0x01000000 [24] NOPRFCNT (1) Indicates whether the implementation does not include... + // 0x00800000 [23] CYCDISS (0) Controls whether the cycle counter is disabled in Secure state + // 0x00400000 [22] CYCEVTENA (1) Enables Event Counter packet generation on POSTCNT underflow + // 0x00200000 [21] FOLDEVTENA (1) Enables DWT_FOLDCNT counter + // 0x00100000 [20] LSUEVTENA (1) Enables DWT_LSUCNT counter + // 0x00080000 [19] SLEEPEVTENA (0) Enable DWT_SLEEPCNT counter + // 0x00040000 [18] EXCEVTENA (1) Enables DWT_EXCCNT counter + // 0x00020000 [17] CPIEVTENA (0) Enables DWT_CPICNT counter + // 0x00010000 [16] EXTTRCENA (0) Enables generation of Exception Trace packets + // 0x00001000 [12] PCSAMPLENA (1) Enables use of POSTCNT counter as a timer for Periodic... + // 0x00000c00 [11:10] SYNCTAP (0x2) Selects the position of the synchronization packet... + // 0x00000200 [9] CYCTAP (0) Selects the position of the POSTCNT tap on the CYCCNT counter + // 0x000001e0 [8:5] POSTINIT (0x1) Initial value for the POSTCNT counter + // 0x0000001e [4:1] POSTPRESET (0x2) Reload value for the POSTCNT counter + // 0x00000001 [0] CYCCNTENA (0) Enables CYCCNT + io_rw_32 dwt_ctrl; + + _REG_(M33_DWT_CYCCNT_OFFSET) // M33_DWT_CYCCNT + // Shows or sets the value of the processor cycle counter, CYCCNT + // 0xffffffff [31:0] CYCCNT (0x00000000) Increments one on each processor clock cycle when DWT_CTRL + io_rw_32 dwt_cyccnt; + + uint32_t _pad8; + + _REG_(M33_DWT_EXCCNT_OFFSET) // M33_DWT_EXCCNT + // Counts the total cycles spent in exception processing + // 0x000000ff [7:0] EXCCNT (0x00) Counts one on each cycle when all of the following are... + io_rw_32 dwt_exccnt; + + uint32_t _pad9; + + _REG_(M33_DWT_LSUCNT_OFFSET) // M33_DWT_LSUCNT + // Increments on the additional cycles required to execute all load or store instructions + // 0x000000ff [7:0] LSUCNT (0x00) Counts one on each cycle when all of the following are... + io_rw_32 dwt_lsucnt; + + _REG_(M33_DWT_FOLDCNT_OFFSET) // M33_DWT_FOLDCNT + // Increments on the additional cycles required to execute all load or store instructions + // 0x000000ff [7:0] FOLDCNT (0x00) Counts on each cycle when all of the following are true:... + io_rw_32 dwt_foldcnt; + + uint32_t _pad10; + + _REG_(M33_DWT_COMP0_OFFSET) // M33_DWT_COMP0 + // Provides a reference value for use by watchpoint comparator 0 + // 0xffffffff [31:0] DWT_COMP0 (0x00000000) + io_rw_32 dwt_comp0; + + uint32_t _pad11; + + _REG_(M33_DWT_FUNCTION0_OFFSET) // M33_DWT_FUNCTION0 + // Controls the operation of watchpoint comparator 0 + // 0xf8000000 [31:27] ID (0x0b) Identifies the capabilities for MATCH for comparator *n + // 0x01000000 [24] MATCHED (0) Set to 1 when the comparator matches + // 0x00000c00 [11:10] DATAVSIZE (0x0) Defines the size of the object being watched for by Data... + // 0x00000030 [5:4] ACTION (0x0) Defines the action on a match + // 0x0000000f [3:0] MATCH (0x0) Controls the type of match generated by this comparator + io_rw_32 dwt_function0; + + uint32_t _pad12; + + _REG_(M33_DWT_COMP1_OFFSET) // M33_DWT_COMP1 + // Provides a reference value for use by watchpoint comparator 1 + // 0xffffffff [31:0] DWT_COMP1 (0x00000000) + io_rw_32 dwt_comp1; + + uint32_t _pad13; + + _REG_(M33_DWT_FUNCTION1_OFFSET) // M33_DWT_FUNCTION1 + // Controls the operation of watchpoint comparator 1 + // 0xf8000000 [31:27] ID (0x11) Identifies the capabilities for MATCH for comparator *n + // 0x01000000 [24] MATCHED (1) Set to 1 when the comparator matches + // 0x00000c00 [11:10] DATAVSIZE (0x2) Defines the size of the object being watched for by Data... + // 0x00000030 [5:4] ACTION (0x2) Defines the action on a match + // 0x0000000f [3:0] MATCH (0x8) Controls the type of match generated by this comparator + io_rw_32 dwt_function1; + + uint32_t _pad14; + + _REG_(M33_DWT_COMP2_OFFSET) // M33_DWT_COMP2 + // Provides a reference value for use by watchpoint comparator 2 + // 0xffffffff [31:0] DWT_COMP2 (0x00000000) + io_rw_32 dwt_comp2; + + uint32_t _pad15; + + _REG_(M33_DWT_FUNCTION2_OFFSET) // M33_DWT_FUNCTION2 + // Controls the operation of watchpoint comparator 2 + // 0xf8000000 [31:27] ID (0x0a) Identifies the capabilities for MATCH for comparator *n + // 0x01000000 [24] MATCHED (0) Set to 1 when the comparator matches + // 0x00000c00 [11:10] DATAVSIZE (0x0) Defines the size of the object being watched for by Data... + // 0x00000030 [5:4] ACTION (0x0) Defines the action on a match + // 0x0000000f [3:0] MATCH (0x0) Controls the type of match generated by this comparator + io_rw_32 dwt_function2; + + uint32_t _pad16; + + _REG_(M33_DWT_COMP3_OFFSET) // M33_DWT_COMP3 + // Provides a reference value for use by watchpoint comparator 3 + // 0xffffffff [31:0] DWT_COMP3 (0x00000000) + io_rw_32 dwt_comp3; + + uint32_t _pad17; + + _REG_(M33_DWT_FUNCTION3_OFFSET) // M33_DWT_FUNCTION3 + // Controls the operation of watchpoint comparator 3 + // 0xf8000000 [31:27] ID (0x04) Identifies the capabilities for MATCH for comparator *n + // 0x01000000 [24] MATCHED (0) Set to 1 when the comparator matches + // 0x00000c00 [11:10] DATAVSIZE (0x2) Defines the size of the object being watched for by Data... + // 0x00000030 [5:4] ACTION (0x0) Defines the action on a match + // 0x0000000f [3:0] MATCH (0x0) Controls the type of match generated by this comparator + io_rw_32 dwt_function3; + + uint32_t _pad18[984]; + + _REG_(M33_DWT_DEVARCH_OFFSET) // M33_DWT_DEVARCH + // Provides CoreSight discovery information for the DWT + // 0xffe00000 [31:21] ARCHITECT (0x23b) Defines the architect of the component + // 0x00100000 [20] PRESENT (1) Defines that the DEVARCH register is present + // 0x000f0000 [19:16] REVISION (0x0) Defines the architecture revision of the component + // 0x0000f000 [15:12] ARCHVER (0x1) Defines the architecture version of the component + // 0x00000fff [11:0] ARCHPART (0xa02) Defines the architecture of the component + io_ro_32 dwt_devarch; + + uint32_t _pad19[3]; + + _REG_(M33_DWT_DEVTYPE_OFFSET) // M33_DWT_DEVTYPE + // Provides CoreSight discovery information for the DWT + // 0x000000f0 [7:4] SUB (0x0) Component sub-type + // 0x0000000f [3:0] MAJOR (0x0) Component major type + io_ro_32 dwt_devtype; + + _REG_(M33_DWT_PIDR4_OFFSET) // M33_DWT_PIDR4 + // Provides CoreSight discovery information for the DWT + // 0x000000f0 [7:4] SIZE (0x0) See CoreSight Architecture Specification + // 0x0000000f [3:0] DES_2 (0x4) See CoreSight Architecture Specification + io_ro_32 dwt_pidr4; + + _REG_(M33_DWT_PIDR5_OFFSET) // M33_DWT_PIDR5 + // Provides CoreSight discovery information for the DWT + // 0x00000000 [31:0] DWT_PIDR5 (0x00000000) + io_rw_32 dwt_pidr5; + + _REG_(M33_DWT_PIDR6_OFFSET) // M33_DWT_PIDR6 + // Provides CoreSight discovery information for the DWT + // 0x00000000 [31:0] DWT_PIDR6 (0x00000000) + io_rw_32 dwt_pidr6; + + _REG_(M33_DWT_PIDR7_OFFSET) // M33_DWT_PIDR7 + // Provides CoreSight discovery information for the DWT + // 0x00000000 [31:0] DWT_PIDR7 (0x00000000) + io_rw_32 dwt_pidr7; + + _REG_(M33_DWT_PIDR0_OFFSET) // M33_DWT_PIDR0 + // Provides CoreSight discovery information for the DWT + // 0x000000ff [7:0] PART_0 (0x21) See CoreSight Architecture Specification + io_ro_32 dwt_pidr0; + + _REG_(M33_DWT_PIDR1_OFFSET) // M33_DWT_PIDR1 + // Provides CoreSight discovery information for the DWT + // 0x000000f0 [7:4] DES_0 (0xb) See CoreSight Architecture Specification + // 0x0000000f [3:0] PART_1 (0xd) See CoreSight Architecture Specification + io_ro_32 dwt_pidr1; + + _REG_(M33_DWT_PIDR2_OFFSET) // M33_DWT_PIDR2 + // Provides CoreSight discovery information for the DWT + // 0x000000f0 [7:4] REVISION (0x0) See CoreSight Architecture Specification + // 0x00000008 [3] JEDEC (1) See CoreSight Architecture Specification + // 0x00000007 [2:0] DES_1 (0x3) See CoreSight Architecture Specification + io_ro_32 dwt_pidr2; + + _REG_(M33_DWT_PIDR3_OFFSET) // M33_DWT_PIDR3 + // Provides CoreSight discovery information for the DWT + // 0x000000f0 [7:4] REVAND (0x0) See CoreSight Architecture Specification + // 0x0000000f [3:0] CMOD (0x0) See CoreSight Architecture Specification + io_ro_32 dwt_pidr3; + + // (Description copied from array index 0 register M33_DWT_CIDR0 applies similarly to other array indexes) + _REG_(M33_DWT_CIDR0_OFFSET) // M33_DWT_CIDR0 + // Provides CoreSight discovery information for the DWT + // 0x000000ff [7:0] PRMBL_0 (0x0d) See CoreSight Architecture Specification + io_ro_32 dwt_cidr[4]; + + _REG_(M33_FP_CTRL_OFFSET) // M33_FP_CTRL + // Provides FPB implementation information, and the global enable for the FPB unit + // 0xf0000000 [31:28] REV (0x6) Flash Patch and Breakpoint Unit architecture revision + // 0x00007000 [14:12] NUM_CODE_14_12_ (0x5) Indicates the number of implemented instruction address... + // 0x00000f00 [11:8] NUM_LIT (0x5) Indicates the number of implemented literal address comparators + // 0x000000f0 [7:4] NUM_CODE_7_4_ (0x8) Indicates the number of implemented instruction address... + // 0x00000002 [1] KEY (0) Writes to the FP_CTRL are ignored unless KEY is... + // 0x00000001 [0] ENABLE (0) Enables the FPB + io_rw_32 fp_ctrl; + + _REG_(M33_FP_REMAP_OFFSET) // M33_FP_REMAP + // Indicates whether the implementation supports Flash Patch remap and, if it does, holds the... + // 0x20000000 [29] RMPSPT (0) Indicates whether the FPB unit supports the Flash Patch... + // 0x1fffffe0 [28:5] REMAP (0x000000) Holds the bits[28:5] of the Flash Patch remap address + io_ro_32 fp_remap; + + // (Description copied from array index 0 register M33_FP_COMP0 applies similarly to other array indexes) + _REG_(M33_FP_COMP0_OFFSET) // M33_FP_COMP0 + // Holds an address for comparison + // 0x00000001 [0] BE (0) Selects between flashpatch and breakpoint functionality + io_rw_32 fp_comp[8]; + + uint32_t _pad20[997]; + + _REG_(M33_FP_DEVARCH_OFFSET) // M33_FP_DEVARCH + // Provides CoreSight discovery information for the FPB + // 0xffe00000 [31:21] ARCHITECT (0x23b) Defines the architect of the component + // 0x00100000 [20] PRESENT (1) Defines that the DEVARCH register is present + // 0x000f0000 [19:16] REVISION (0x0) Defines the architecture revision of the component + // 0x0000f000 [15:12] ARCHVER (0x1) Defines the architecture version of the component + // 0x00000fff [11:0] ARCHPART (0xa03) Defines the architecture of the component + io_ro_32 fp_devarch; + + uint32_t _pad21[3]; + + _REG_(M33_FP_DEVTYPE_OFFSET) // M33_FP_DEVTYPE + // Provides CoreSight discovery information for the FPB + // 0x000000f0 [7:4] SUB (0x0) Component sub-type + // 0x0000000f [3:0] MAJOR (0x0) Component major type + io_ro_32 fp_devtype; + + _REG_(M33_FP_PIDR4_OFFSET) // M33_FP_PIDR4 + // Provides CoreSight discovery information for the FP + // 0x000000f0 [7:4] SIZE (0x0) See CoreSight Architecture Specification + // 0x0000000f [3:0] DES_2 (0x4) See CoreSight Architecture Specification + io_ro_32 fp_pidr4; + + _REG_(M33_FP_PIDR5_OFFSET) // M33_FP_PIDR5 + // Provides CoreSight discovery information for the FP + // 0x00000000 [31:0] FP_PIDR5 (0x00000000) + io_rw_32 fp_pidr5; + + _REG_(M33_FP_PIDR6_OFFSET) // M33_FP_PIDR6 + // Provides CoreSight discovery information for the FP + // 0x00000000 [31:0] FP_PIDR6 (0x00000000) + io_rw_32 fp_pidr6; + + _REG_(M33_FP_PIDR7_OFFSET) // M33_FP_PIDR7 + // Provides CoreSight discovery information for the FP + // 0x00000000 [31:0] FP_PIDR7 (0x00000000) + io_rw_32 fp_pidr7; + + _REG_(M33_FP_PIDR0_OFFSET) // M33_FP_PIDR0 + // Provides CoreSight discovery information for the FP + // 0x000000ff [7:0] PART_0 (0x21) See CoreSight Architecture Specification + io_ro_32 fp_pidr0; + + _REG_(M33_FP_PIDR1_OFFSET) // M33_FP_PIDR1 + // Provides CoreSight discovery information for the FP + // 0x000000f0 [7:4] DES_0 (0xb) See CoreSight Architecture Specification + // 0x0000000f [3:0] PART_1 (0xd) See CoreSight Architecture Specification + io_ro_32 fp_pidr1; + + _REG_(M33_FP_PIDR2_OFFSET) // M33_FP_PIDR2 + // Provides CoreSight discovery information for the FP + // 0x000000f0 [7:4] REVISION (0x0) See CoreSight Architecture Specification + // 0x00000008 [3] JEDEC (1) See CoreSight Architecture Specification + // 0x00000007 [2:0] DES_1 (0x3) See CoreSight Architecture Specification + io_ro_32 fp_pidr2; + + _REG_(M33_FP_PIDR3_OFFSET) // M33_FP_PIDR3 + // Provides CoreSight discovery information for the FP + // 0x000000f0 [7:4] REVAND (0x0) See CoreSight Architecture Specification + // 0x0000000f [3:0] CMOD (0x0) See CoreSight Architecture Specification + io_ro_32 fp_pidr3; + + // (Description copied from array index 0 register M33_FP_CIDR0 applies similarly to other array indexes) + _REG_(M33_FP_CIDR0_OFFSET) // M33_FP_CIDR0 + // Provides CoreSight discovery information for the FP + // 0x000000ff [7:0] PRMBL_0 (0x0d) See CoreSight Architecture Specification + io_ro_32 fp_cidr[4]; + + uint32_t _pad22[11265]; + + _REG_(M33_ICTR_OFFSET) // M33_ICTR + // Provides information about the interrupt controller + // 0x0000000f [3:0] INTLINESNUM (0x1) Indicates the number of the highest implemented register... + io_ro_32 ictr; + + _REG_(M33_ACTLR_OFFSET) // M33_ACTLR + // Provides IMPLEMENTATION DEFINED configuration and control options + // 0x20000000 [29] EXTEXCLALL (0) External Exclusives Allowed with no MPU + // 0x00001000 [12] DISITMATBFLUSH (0) Disable ATB Flush + // 0x00000400 [10] FPEXCODIS (0) Disable FPU exception outputs + // 0x00000200 [9] DISOOFP (0) Disable out-of-order FP instruction completion + // 0x00000004 [2] DISFOLD (0) Disable dual-issue + // 0x00000001 [0] DISMCYCINT (0) Disable dual-issue + io_rw_32 actlr; + + uint32_t _pad23; + + _REG_(M33_SYST_CSR_OFFSET) // M33_SYST_CSR + // SysTick Control and Status Register + // 0x00010000 [16] COUNTFLAG (0) Returns 1 if timer counted to 0 since last time this was read + // 0x00000004 [2] CLKSOURCE (0) SysTick clock source + // 0x00000002 [1] TICKINT (0) Enables SysTick exception request: + + // 0x00000001 [0] ENABLE (0) Enable SysTick counter: + + io_rw_32 syst_csr; + + _REG_(M33_SYST_RVR_OFFSET) // M33_SYST_RVR + // SysTick Reload Value Register + // 0x00ffffff [23:0] RELOAD (0x000000) Value to load into the SysTick Current Value Register... + io_rw_32 syst_rvr; + + _REG_(M33_SYST_CVR_OFFSET) // M33_SYST_CVR + // SysTick Current Value Register + // 0x00ffffff [23:0] CURRENT (0x000000) Reads return the current value of the SysTick counter + io_rw_32 syst_cvr; + + _REG_(M33_SYST_CALIB_OFFSET) // M33_SYST_CALIB + // SysTick Calibration Value Register + // 0x80000000 [31] NOREF (0) If reads as 1, the Reference clock is not provided - the... + // 0x40000000 [30] SKEW (0) If reads as 1, the calibration value for 10ms is inexact... + // 0x00ffffff [23:0] TENMS (0x000000) An optional Reload value to be used for 10ms (100Hz)... + io_ro_32 syst_calib; + + uint32_t _pad24[56]; + + // (Description copied from array index 0 register M33_NVIC_ISER0 applies similarly to other array indexes) + _REG_(M33_NVIC_ISER0_OFFSET) // M33_NVIC_ISER0 + // Enables or reads the enabled state of each group of 32 interrupts + // 0xffffffff [31:0] SETENA (0x00000000) For SETENA[m] in NVIC_ISER*n, indicates whether... + io_rw_32 nvic_iser[2]; + + uint32_t _pad25[30]; + + // (Description copied from array index 0 register M33_NVIC_ICER0 applies similarly to other array indexes) + _REG_(M33_NVIC_ICER0_OFFSET) // M33_NVIC_ICER0 + // Clears or reads the enabled state of each group of 32 interrupts + // 0xffffffff [31:0] CLRENA (0x00000000) For CLRENA[m] in NVIC_ICER*n, indicates whether... + io_rw_32 nvic_icer[2]; + + uint32_t _pad26[30]; + + // (Description copied from array index 0 register M33_NVIC_ISPR0 applies similarly to other array indexes) + _REG_(M33_NVIC_ISPR0_OFFSET) // M33_NVIC_ISPR0 + // Enables or reads the pending state of each group of 32 interrupts + // 0xffffffff [31:0] SETPEND (0x00000000) For SETPEND[m] in NVIC_ISPR*n, indicates whether... + io_rw_32 nvic_ispr[2]; + + uint32_t _pad27[30]; + + // (Description copied from array index 0 register M33_NVIC_ICPR0 applies similarly to other array indexes) + _REG_(M33_NVIC_ICPR0_OFFSET) // M33_NVIC_ICPR0 + // Clears or reads the pending state of each group of 32 interrupts + // 0xffffffff [31:0] CLRPEND (0x00000000) For CLRPEND[m] in NVIC_ICPR*n, indicates whether... + io_rw_32 nvic_icpr[2]; + + uint32_t _pad28[30]; + + // (Description copied from array index 0 register M33_NVIC_IABR0 applies similarly to other array indexes) + _REG_(M33_NVIC_IABR0_OFFSET) // M33_NVIC_IABR0 + // For each group of 32 interrupts, shows the active state of each interrupt + // 0xffffffff [31:0] ACTIVE (0x00000000) For ACTIVE[m] in NVIC_IABR*n, indicates the active state... + io_rw_32 nvic_iabr[2]; + + uint32_t _pad29[30]; + + // (Description copied from array index 0 register M33_NVIC_ITNS0 applies similarly to other array indexes) + _REG_(M33_NVIC_ITNS0_OFFSET) // M33_NVIC_ITNS0 + // For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state + // 0xffffffff [31:0] ITNS (0x00000000) For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security... + io_rw_32 nvic_itns[2]; + + uint32_t _pad30[30]; + + // (Description copied from array index 0 register M33_NVIC_IPR0 applies similarly to other array indexes) + _REG_(M33_NVIC_IPR0_OFFSET) // M33_NVIC_IPR0 + // Sets or reads interrupt priorities + // 0xf0000000 [31:28] PRI_N3 (0x0) For register NVIC_IPRn, the priority of interrupt number... + // 0x00f00000 [23:20] PRI_N2 (0x0) For register NVIC_IPRn, the priority of interrupt number... + // 0x0000f000 [15:12] PRI_N1 (0x0) For register NVIC_IPRn, the priority of interrupt number... + // 0x000000f0 [7:4] PRI_N0 (0x0) For register NVIC_IPRn, the priority of interrupt number... + io_rw_32 nvic_ipr[16]; + + uint32_t _pad31[560]; + + _REG_(M33_CPUID_OFFSET) // M33_CPUID + // Provides identification information for the PE, including an implementer code for the device and... + // 0xff000000 [31:24] IMPLEMENTER (0x41) This field must hold an implementer code that has been... + // 0x00f00000 [23:20] VARIANT (0x1) IMPLEMENTATION DEFINED variant number + // 0x000f0000 [19:16] ARCHITECTURE (0xf) Defines the Architecture implemented by the PE + // 0x0000fff0 [15:4] PARTNO (0xd21) IMPLEMENTATION DEFINED primary part number for the device + // 0x0000000f [3:0] REVISION (0x0) IMPLEMENTATION DEFINED revision number for the device + io_ro_32 cpuid; + + _REG_(M33_ICSR_OFFSET) // M33_ICSR + // Controls and provides status information for NMI, PendSV, SysTick and interrupts + // 0x80000000 [31] PENDNMISET (0) Indicates whether the NMI exception is pending + // 0x40000000 [30] PENDNMICLR (0) Allows the NMI exception pend state to be cleared + // 0x10000000 [28] PENDSVSET (0) Indicates whether the PendSV `FTSSS exception is pending + // 0x08000000 [27] PENDSVCLR (0) Allows the PendSV exception pend state to be cleared `FTSSS + // 0x04000000 [26] PENDSTSET (0) Indicates whether the SysTick `FTSSS exception is pending + // 0x02000000 [25] PENDSTCLR (0) Allows the SysTick exception pend state to be cleared `FTSSS + // 0x01000000 [24] STTNS (0) Controls whether in a single SysTick implementation, the... + // 0x00800000 [23] ISRPREEMPT (0) Indicates whether a pending exception will be serviced... + // 0x00400000 [22] ISRPENDING (0) Indicates whether an external interrupt, generated by... + // 0x001ff000 [20:12] VECTPENDING (0x000) The exception number of the highest priority pending and... + // 0x00000800 [11] RETTOBASE (0) In Handler mode, indicates whether there is more than... + // 0x000001ff [8:0] VECTACTIVE (0x000) The exception number of the current executing exception + io_rw_32 icsr; + + _REG_(M33_VTOR_OFFSET) // M33_VTOR + // Vector Table Offset Register + // 0xffffff80 [31:7] TBLOFF (0x0000000) Vector table base offset field + io_rw_32 vtor; + + _REG_(M33_AIRCR_OFFSET) // M33_AIRCR + // Application Interrupt and Reset Control Register + // 0xffff0000 [31:16] VECTKEY (0x0000) Register key: + + // 0x00008000 [15] ENDIANESS (0) Data endianness implemented: + + // 0x00004000 [14] PRIS (0) Prioritize Secure exceptions + // 0x00002000 [13] BFHFNMINS (0) BusFault, HardFault, and NMI Non-secure enable + // 0x00000700 [10:8] PRIGROUP (0x0) Interrupt priority grouping field + // 0x00000008 [3] SYSRESETREQS (0) System reset request, Secure state only + // 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to... + // 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and... + io_rw_32 aircr; + + _REG_(M33_SCR_OFFSET) // M33_SCR + // System Control Register + // 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: + + // 0x00000008 [3] SLEEPDEEPS (0) 0 SLEEPDEEP is available to both security states + + // 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep... + // 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode... + io_rw_32 scr; + + _REG_(M33_CCR_OFFSET) // M33_CCR + // Sets or returns configuration and control data + // 0x00040000 [18] BP (0) Enables program flow prediction `FTSSS + // 0x00020000 [17] IC (0) This is a global enable bit for instruction caches in... + // 0x00010000 [16] DC (0) Enables data caching of all data accesses to Normal memory `FTSSS + // 0x00000400 [10] STKOFHFNMIGN (0) Controls the effect of a stack limit violation while... + // 0x00000200 [9] RES1 (1) Reserved, RES1 + // 0x00000100 [8] BFHFNMIGN (0) Determines the effect of precise BusFaults on handlers... + // 0x00000010 [4] DIV_0_TRP (0) Controls the generation of a DIVBYZERO UsageFault when... + // 0x00000008 [3] UNALIGN_TRP (0) Controls the trapping of unaligned word or halfword accesses + // 0x00000002 [1] USERSETMPEND (0) Determines whether unprivileged accesses are permitted... + // 0x00000001 [0] RES1_1 (1) Reserved, RES1 + io_rw_32 ccr; + + // (Description copied from array index 0 register M33_SHPR1 applies similarly to other array indexes) + _REG_(M33_SHPR1_OFFSET) // M33_SHPR1 + // Sets or returns priority for system handlers 4 - 7 + // 0xe0000000 [31:29] PRI_7_3 (0x0) Priority of system handler 7, SecureFault + // 0x00e00000 [23:21] PRI_6_3 (0x0) Priority of system handler 6, SecureFault + // 0x0000e000 [15:13] PRI_5_3 (0x0) Priority of system handler 5, SecureFault + // 0x000000e0 [7:5] PRI_4_3 (0x0) Priority of system handler 4, SecureFault + io_rw_32 shpr[3]; + + _REG_(M33_SHCSR_OFFSET) // M33_SHCSR + // Provides access to the active and pending status of system exceptions + // 0x00200000 [21] HARDFAULTPENDED (0) `IAAMO the pending state of the HardFault exception `CTTSSS + // 0x00100000 [20] SECUREFAULTPENDED (0) `IAAMO the pending state of the SecureFault exception + // 0x00080000 [19] SECUREFAULTENA (0) `DW the SecureFault exception is enabled + // 0x00040000 [18] USGFAULTENA (0) `DW the UsageFault exception is enabled `FTSSS + // 0x00020000 [17] BUSFAULTENA (0) `DW the BusFault exception is enabled + // 0x00010000 [16] MEMFAULTENA (0) `DW the MemManage exception is enabled `FTSSS + // 0x00008000 [15] SVCALLPENDED (0) `IAAMO the pending state of the SVCall exception `FTSSS + // 0x00004000 [14] BUSFAULTPENDED (0) `IAAMO the pending state of the BusFault exception + // 0x00002000 [13] MEMFAULTPENDED (0) `IAAMO the pending state of the MemManage exception `FTSSS + // 0x00001000 [12] USGFAULTPENDED (0) The UsageFault exception is banked between Security... + // 0x00000800 [11] SYSTICKACT (0) `IAAMO the active state of the SysTick exception `FTSSS + // 0x00000400 [10] PENDSVACT (0) `IAAMO the active state of the PendSV exception `FTSSS + // 0x00000100 [8] MONITORACT (0) `IAAMO the active state of the DebugMonitor exception + // 0x00000080 [7] SVCALLACT (0) `IAAMO the active state of the SVCall exception `FTSSS + // 0x00000020 [5] NMIACT (0) `IAAMO the active state of the NMI exception + // 0x00000010 [4] SECUREFAULTACT (0) `IAAMO the active state of the SecureFault exception + // 0x00000008 [3] USGFAULTACT (0) `IAAMO the active state of the UsageFault exception `FTSSS + // 0x00000004 [2] HARDFAULTACT (0) Indicates and allows limited modification of the active... + // 0x00000002 [1] BUSFAULTACT (0) `IAAMO the active state of the BusFault exception + // 0x00000001 [0] MEMFAULTACT (0) `IAAMO the active state of the MemManage exception `FTSSS + io_rw_32 shcsr; + + _REG_(M33_CFSR_OFFSET) // M33_CFSR + // Contains the three Configurable Fault Status Registers + // 0x02000000 [25] UFSR_DIVBYZERO (0) Sticky flag indicating whether an integer division by... + // 0x01000000 [24] UFSR_UNALIGNED (0) Sticky flag indicating whether an unaligned access error... + // 0x00100000 [20] UFSR_STKOF (0) Sticky flag indicating whether a stack overflow error... + // 0x00080000 [19] UFSR_NOCP (0) Sticky flag indicating whether a coprocessor disabled or... + // 0x00040000 [18] UFSR_INVPC (0) Sticky flag indicating whether an integrity check error... + // 0x00020000 [17] UFSR_INVSTATE (0) Sticky flag indicating whether an EPSR + // 0x00010000 [16] UFSR_UNDEFINSTR (0) Sticky flag indicating whether an undefined instruction... + // 0x00008000 [15] BFSR_BFARVALID (0) Indicates validity of the contents of the BFAR register + // 0x00002000 [13] BFSR_LSPERR (0) Records whether a BusFault occurred during FP lazy state... + // 0x00001000 [12] BFSR_STKERR (0) Records whether a derived BusFault occurred during... + // 0x00000800 [11] BFSR_UNSTKERR (0) Records whether a derived BusFault occurred during... + // 0x00000400 [10] BFSR_IMPRECISERR (0) Records whether an imprecise data access error has occurred + // 0x00000200 [9] BFSR_PRECISERR (0) Records whether a precise data access error has occurred + // 0x00000100 [8] BFSR_IBUSERR (0) Records whether a BusFault on an instruction prefetch... + // 0x000000ff [7:0] MMFSR (0x00) Provides information on MemManage exceptions + io_rw_32 cfsr; + + _REG_(M33_HFSR_OFFSET) // M33_HFSR + // Shows the cause of any HardFaults + // 0x80000000 [31] DEBUGEVT (0) Indicates when a Debug event has occurred + // 0x40000000 [30] FORCED (0) Indicates that a fault with configurable priority has... + // 0x00000002 [1] VECTTBL (0) Indicates when a fault has occurred because of a vector... + io_rw_32 hfsr; + + _REG_(M33_DFSR_OFFSET) // M33_DFSR + // Shows which debug event occurred + // 0x00000010 [4] EXTERNAL (0) Sticky flag indicating whether an External debug request... + // 0x00000008 [3] VCATCH (0) Sticky flag indicating whether a Vector catch debug... + // 0x00000004 [2] DWTTRAP (0) Sticky flag indicating whether a Watchpoint debug event... + // 0x00000002 [1] BKPT (0) Sticky flag indicating whether a Breakpoint debug event... + // 0x00000001 [0] HALTED (0) Sticky flag indicating that a Halt request debug event... + io_rw_32 dfsr; + + _REG_(M33_MMFAR_OFFSET) // M33_MMFAR + // Shows the address of the memory location that caused an MPU fault + // 0xffffffff [31:0] ADDRESS (0x00000000) This register is updated with the address of a location... + io_rw_32 mmfar; + + _REG_(M33_BFAR_OFFSET) // M33_BFAR + // Shows the address associated with a precise data access BusFault + // 0xffffffff [31:0] ADDRESS (0x00000000) This register is updated with the address of a location... + io_rw_32 bfar; + + uint32_t _pad32; + + // (Description copied from array index 0 register M33_ID_PFR0 applies similarly to other array indexes) + _REG_(M33_ID_PFR0_OFFSET) // M33_ID_PFR0 + // Gives top-level information about the instruction set supported by the PE + // 0x000000f0 [7:4] STATE1 (0x3) T32 instruction set support + // 0x0000000f [3:0] STATE0 (0x0) A32 instruction set support + io_ro_32 id_pfr[2]; + + _REG_(M33_ID_DFR0_OFFSET) // M33_ID_DFR0 + // Provides top level information about the debug system + // 0x00f00000 [23:20] MPROFDBG (0x2) Indicates the supported M-profile debug architecture + io_ro_32 id_dfr0; + + _REG_(M33_ID_AFR0_OFFSET) // M33_ID_AFR0 + // Provides information about the IMPLEMENTATION DEFINED features of the PE + // 0x0000f000 [15:12] IMPDEF3 (0x0) IMPLEMENTATION DEFINED meaning + // 0x00000f00 [11:8] IMPDEF2 (0x0) IMPLEMENTATION DEFINED meaning + // 0x000000f0 [7:4] IMPDEF1 (0x0) IMPLEMENTATION DEFINED meaning + // 0x0000000f [3:0] IMPDEF0 (0x0) IMPLEMENTATION DEFINED meaning + io_ro_32 id_afr0; + + // (Description copied from array index 0 register M33_ID_MMFR0 applies similarly to other array indexes) + _REG_(M33_ID_MMFR0_OFFSET) // M33_ID_MMFR0 + // Provides information about the implemented memory model and memory management support + // 0x00f00000 [23:20] AUXREG (0x1) Indicates support for Auxiliary Control Registers + // 0x000f0000 [19:16] TCM (0x0) Indicates support for tightly coupled memories (TCMs) + // 0x0000f000 [15:12] SHARELVL (0x1) Indicates the number of shareability levels implemented + // 0x00000f00 [11:8] OUTERSHR (0xf) Indicates the outermost shareability domain implemented + // 0x000000f0 [7:4] PMSA (0x4) Indicates support for the protected memory system... + io_ro_32 id_mmfr[4]; + + // (Description copied from array index 0 register M33_ID_ISAR0 applies similarly to other array indexes) + _REG_(M33_ID_ISAR0_OFFSET) // M33_ID_ISAR0 + // Provides information about the instruction set implemented by the PE + // 0x0f000000 [27:24] DIVIDE (0x8) Indicates the supported Divide instructions + // 0x00f00000 [23:20] DEBUG (0x0) Indicates the implemented Debug instructions + // 0x000f0000 [19:16] COPROC (0x9) Indicates the supported Coprocessor instructions + // 0x0000f000 [15:12] CMPBRANCH (0x2) Indicates the supported combined Compare and Branch instructions + // 0x00000f00 [11:8] BITFIELD (0x3) Indicates the supported bit field instructions + // 0x000000f0 [7:4] BITCOUNT (0x0) Indicates the supported bit count instructions + io_ro_32 id_isar[6]; + + uint32_t _pad33; + + _REG_(M33_CTR_OFFSET) // M33_CTR + // Provides information about the architecture of the caches + // 0x80000000 [31] RES1 (1) Reserved, RES1 + // 0x0f000000 [27:24] CWG (0x0) Log2 of the number of words of the maximum size of... + // 0x00f00000 [23:20] ERG (0x0) Log2 of the number of words of the maximum size of the... + // 0x000f0000 [19:16] DMINLINE (0x0) Log2 of the number of words in the smallest cache line... + // 0x0000c000 [15:14] RES1_1 (0x3) Reserved, RES1 + // 0x0000000f [3:0] IMINLINE (0x0) Log2 of the number of words in the smallest cache line... + io_ro_32 ctr; + + uint32_t _pad34[2]; + + _REG_(M33_CPACR_OFFSET) // M33_CPACR + // Specifies the access privileges for coprocessors and the FP Extension + // 0x00c00000 [23:22] CP11 (0x0) The value in this field is ignored + // 0x00300000 [21:20] CP10 (0x0) Defines the access rights for the floating-point functionality + // 0x0000c000 [15:14] CP7 (0x0) Controls access privileges for coprocessor 7 + // 0x00003000 [13:12] CP6 (0x0) Controls access privileges for coprocessor 6 + // 0x00000c00 [11:10] CP5 (0x0) Controls access privileges for coprocessor 5 + // 0x00000300 [9:8] CP4 (0x0) Controls access privileges for coprocessor 4 + // 0x000000c0 [7:6] CP3 (0x0) Controls access privileges for coprocessor 3 + // 0x00000030 [5:4] CP2 (0x0) Controls access privileges for coprocessor 2 + // 0x0000000c [3:2] CP1 (0x0) Controls access privileges for coprocessor 1 + // 0x00000003 [1:0] CP0 (0x0) Controls access privileges for coprocessor 0 + io_rw_32 cpacr; + + _REG_(M33_NSACR_OFFSET) // M33_NSACR + // Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7 + // 0x00000800 [11] CP11 (0) Enables Non-secure access to the Floating-point Extension + // 0x00000400 [10] CP10 (0) Enables Non-secure access to the Floating-point Extension + // 0x00000080 [7] CP7 (0) Enables Non-secure access to coprocessor CP7 + // 0x00000040 [6] CP6 (0) Enables Non-secure access to coprocessor CP6 + // 0x00000020 [5] CP5 (0) Enables Non-secure access to coprocessor CP5 + // 0x00000010 [4] CP4 (0) Enables Non-secure access to coprocessor CP4 + // 0x00000008 [3] CP3 (0) Enables Non-secure access to coprocessor CP3 + // 0x00000004 [2] CP2 (0) Enables Non-secure access to coprocessor CP2 + // 0x00000002 [1] CP1 (0) Enables Non-secure access to coprocessor CP1 + // 0x00000001 [0] CP0 (0) Enables Non-secure access to coprocessor CP0 + io_rw_32 nsacr; + + _REG_(M33_MPU_TYPE_OFFSET) // M33_MPU_TYPE + // The MPU Type Register indicates how many regions the MPU `FTSSS supports + // 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU + // 0x00000001 [0] SEPARATE (0) Indicates support for separate instructions and data... + io_ro_32 mpu_type; + + _REG_(M33_MPU_CTRL_OFFSET) // M33_MPU_CTRL + // Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled... + // 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled for... + // 0x00000002 [1] HFNMIENA (0) Controls whether handlers executing with priority less... + // 0x00000001 [0] ENABLE (0) Enables the MPU + io_rw_32 mpu_ctrl; + + _REG_(M33_MPU_RNR_OFFSET) // M33_MPU_RNR + // Selects the region currently accessed by MPU_RBAR and MPU_RLAR + // 0x00000007 [2:0] REGION (0x0) Indicates the memory region accessed by MPU_RBAR and MPU_RLAR + io_rw_32 mpu_rnr; + + _REG_(M33_MPU_RBAR_OFFSET) // M33_MPU_RBAR + // Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS + // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... + // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory + // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region + // 0x00000001 [0] XN (0) Defines whether code can be executed from this region + io_rw_32 mpu_rbar; + + _REG_(M33_MPU_RLAR_OFFSET) // M33_MPU_RLAR + // Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS + // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... + // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... + // 0x00000001 [0] EN (0) Region enable + io_rw_32 mpu_rlar; + + _REG_(M33_MPU_RBAR_A1_OFFSET) // M33_MPU_RBAR_A1 + // Provides indirect read and write access to the base address of the MPU region selected by... + // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... + // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory + // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region + // 0x00000001 [0] XN (0) Defines whether code can be executed from this region + io_rw_32 mpu_rbar_a1; + + _REG_(M33_MPU_RLAR_A1_OFFSET) // M33_MPU_RLAR_A1 + // Provides indirect read and write access to the limit address of the currently selected MPU... + // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... + // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... + // 0x00000001 [0] EN (0) Region enable + io_rw_32 mpu_rlar_a1; + + _REG_(M33_MPU_RBAR_A2_OFFSET) // M33_MPU_RBAR_A2 + // Provides indirect read and write access to the base address of the MPU region selected by... + // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... + // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory + // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region + // 0x00000001 [0] XN (0) Defines whether code can be executed from this region + io_rw_32 mpu_rbar_a2; + + _REG_(M33_MPU_RLAR_A2_OFFSET) // M33_MPU_RLAR_A2 + // Provides indirect read and write access to the limit address of the currently selected MPU... + // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... + // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... + // 0x00000001 [0] EN (0) Region enable + io_rw_32 mpu_rlar_a2; + + _REG_(M33_MPU_RBAR_A3_OFFSET) // M33_MPU_RBAR_A3 + // Provides indirect read and write access to the base address of the MPU region selected by... + // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... + // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory + // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region + // 0x00000001 [0] XN (0) Defines whether code can be executed from this region + io_rw_32 mpu_rbar_a3; + + _REG_(M33_MPU_RLAR_A3_OFFSET) // M33_MPU_RLAR_A3 + // Provides indirect read and write access to the limit address of the currently selected MPU... + // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... + // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... + // 0x00000001 [0] EN (0) Region enable + io_rw_32 mpu_rlar_a3; + + uint32_t _pad35; + + // (Description copied from array index 0 register M33_MPU_MAIR0 applies similarly to other array indexes) + _REG_(M33_MPU_MAIR0_OFFSET) // M33_MPU_MAIR0 + // Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values + // 0xff000000 [31:24] ATTR3 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 3 + // 0x00ff0000 [23:16] ATTR2 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 2 + // 0x0000ff00 [15:8] ATTR1 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 1 + // 0x000000ff [7:0] ATTR0 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 0 + io_rw_32 mpu_mair[2]; + + uint32_t _pad36[2]; + + _REG_(M33_SAU_CTRL_OFFSET) // M33_SAU_CTRL + // Allows enabling of the Security Attribution Unit + // 0x00000002 [1] ALLNS (0) When SAU_CTRL + // 0x00000001 [0] ENABLE (0) Enables the SAU + io_rw_32 sau_ctrl; + + _REG_(M33_SAU_TYPE_OFFSET) // M33_SAU_TYPE + // Indicates the number of regions implemented by the Security Attribution Unit + // 0x000000ff [7:0] SREGION (0x08) The number of implemented SAU regions + io_ro_32 sau_type; + + _REG_(M33_SAU_RNR_OFFSET) // M33_SAU_RNR + // Selects the region currently accessed by SAU_RBAR and SAU_RLAR + // 0x000000ff [7:0] REGION (0x00) Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR + io_rw_32 sau_rnr; + + _REG_(M33_SAU_RBAR_OFFSET) // M33_SAU_RBAR + // Provides indirect read and write access to the base address of the currently selected SAU region + // 0xffffffe0 [31:5] BADDR (0x0000000) Holds bits [31:5] of the base address for the selected SAU region + io_rw_32 sau_rbar; + + _REG_(M33_SAU_RLAR_OFFSET) // M33_SAU_RLAR + // Provides indirect read and write access to the limit address of the currently selected SAU region + // 0xffffffe0 [31:5] LADDR (0x0000000) Holds bits [31:5] of the limit address for the selected... + // 0x00000002 [1] NSC (0) Controls whether Non-secure state is permitted to... + // 0x00000001 [0] ENABLE (0) SAU region enable + io_rw_32 sau_rlar; + + _REG_(M33_SFSR_OFFSET) // M33_SFSR + // Provides information about any security related faults + // 0x00000080 [7] LSERR (0) Sticky flag indicating that an error occurred during... + // 0x00000040 [6] SFARVALID (0) This bit is set when the SFAR register contains a valid value + // 0x00000020 [5] LSPERR (0) Stick flag indicating that an SAU or IDAU violation... + // 0x00000010 [4] INVTRAN (0) Sticky flag indicating that an exception was raised due... + // 0x00000008 [3] AUVIOL (0) Sticky flag indicating that an attempt was made to... + // 0x00000004 [2] INVER (0) This can be caused by EXC_RETURN + // 0x00000002 [1] INVIS (0) This bit is set if the integrity signature in an... + // 0x00000001 [0] INVEP (0) This bit is set if a function call from the Non-secure... + io_rw_32 sfsr; + + _REG_(M33_SFAR_OFFSET) // M33_SFAR + // Shows the address of the memory location that caused a Security violation + // 0xffffffff [31:0] ADDRESS (0x00000000) The address of an access that caused a attribution unit violation + io_rw_32 sfar; + + uint32_t _pad37; + + _REG_(M33_DHCSR_OFFSET) // M33_DHCSR + // Controls halting debug + // 0x04000000 [26] S_RESTART_ST (0) Indicates the PE has processed a request to clear DHCSR + // 0x02000000 [25] S_RESET_ST (0) Indicates whether the PE has been reset since the last... + // 0x01000000 [24] S_RETIRE_ST (0) Set to 1 every time the PE retires one of more instructions + // 0x00100000 [20] S_SDE (0) Indicates whether Secure invasive debug is allowed + // 0x00080000 [19] S_LOCKUP (0) Indicates whether the PE is in Lockup state + // 0x00040000 [18] S_SLEEP (0) Indicates whether the PE is sleeping + // 0x00020000 [17] S_HALT (0) Indicates whether the PE is in Debug state + // 0x00010000 [16] S_REGRDY (0) Handshake flag to transfers through the DCRDR + // 0x00000020 [5] C_SNAPSTALL (0) Allow imprecise entry to Debug state + // 0x00000008 [3] C_MASKINTS (0) When debug is enabled, the debugger can write to this... + // 0x00000004 [2] C_STEP (0) Enable single instruction step + // 0x00000002 [1] C_HALT (0) PE enter Debug state halt request + // 0x00000001 [0] C_DEBUGEN (0) Enable Halting debug + io_rw_32 dhcsr; + + _REG_(M33_DCRSR_OFFSET) // M33_DCRSR + // With the DCRDR, provides debug access to the general-purpose registers, special-purpose... + // 0x00010000 [16] REGWNR (0) Specifies the access type for the transfer + // 0x0000007f [6:0] REGSEL (0x00) Specifies the general-purpose register, special-purpose... + io_rw_32 dcrsr; + + _REG_(M33_DCRDR_OFFSET) // M33_DCRDR + // With the DCRSR, provides debug access to the general-purpose registers, special-purpose... + // 0xffffffff [31:0] DBGTMP (0x00000000) Provides debug access for reading and writing the... + io_rw_32 dcrdr; + + _REG_(M33_DEMCR_OFFSET) // M33_DEMCR + // Manages vector catch behavior and DebugMonitor handling when debugging + // 0x01000000 [24] TRCENA (0) Global enable for all DWT and ITM features + // 0x00100000 [20] SDME (0) Indicates whether the DebugMonitor targets the Secure or... + // 0x00080000 [19] MON_REQ (0) DebugMonitor semaphore bit + // 0x00040000 [18] MON_STEP (0) Enable DebugMonitor stepping + // 0x00020000 [17] MON_PEND (0) Sets or clears the pending state of the DebugMonitor exception + // 0x00010000 [16] MON_EN (0) Enable the DebugMonitor exception + // 0x00000800 [11] VC_SFERR (0) SecureFault exception halting debug vector catch enable + // 0x00000400 [10] VC_HARDERR (0) HardFault exception halting debug vector catch enable + // 0x00000200 [9] VC_INTERR (0) Enable halting debug vector catch for faults during... + // 0x00000100 [8] VC_BUSERR (0) BusFault exception halting debug vector catch enable + // 0x00000080 [7] VC_STATERR (0) Enable halting debug trap on a UsageFault exception... + // 0x00000040 [6] VC_CHKERR (0) Enable halting debug trap on a UsageFault exception... + // 0x00000020 [5] VC_NOCPERR (0) Enable halting debug trap on a UsageFault caused by an... + // 0x00000010 [4] VC_MMERR (0) Enable halting debug trap on a MemManage exception + // 0x00000001 [0] VC_CORERESET (0) Enable Reset Vector Catch + io_rw_32 demcr; + + uint32_t _pad38[2]; + + _REG_(M33_DSCSR_OFFSET) // M33_DSCSR + // Provides control and status information for Secure debug + // 0x00020000 [17] CDSKEY (0) Writes to the CDS bit are ignored unless CDSKEY is... + // 0x00010000 [16] CDS (0) This field indicates the current Security state of the processor + // 0x00000002 [1] SBRSEL (0) If SBRSELEN is 1 this bit selects whether the Non-secure... + // 0x00000001 [0] SBRSELEN (0) Controls whether the SBRSEL field or the current... + io_rw_32 dscsr; + + uint32_t _pad39[61]; + + _REG_(M33_STIR_OFFSET) // M33_STIR + // Provides a mechanism for software to generate an interrupt + // 0x000001ff [8:0] INTID (0x000) Indicates the interrupt to be pended + io_rw_32 stir; + + uint32_t _pad40[12]; + + _REG_(M33_FPCCR_OFFSET) // M33_FPCCR + // Holds control data for the Floating-point extension + // 0x80000000 [31] ASPEN (0) When this bit is set to 1, execution of a floating-point... + // 0x40000000 [30] LSPEN (0) Enables lazy context save of floating-point state + // 0x20000000 [29] LSPENS (1) This bit controls whether the LSPEN bit is writeable... + // 0x10000000 [28] CLRONRET (0) Clear floating-point caller saved registers on exception return + // 0x08000000 [27] CLRONRETS (0) This bit controls whether the CLRONRET bit is writeable... + // 0x04000000 [26] TS (0) Treat floating-point registers as Secure enable + // 0x00000400 [10] UFRDY (1) Indicates whether the software executing when the PE... + // 0x00000200 [9] SPLIMVIOL (0) This bit is banked between the Security states and... + // 0x00000100 [8] MONRDY (0) Indicates whether the software executing when the PE... + // 0x00000080 [7] SFRDY (0) Indicates whether the software executing when the PE... + // 0x00000040 [6] BFRDY (1) Indicates whether the software executing when the PE... + // 0x00000020 [5] MMRDY (1) Indicates whether the software executing when the PE... + // 0x00000010 [4] HFRDY (1) Indicates whether the software executing when the PE... + // 0x00000008 [3] THREAD (0) Indicates the PE mode when it allocated the... + // 0x00000004 [2] S (0) Security status of the floating-point context + // 0x00000002 [1] USER (1) Indicates the privilege level of the software executing... + // 0x00000001 [0] LSPACT (0) Indicates whether lazy preservation of the... + io_rw_32 fpccr; + + _REG_(M33_FPCAR_OFFSET) // M33_FPCAR + // Holds the location of the unpopulated floating-point register space allocated on an exception stack frame + // 0xfffffff8 [31:3] ADDRESS (0x00000000) The location of the unpopulated floating-point register... + io_rw_32 fpcar; + + _REG_(M33_FPDSCR_OFFSET) // M33_FPDSCR + // Holds the default values for the floating-point status control data that the PE assigns to the... + // 0x04000000 [26] AHP (0) Default value for FPSCR + // 0x02000000 [25] DN (0) Default value for FPSCR + // 0x01000000 [24] FZ (0) Default value for FPSCR + // 0x00c00000 [23:22] RMODE (0x0) Default value for FPSCR + io_rw_32 fpdscr; + + // (Description copied from array index 0 register M33_MVFR0 applies similarly to other array indexes) + _REG_(M33_MVFR0_OFFSET) // M33_MVFR0 + // Describes the features provided by the Floating-point Extension + // 0xf0000000 [31:28] FPROUND (0x6) Indicates the rounding modes supported by the FP Extension + // 0x00f00000 [23:20] FPSQRT (0x5) Indicates the support for FP square root operations + // 0x000f0000 [19:16] FPDIVIDE (0x4) Indicates the support for FP divide operations + // 0x00000f00 [11:8] FPDP (0x6) Indicates support for FP double-precision operations + // 0x000000f0 [7:4] FPSP (0x0) Indicates support for FP single-precision operations + // 0x0000000f [3:0] SIMDREG (0x1) Indicates size of FP register file + io_ro_32 mvfr[3]; + + uint32_t _pad41[28]; + + _REG_(M33_DDEVARCH_OFFSET) // M33_DDEVARCH + // Provides CoreSight discovery information for the SCS + // 0xffe00000 [31:21] ARCHITECT (0x23b) Defines the architect of the component + // 0x00100000 [20] PRESENT (1) Defines that the DEVARCH register is present + // 0x000f0000 [19:16] REVISION (0x0) Defines the architecture revision of the component + // 0x0000f000 [15:12] ARCHVER (0x2) Defines the architecture version of the component + // 0x00000fff [11:0] ARCHPART (0xa04) Defines the architecture of the component + io_ro_32 ddevarch; + + uint32_t _pad42[3]; + + _REG_(M33_DDEVTYPE_OFFSET) // M33_DDEVTYPE + // Provides CoreSight discovery information for the SCS + // 0x000000f0 [7:4] SUB (0x0) Component sub-type + // 0x0000000f [3:0] MAJOR (0x0) CoreSight major type + io_ro_32 ddevtype; + + _REG_(M33_DPIDR4_OFFSET) // M33_DPIDR4 + // Provides CoreSight discovery information for the SCS + // 0x000000f0 [7:4] SIZE (0x0) See CoreSight Architecture Specification + // 0x0000000f [3:0] DES_2 (0x4) See CoreSight Architecture Specification + io_ro_32 dpidr4; + + _REG_(M33_DPIDR5_OFFSET) // M33_DPIDR5 + // Provides CoreSight discovery information for the SCS + // 0x00000000 [31:0] DPIDR5 (0x00000000) + io_rw_32 dpidr5; + + _REG_(M33_DPIDR6_OFFSET) // M33_DPIDR6 + // Provides CoreSight discovery information for the SCS + // 0x00000000 [31:0] DPIDR6 (0x00000000) + io_rw_32 dpidr6; + + _REG_(M33_DPIDR7_OFFSET) // M33_DPIDR7 + // Provides CoreSight discovery information for the SCS + // 0x00000000 [31:0] DPIDR7 (0x00000000) + io_rw_32 dpidr7; + + _REG_(M33_DPIDR0_OFFSET) // M33_DPIDR0 + // Provides CoreSight discovery information for the SCS + // 0x000000ff [7:0] PART_0 (0x21) See CoreSight Architecture Specification + io_ro_32 dpidr0; + + _REG_(M33_DPIDR1_OFFSET) // M33_DPIDR1 + // Provides CoreSight discovery information for the SCS + // 0x000000f0 [7:4] DES_0 (0xb) See CoreSight Architecture Specification + // 0x0000000f [3:0] PART_1 (0xd) See CoreSight Architecture Specification + io_ro_32 dpidr1; + + _REG_(M33_DPIDR2_OFFSET) // M33_DPIDR2 + // Provides CoreSight discovery information for the SCS + // 0x000000f0 [7:4] REVISION (0x0) See CoreSight Architecture Specification + // 0x00000008 [3] JEDEC (1) See CoreSight Architecture Specification + // 0x00000007 [2:0] DES_1 (0x3) See CoreSight Architecture Specification + io_ro_32 dpidr2; + + _REG_(M33_DPIDR3_OFFSET) // M33_DPIDR3 + // Provides CoreSight discovery information for the SCS + // 0x000000f0 [7:4] REVAND (0x0) See CoreSight Architecture Specification + // 0x0000000f [3:0] CMOD (0x0) See CoreSight Architecture Specification + io_ro_32 dpidr3; + + // (Description copied from array index 0 register M33_DCIDR0 applies similarly to other array indexes) + _REG_(M33_DCIDR0_OFFSET) // M33_DCIDR0 + // Provides CoreSight discovery information for the SCS + // 0x000000ff [7:0] PRMBL_0 (0x0d) See CoreSight Architecture Specification + io_ro_32 dcidr[4]; + + uint32_t _pad43[51201]; + + _REG_(M33_TRCPRGCTLR_OFFSET) // M33_TRCPRGCTLR + // Programming Control Register + // 0x00000001 [0] EN (0) Trace Unit Enable + io_rw_32 trcprgctlr; + + uint32_t _pad44; + + _REG_(M33_TRCSTATR_OFFSET) // M33_TRCSTATR + // The TRCSTATR indicates the ETM-Teal status + // 0x00000002 [1] PMSTABLE (0) Indicates whether the ETM-Teal registers are stable and... + // 0x00000001 [0] IDLE (0) Indicates that the trace unit is inactive + io_ro_32 trcstatr; + + _REG_(M33_TRCCONFIGR_OFFSET) // M33_TRCCONFIGR + // The TRCCONFIGR sets the basic tracing options for the trace unit + // 0x00001000 [12] RS (0) Return stack enable + // 0x00000800 [11] TS (0) Global timestamp tracing + // 0x000007e0 [10:5] COND (0x00) Conditional instruction tracing + // 0x00000010 [4] CCI (0) Cycle counting in instruction trace + // 0x00000008 [3] BB (0) Branch broadcast mode + io_rw_32 trcconfigr; + + uint32_t _pad45[3]; + + _REG_(M33_TRCEVENTCTL0R_OFFSET) // M33_TRCEVENTCTL0R + // The TRCEVENTCTL0R controls the tracing of events in the trace stream + // 0x00008000 [15] TYPE1 (0) Selects the resource type for event 1 + // 0x00000700 [10:8] SEL1 (0x0) Selects the resource number, based on the value of... + // 0x00000080 [7] TYPE0 (0) Selects the resource type for event 0 + // 0x00000007 [2:0] SEL0 (0x0) Selects the resource number, based on the value of... + io_rw_32 trceventctl0r; + + _REG_(M33_TRCEVENTCTL1R_OFFSET) // M33_TRCEVENTCTL1R + // The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R behave + // 0x00001000 [12] LPOVERRIDE (0) Low power state behavior override + // 0x00000800 [11] ATB (0) ATB enabled + // 0x00000002 [1] INSTEN1 (0) One bit per event, to enable generation of an event... + // 0x00000001 [0] INSTEN0 (0) One bit per event, to enable generation of an event... + io_rw_32 trceventctl1r; + + uint32_t _pad46; + + _REG_(M33_TRCSTALLCTLR_OFFSET) // M33_TRCSTALLCTLR + // The TRCSTALLCTLR enables ETM-Teal to stall the processor if the ETM-Teal FIFO goes over the... + // 0x00000400 [10] INSTPRIORITY (0) Reserved, RES0 + // 0x00000100 [8] ISTALL (0) Stall processor based on instruction trace buffer space + // 0x0000000c [3:2] LEVEL (0x0) Threshold at which stalling becomes active + io_rw_32 trcstallctlr; + + _REG_(M33_TRCTSCTLR_OFFSET) // M33_TRCTSCTLR + // The TRCTSCTLR controls the insertion of global timestamps into the trace stream + // 0x00000080 [7] TYPE0 (0) Selects the resource type for event 0 + // 0x00000003 [1:0] SEL0 (0x0) Selects the resource number, based on the value of... + io_rw_32 trctsctlr; + + _REG_(M33_TRCSYNCPR_OFFSET) // M33_TRCSYNCPR + // The TRCSYNCPR specifies the period of trace synchronization of the trace streams + // 0x0000001f [4:0] PERIOD (0x0a) Defines the number of bytes of trace between trace... + io_ro_32 trcsyncpr; + + _REG_(M33_TRCCCCTLR_OFFSET) // M33_TRCCCCTLR + // The TRCCCCTLR sets the threshold value for instruction trace cycle counting + // 0x00000fff [11:0] THRESHOLD (0x000) Instruction trace cycle count threshold + io_rw_32 trcccctlr; + + uint32_t _pad47[17]; + + _REG_(M33_TRCVICTLR_OFFSET) // M33_TRCVICTLR + // The TRCVICTLR controls instruction trace filtering + // 0x00080000 [19] EXLEVEL_S3 (0) In Secure state, each bit controls whether instruction... + // 0x00010000 [16] EXLEVEL_S0 (0) In Secure state, each bit controls whether instruction... + // 0x00000800 [11] TRCERR (0) Selects whether a system error exception must always be traced + // 0x00000400 [10] TRCRESET (0) Selects whether a reset exception must always be traced + // 0x00000200 [9] SSSTATUS (0) Indicates the current status of the start/stop logic + // 0x00000080 [7] TYPE0 (0) Selects the resource type for event 0 + // 0x00000003 [1:0] SEL0 (0x0) Selects the resource number, based on the value of... + io_rw_32 trcvictlr; + + uint32_t _pad48[47]; + + _REG_(M33_TRCCNTRLDVR0_OFFSET) // M33_TRCCNTRLDVR0 + // The TRCCNTRLDVR defines the reload value for the reduced function counter + // 0x0000ffff [15:0] VALUE (0x0000) Defines the reload value for the counter + io_rw_32 trccntrldvr0; + + uint32_t _pad49[15]; + + _REG_(M33_TRCIDR8_OFFSET) // M33_TRCIDR8 + // TRCIDR8 + // 0xffffffff [31:0] MAXSPEC (0x00000000) reads as `ImpDef + io_ro_32 trcidr8; + + _REG_(M33_TRCIDR9_OFFSET) // M33_TRCIDR9 + // TRCIDR9 + // 0xffffffff [31:0] NUMP0KEY (0x00000000) reads as `ImpDef + io_ro_32 trcidr9; + + _REG_(M33_TRCIDR10_OFFSET) // M33_TRCIDR10 + // TRCIDR10 + // 0xffffffff [31:0] NUMP1KEY (0x00000000) reads as `ImpDef + io_ro_32 trcidr10; + + _REG_(M33_TRCIDR11_OFFSET) // M33_TRCIDR11 + // TRCIDR11 + // 0xffffffff [31:0] NUMP1SPC (0x00000000) reads as `ImpDef + io_ro_32 trcidr11; + + _REG_(M33_TRCIDR12_OFFSET) // M33_TRCIDR12 + // TRCIDR12 + // 0xffffffff [31:0] NUMCONDKEY (0x00000001) reads as `ImpDef + io_ro_32 trcidr12; + + _REG_(M33_TRCIDR13_OFFSET) // M33_TRCIDR13 + // TRCIDR13 + // 0xffffffff [31:0] NUMCONDSPC (0x00000000) reads as `ImpDef + io_ro_32 trcidr13; + + uint32_t _pad50[10]; + + _REG_(M33_TRCIMSPEC_OFFSET) // M33_TRCIMSPEC + // The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any... + // 0x0000000f [3:0] SUPPORT (0x0) Reserved, RES0 + io_ro_32 trcimspec; + + uint32_t _pad51[7]; + + _REG_(M33_TRCIDR0_OFFSET) // M33_TRCIDR0 + // TRCIDR0 + // 0x20000000 [29] COMMOPT (1) reads as `ImpDef + // 0x1f000000 [28:24] TSSIZE (0x08) reads as `ImpDef + // 0x00020000 [17] TRCEXDATA (0) reads as `ImpDef + // 0x00018000 [16:15] QSUPP (0x0) reads as `ImpDef + // 0x00004000 [14] QFILT (0) reads as `ImpDef + // 0x00003000 [13:12] CONDTYPE (0x0) reads as `ImpDef + // 0x00000c00 [11:10] NUMEVENT (0x1) reads as `ImpDef + // 0x00000200 [9] RETSTACK (1) reads as `ImpDef + // 0x00000080 [7] TRCCCI (1) reads as `ImpDef + // 0x00000040 [6] TRCCOND (1) reads as `ImpDef + // 0x00000020 [5] TRCBB (1) reads as `ImpDef + // 0x00000018 [4:3] TRCDATA (0x0) reads as `ImpDef + // 0x00000006 [2:1] INSTP0 (0x0) reads as `ImpDef + // 0x00000001 [0] RES1 (1) Reserved, RES1 + io_ro_32 trcidr0; + + _REG_(M33_TRCIDR1_OFFSET) // M33_TRCIDR1 + // TRCIDR1 + // 0xff000000 [31:24] DESIGNER (0x41) reads as `ImpDef + // 0x0000f000 [15:12] RES1 (0xf) Reserved, RES1 + // 0x00000f00 [11:8] TRCARCHMAJ (0x4) reads as 0b0100 + // 0x000000f0 [7:4] TRCARCHMIN (0x2) reads as 0b0000 + // 0x0000000f [3:0] REVISION (0x1) reads as `ImpDef + io_ro_32 trcidr1; + + _REG_(M33_TRCIDR2_OFFSET) // M33_TRCIDR2 + // TRCIDR2 + // 0x1e000000 [28:25] CCSIZE (0x0) reads as `ImpDef + // 0x01f00000 [24:20] DVSIZE (0x00) reads as `ImpDef + // 0x000f8000 [19:15] DASIZE (0x00) reads as `ImpDef + // 0x00007c00 [14:10] VMIDSIZE (0x00) reads as `ImpDef + // 0x000003e0 [9:5] CIDSIZE (0x00) reads as `ImpDef + // 0x0000001f [4:0] IASIZE (0x04) reads as `ImpDef + io_ro_32 trcidr2; + + _REG_(M33_TRCIDR3_OFFSET) // M33_TRCIDR3 + // TRCIDR3 + // 0x80000000 [31] NOOVERFLOW (0) reads as `ImpDef + // 0x70000000 [30:28] NUMPROC (0x0) reads as `ImpDef + // 0x08000000 [27] SYSSTALL (1) reads as `ImpDef + // 0x04000000 [26] STALLCTL (1) reads as `ImpDef + // 0x02000000 [25] SYNCPR (1) reads as `ImpDef + // 0x01000000 [24] TRCERR (1) reads as `ImpDef + // 0x00f00000 [23:20] EXLEVEL_NS (0x0) reads as `ImpDef + // 0x000f0000 [19:16] EXLEVEL_S (0x9) reads as `ImpDef + // 0x00000fff [11:0] CCITMIN (0x004) reads as `ImpDef + io_ro_32 trcidr3; + + _REG_(M33_TRCIDR4_OFFSET) // M33_TRCIDR4 + // TRCIDR4 + // 0xf0000000 [31:28] NUMVMIDC (0x0) reads as `ImpDef + // 0x0f000000 [27:24] NUMCIDC (0x0) reads as `ImpDef + // 0x00f00000 [23:20] NUMSSCC (0x1) reads as `ImpDef + // 0x000f0000 [19:16] NUMRSPAIR (0x1) reads as `ImpDef + // 0x0000f000 [15:12] NUMPC (0x4) reads as `ImpDef + // 0x00000100 [8] SUPPDAC (0) reads as `ImpDef + // 0x000000f0 [7:4] NUMDVC (0x0) reads as `ImpDef + // 0x0000000f [3:0] NUMACPAIRS (0x0) reads as `ImpDef + io_ro_32 trcidr4; + + _REG_(M33_TRCIDR5_OFFSET) // M33_TRCIDR5 + // TRCIDR5 + // 0x80000000 [31] REDFUNCNTR (1) reads as `ImpDef + // 0x70000000 [30:28] NUMCNTR (0x1) reads as `ImpDef + // 0x0e000000 [27:25] NUMSEQSTATE (0x0) reads as `ImpDef + // 0x00800000 [23] LPOVERRIDE (1) reads as `ImpDef + // 0x00400000 [22] ATBTRIG (1) reads as `ImpDef + // 0x003f0000 [21:16] TRACEIDSIZE (0x07) reads as 0x07 + // 0x00000e00 [11:9] NUMEXTINSEL (0x0) reads as `ImpDef + // 0x000001ff [8:0] NUMEXTIN (0x004) reads as `ImpDef + io_ro_32 trcidr5; + + _REG_(M33_TRCIDR6_OFFSET) // M33_TRCIDR6 + // TRCIDR6 + // 0x00000000 [31:0] TRCIDR6 (0x00000000) + io_rw_32 trcidr6; + + _REG_(M33_TRCIDR7_OFFSET) // M33_TRCIDR7 + // TRCIDR7 + // 0x00000000 [31:0] TRCIDR7 (0x00000000) + io_rw_32 trcidr7; + + uint32_t _pad52[2]; + + // (Description copied from array index 0 register M33_TRCRSCTLR2 applies similarly to other array indexes) + _REG_(M33_TRCRSCTLR2_OFFSET) // M33_TRCRSCTLR2 + // The TRCRSCTLR controls the trace resources + // 0x00200000 [21] PAIRINV (0) Inverts the result of a combined pair of resources + // 0x00100000 [20] INV (0) Inverts the selected resources + // 0x00070000 [18:16] GROUP (0x0) Selects a group of resource + // 0x000000ff [7:0] SELECT (0x00) Selects one or more resources from the wanted group + io_rw_32 trcrsctlr[2]; + + uint32_t _pad53[36]; + + _REG_(M33_TRCSSCSR_OFFSET) // M33_TRCSSCSR + // Controls the corresponding single-shot comparator resource + // 0x80000000 [31] STATUS (0) Single-shot status bit + // 0x00000008 [3] PC (0) Reserved, RES1 + // 0x00000004 [2] DV (0) Reserved, RES0 + // 0x00000002 [1] DA (0) Reserved, RES0 + // 0x00000001 [0] INST (0) Reserved, RES0 + io_rw_32 trcsscsr; + + uint32_t _pad54[7]; + + _REG_(M33_TRCSSPCICR_OFFSET) // M33_TRCSSPCICR + // Selects the PE comparator inputs for Single-shot control + // 0x0000000f [3:0] PC (0x0) Selects one or more PE comparator inputs for Single-shot control + io_rw_32 trcsspcicr; + + uint32_t _pad55[19]; + + _REG_(M33_TRCPDCR_OFFSET) // M33_TRCPDCR + // Requests the system to provide power to the trace unit + // 0x00000008 [3] PU (0) Powerup request bit: + io_rw_32 trcpdcr; + + _REG_(M33_TRCPDSR_OFFSET) // M33_TRCPDSR + // Returns the following information about the trace unit: - OS Lock status + // 0x00000020 [5] OSLK (0) OS Lock status bit: + // 0x00000002 [1] STICKYPD (1) Sticky powerdown status bit + // 0x00000001 [0] POWER (1) Power status bit: + io_ro_32 trcpdsr; + + uint32_t _pad56[755]; + + _REG_(M33_TRCITATBIDR_OFFSET) // M33_TRCITATBIDR + // Trace Integration ATB Identification Register + // 0x0000007f [6:0] ID (0x00) Trace ID + io_rw_32 trcitatbidr; + + uint32_t _pad57[3]; + + _REG_(M33_TRCITIATBINR_OFFSET) // M33_TRCITIATBINR + // Trace Integration Instruction ATB In Register + // 0x00000002 [1] AFVALIDM (0) Integration Mode instruction AFVALIDM in + // 0x00000001 [0] ATREADYM (0) Integration Mode instruction ATREADYM in + io_rw_32 trcitiatbinr; + + uint32_t _pad58; + + _REG_(M33_TRCITIATBOUTR_OFFSET) // M33_TRCITIATBOUTR + // Trace Integration Instruction ATB Out Register + // 0x00000002 [1] AFREADY (0) Integration Mode instruction AFREADY out + // 0x00000001 [0] ATVALID (0) Integration Mode instruction ATVALID out + io_rw_32 trcitiatboutr; + + uint32_t _pad59[40]; + + _REG_(M33_TRCCLAIMSET_OFFSET) // M33_TRCCLAIMSET + // Claim Tag Set Register + // 0x00000008 [3] SET3 (1) When a write to one of these bits occurs, with the value: + // 0x00000004 [2] SET2 (1) When a write to one of these bits occurs, with the value: + // 0x00000002 [1] SET1 (1) When a write to one of these bits occurs, with the value: + // 0x00000001 [0] SET0 (1) When a write to one of these bits occurs, with the value: + io_rw_32 trcclaimset; + + _REG_(M33_TRCCLAIMCLR_OFFSET) // M33_TRCCLAIMCLR + // Claim Tag Clear Register + // 0x00000008 [3] CLR3 (0) When a write to one of these bits occurs, with the value: + // 0x00000004 [2] CLR2 (0) When a write to one of these bits occurs, with the value: + // 0x00000002 [1] CLR1 (0) When a write to one of these bits occurs, with the value: + // 0x00000001 [0] CLR0 (0) When a write to one of these bits occurs, with the value: + io_rw_32 trcclaimclr; + + uint32_t _pad60[4]; + + _REG_(M33_TRCAUTHSTATUS_OFFSET) // M33_TRCAUTHSTATUS + // Returns the level of tracing that the trace unit can support + // 0x000000c0 [7:6] SNID (0x0) Indicates whether the system enables the trace unit to... + // 0x00000030 [5:4] SID (0x0) Indicates whether the trace unit supports Secure invasive debug: + // 0x0000000c [3:2] NSNID (0x0) Indicates whether the system enables the trace unit to... + // 0x00000003 [1:0] NSID (0x0) Indicates whether the trace unit supports Non-secure... + io_ro_32 trcauthstatus; + + _REG_(M33_TRCDEVARCH_OFFSET) // M33_TRCDEVARCH + // TRCDEVARCH + // 0xffe00000 [31:21] ARCHITECT (0x23b) reads as 0b01000111011 + // 0x00100000 [20] PRESENT (1) reads as 0b1 + // 0x000f0000 [19:16] REVISION (0x2) reads as 0b0000 + // 0x0000ffff [15:0] ARCHID (0x4a13) reads as 0b0100101000010011 + io_ro_32 trcdevarch; + + uint32_t _pad61[2]; + + _REG_(M33_TRCDEVID_OFFSET) // M33_TRCDEVID + // TRCDEVID + // 0x00000000 [31:0] TRCDEVID (0x00000000) + io_rw_32 trcdevid; + + _REG_(M33_TRCDEVTYPE_OFFSET) // M33_TRCDEVTYPE + // TRCDEVTYPE + // 0x000000f0 [7:4] SUB (0x1) reads as 0b0001 + // 0x0000000f [3:0] MAJOR (0x3) reads as 0b0011 + io_ro_32 trcdevtype; + + _REG_(M33_TRCPIDR4_OFFSET) // M33_TRCPIDR4 + // TRCPIDR4 + // 0x000000f0 [7:4] SIZE (0x0) reads as `ImpDef + // 0x0000000f [3:0] DES_2 (0x4) reads as `ImpDef + io_ro_32 trcpidr4; + + _REG_(M33_TRCPIDR5_OFFSET) // M33_TRCPIDR5 + // TRCPIDR5 + // 0x00000000 [31:0] TRCPIDR5 (0x00000000) + io_rw_32 trcpidr5; + + _REG_(M33_TRCPIDR6_OFFSET) // M33_TRCPIDR6 + // TRCPIDR6 + // 0x00000000 [31:0] TRCPIDR6 (0x00000000) + io_rw_32 trcpidr6; + + _REG_(M33_TRCPIDR7_OFFSET) // M33_TRCPIDR7 + // TRCPIDR7 + // 0x00000000 [31:0] TRCPIDR7 (0x00000000) + io_rw_32 trcpidr7; + + _REG_(M33_TRCPIDR0_OFFSET) // M33_TRCPIDR0 + // TRCPIDR0 + // 0x000000ff [7:0] PART_0 (0x21) reads as `ImpDef + io_ro_32 trcpidr0; + + _REG_(M33_TRCPIDR1_OFFSET) // M33_TRCPIDR1 + // TRCPIDR1 + // 0x000000f0 [7:4] DES_0 (0xb) reads as `ImpDef + // 0x0000000f [3:0] PART_0 (0xd) reads as `ImpDef + io_ro_32 trcpidr1; + + _REG_(M33_TRCPIDR2_OFFSET) // M33_TRCPIDR2 + // TRCPIDR2 + // 0x000000f0 [7:4] REVISION (0x2) reads as `ImpDef + // 0x00000008 [3] JEDEC (1) reads as 0b1 + // 0x00000007 [2:0] DES_0 (0x3) reads as `ImpDef + io_ro_32 trcpidr2; + + _REG_(M33_TRCPIDR3_OFFSET) // M33_TRCPIDR3 + // TRCPIDR3 + // 0x000000f0 [7:4] REVAND (0x0) reads as `ImpDef + // 0x0000000f [3:0] CMOD (0x0) reads as `ImpDef + io_ro_32 trcpidr3; + + // (Description copied from array index 0 register M33_TRCCIDR0 applies similarly to other array indexes) + _REG_(M33_TRCCIDR0_OFFSET) // M33_TRCCIDR0 + // TRCCIDR0 + // 0x000000ff [7:0] PRMBL_0 (0x0d) reads as 0b00001101 + io_ro_32 trccidr[4]; + + _REG_(M33_CTICONTROL_OFFSET) // M33_CTICONTROL + // CTI Control Register + // 0x00000001 [0] GLBEN (0) Enables or disables the CTI + io_rw_32 cticontrol; + + uint32_t _pad62[3]; + + _REG_(M33_CTIINTACK_OFFSET) // M33_CTIINTACK + // CTI Interrupt Acknowledge Register + // 0x000000ff [7:0] INTACK (0x00) Acknowledges the corresponding ctitrigout output + io_rw_32 ctiintack; + + _REG_(M33_CTIAPPSET_OFFSET) // M33_CTIAPPSET + // CTI Application Trigger Set Register + // 0x0000000f [3:0] APPSET (0x0) Setting a bit HIGH generates a channel event for the... + io_rw_32 ctiappset; + + _REG_(M33_CTIAPPCLEAR_OFFSET) // M33_CTIAPPCLEAR + // CTI Application Trigger Clear Register + // 0x0000000f [3:0] APPCLEAR (0x0) Sets the corresponding bits in the CTIAPPSET to 0 + io_rw_32 ctiappclear; + + _REG_(M33_CTIAPPPULSE_OFFSET) // M33_CTIAPPPULSE + // CTI Application Pulse Register + // 0x0000000f [3:0] APPULSE (0x0) Setting a bit HIGH generates a channel event pulse for... + io_rw_32 ctiapppulse; + + // (Description copied from array index 0 register M33_CTIINEN0 applies similarly to other array indexes) + _REG_(M33_CTIINEN0_OFFSET) // M33_CTIINEN0 + // CTI Trigger to Channel Enable Registers + // 0x0000000f [3:0] TRIGINEN (0x0) Enables a cross trigger event to the corresponding... + io_rw_32 ctiinen[8]; + + uint32_t _pad63[24]; + + // (Description copied from array index 0 register M33_CTIOUTEN0 applies similarly to other array indexes) + _REG_(M33_CTIOUTEN0_OFFSET) // M33_CTIOUTEN0 + // CTI Trigger to Channel Enable Registers + // 0x0000000f [3:0] TRIGOUTEN (0x0) Enables a cross trigger event to ctitrigout when the... + io_rw_32 ctiouten[8]; + + uint32_t _pad64[28]; + + _REG_(M33_CTITRIGINSTATUS_OFFSET) // M33_CTITRIGINSTATUS + // CTI Trigger to Channel Enable Registers + // 0x000000ff [7:0] TRIGINSTATUS (0x00) Shows the status of the ctitrigin inputs + io_ro_32 ctitriginstatus; + + _REG_(M33_CTITRIGOUTSTATUS_OFFSET) // M33_CTITRIGOUTSTATUS + // CTI Trigger In Status Register + // 0x000000ff [7:0] TRIGOUTSTATUS (0x00) Shows the status of the ctitrigout outputs + io_ro_32 ctitrigoutstatus; + + _REG_(M33_CTICHINSTATUS_OFFSET) // M33_CTICHINSTATUS + // CTI Channel In Status Register + // 0x0000000f [3:0] CTICHOUTSTATUS (0x0) Shows the status of the ctichout outputs + io_ro_32 ctichinstatus; + + uint32_t _pad65; + + _REG_(M33_CTIGATE_OFFSET) // M33_CTIGATE + // Enable CTI Channel Gate register + // 0x00000008 [3] CTIGATEEN3 (1) Enable ctichout3 + // 0x00000004 [2] CTIGATEEN2 (1) Enable ctichout2 + // 0x00000002 [1] CTIGATEEN1 (1) Enable ctichout1 + // 0x00000001 [0] CTIGATEEN0 (1) Enable ctichout0 + io_rw_32 ctigate; + + _REG_(M33_ASICCTL_OFFSET) // M33_ASICCTL + // External Multiplexer Control register + // 0x00000000 [31:0] ASICCTL (0x00000000) + io_rw_32 asicctl; + + uint32_t _pad66[871]; + + _REG_(M33_ITCHOUT_OFFSET) // M33_ITCHOUT + // Integration Test Channel Output register + // 0x0000000f [3:0] CTCHOUT (0x0) Sets the value of the ctichout outputs + io_rw_32 itchout; + + _REG_(M33_ITTRIGOUT_OFFSET) // M33_ITTRIGOUT + // Integration Test Trigger Output register + // 0x000000ff [7:0] CTTRIGOUT (0x00) Sets the value of the ctitrigout outputs + io_rw_32 ittrigout; + + uint32_t _pad67[2]; + + _REG_(M33_ITCHIN_OFFSET) // M33_ITCHIN + // Integration Test Channel Input register + // 0x0000000f [3:0] CTCHIN (0x0) Reads the value of the ctichin inputs + io_ro_32 itchin; + + uint32_t _pad68[2]; + + _REG_(M33_ITCTRL_OFFSET) // M33_ITCTRL + // Integration Mode Control register + // 0x00000001 [0] IME (0) Integration Mode Enable + io_rw_32 itctrl; + + uint32_t _pad69[46]; + + _REG_(M33_DEVARCH_OFFSET) // M33_DEVARCH + // Device Architecture register + // 0xffe00000 [31:21] ARCHITECT (0x23b) Indicates the component architect + // 0x00100000 [20] PRESENT (1) Indicates whether the DEVARCH register is present + // 0x000f0000 [19:16] REVISION (0x0) Indicates the architecture revision + // 0x0000ffff [15:0] ARCHID (0x1a14) Indicates the component + io_ro_32 devarch; + + uint32_t _pad70[2]; + + _REG_(M33_DEVID_OFFSET) // M33_DEVID + // Device Configuration register + // 0x000f0000 [19:16] NUMCH (0x4) Number of ECT channels available + // 0x0000ff00 [15:8] NUMTRIG (0x08) Number of ECT triggers available + // 0x0000001f [4:0] EXTMUXNUM (0x00) Indicates the number of multiplexers available on... + io_ro_32 devid; + + _REG_(M33_DEVTYPE_OFFSET) // M33_DEVTYPE + // Device Type Identifier register + // 0x000000f0 [7:4] SUB (0x1) Sub-classification of the type of the debug component as... + // 0x0000000f [3:0] MAJOR (0x4) Major classification of the type of the debug component... + io_ro_32 devtype; + + _REG_(M33_PIDR4_OFFSET) // M33_PIDR4 + // CoreSight Peripheral ID4 + // 0x000000f0 [7:4] SIZE (0x0) Always 0b0000 + // 0x0000000f [3:0] DES_2 (0x4) Together, PIDR1 + io_ro_32 pidr4; + + _REG_(M33_PIDR5_OFFSET) // M33_PIDR5 + // CoreSight Peripheral ID5 + // 0x00000000 [31:0] PIDR5 (0x00000000) + io_rw_32 pidr5; + + _REG_(M33_PIDR6_OFFSET) // M33_PIDR6 + // CoreSight Peripheral ID6 + // 0x00000000 [31:0] PIDR6 (0x00000000) + io_rw_32 pidr6; + + _REG_(M33_PIDR7_OFFSET) // M33_PIDR7 + // CoreSight Peripheral ID7 + // 0x00000000 [31:0] PIDR7 (0x00000000) + io_rw_32 pidr7; + + _REG_(M33_PIDR0_OFFSET) // M33_PIDR0 + // CoreSight Peripheral ID0 + // 0x000000ff [7:0] PART_0 (0x21) Bits[7:0] of the 12-bit part number of the component + io_ro_32 pidr0; + + _REG_(M33_PIDR1_OFFSET) // M33_PIDR1 + // CoreSight Peripheral ID1 + // 0x000000f0 [7:4] DES_0 (0xb) Together, PIDR1 + // 0x0000000f [3:0] PART_1 (0xd) Bits[11:8] of the 12-bit part number of the component + io_ro_32 pidr1; + + _REG_(M33_PIDR2_OFFSET) // M33_PIDR2 + // CoreSight Peripheral ID2 + // 0x000000f0 [7:4] REVISION (0x0) This device is at r1p0 + // 0x00000008 [3] JEDEC (1) Always 1 + // 0x00000007 [2:0] DES_1 (0x3) Together, PIDR1 + io_ro_32 pidr2; + + _REG_(M33_PIDR3_OFFSET) // M33_PIDR3 + // CoreSight Peripheral ID3 + // 0x000000f0 [7:4] REVAND (0x0) Indicates minor errata fixes specific to the revision of... + // 0x0000000f [3:0] CMOD (0x0) Customer Modified + io_ro_32 pidr3; + + // (Description copied from array index 0 register M33_CIDR0 applies similarly to other array indexes) + _REG_(M33_CIDR0_OFFSET) // M33_CIDR0 + // CoreSight Component ID0 + // 0x000000ff [7:0] PRMBL_0 (0x0d) Preamble[0] + io_ro_32 cidr[4]; +} m33_hw_t; + +#define m33_hw ((m33_hw_t *)PPB_BASE) +#define m33_ns_hw ((m33_hw_t *)PPB_NONSEC_BASE) +static_assert(sizeof (m33_hw_t) == 0x43000, ""); + +#endif // _HARDWARE_STRUCTS_M33_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/m33_eppb.h b/lib/pico-sdk/rp2350/hardware/structs/m33_eppb.h new file mode 100644 index 00000000..3b271e6f --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/m33_eppb.h @@ -0,0 +1,50 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_M33_EPPB_H +#define _HARDWARE_STRUCTS_M33_EPPB_H + +/** + * \file rp2350/m33_eppb.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/m33_eppb.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33_eppb +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m33_eppb.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV +#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" +#endif + + +typedef struct { + // (Description copied from array index 0 register M33_EPPB_NMI_MASK0 applies similarly to other array indexes) + _REG_(M33_EPPB_NMI_MASK0_OFFSET) // M33_EPPB_NMI_MASK0 + // NMI mask for IRQs 0 through 31 + // 0xffffffff [31:0] NMI_MASK0 (0x00000000) + io_rw_32 nmi_mask[2]; + + _REG_(M33_EPPB_SLEEPCTRL_OFFSET) // M33_EPPB_SLEEPCTRL + // Nonstandard sleep control register + // 0x00000004 [2] WICENACK (0) Status signal from the processor's interrupt controller + // 0x00000002 [1] WICENREQ (1) Request that the next processor deep sleep is a WIC sleep + // 0x00000001 [0] LIGHT_SLEEP (0) By default, any processor sleep will deassert the... + io_rw_32 sleepctrl; +} m33_eppb_hw_t; + +#define eppb_hw ((m33_eppb_hw_t *)EPPB_BASE) +static_assert(sizeof (m33_eppb_hw_t) == 0x000c, ""); + +#endif // _HARDWARE_STRUCTS_M33_EPPB_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/mpu.h b/lib/pico-sdk/rp2350/hardware/structs/mpu.h new file mode 100644 index 00000000..e3bf920d --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/mpu.h @@ -0,0 +1,126 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_MPU_H +#define _HARDWARE_STRUCTS_MPU_H + +/** + * \file rp2350/mpu.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/m33.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m33.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV +#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" +#endif + +typedef struct { + _REG_(M33_MPU_TYPE_OFFSET) // M33_MPU_TYPE + // The MPU Type Register indicates how many regions the MPU `FTSSS supports + // 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU + // 0x00000001 [0] SEPARATE (0) Indicates support for separate instructions and data... + io_ro_32 type; + + _REG_(M33_MPU_CTRL_OFFSET) // M33_MPU_CTRL + // Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled... + // 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled for... + // 0x00000002 [1] HFNMIENA (0) Controls whether handlers executing with priority less... + // 0x00000001 [0] ENABLE (0) Enables the MPU + io_rw_32 ctrl; + + _REG_(M33_MPU_RNR_OFFSET) // M33_MPU_RNR + // Selects the region currently accessed by MPU_RBAR and MPU_RLAR + // 0x00000007 [2:0] REGION (0x0) Indicates the memory region accessed by MPU_RBAR and MPU_RLAR + io_rw_32 rnr; + + _REG_(M33_MPU_RBAR_OFFSET) // M33_MPU_RBAR + // Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS + // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... + // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory + // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region + // 0x00000001 [0] XN (0) Defines whether code can be executed from this region + io_rw_32 rbar; + + _REG_(M33_MPU_RLAR_OFFSET) // M33_MPU_RLAR + // Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS + // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... + // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... + // 0x00000001 [0] EN (0) Region enable + io_rw_32 rlar; + + _REG_(M33_MPU_RBAR_A1_OFFSET) // M33_MPU_RBAR_A1 + // Provides indirect read and write access to the base address of the MPU region selected by... + // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... + // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory + // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region + // 0x00000001 [0] XN (0) Defines whether code can be executed from this region + io_rw_32 rbar_a1; + + _REG_(M33_MPU_RLAR_A1_OFFSET) // M33_MPU_RLAR_A1 + // Provides indirect read and write access to the limit address of the currently selected MPU... + // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... + // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... + // 0x00000001 [0] EN (0) Region enable + io_rw_32 rlar_a1; + + _REG_(M33_MPU_RBAR_A2_OFFSET) // M33_MPU_RBAR_A2 + // Provides indirect read and write access to the base address of the MPU region selected by... + // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... + // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory + // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region + // 0x00000001 [0] XN (0) Defines whether code can be executed from this region + io_rw_32 rbar_a2; + + _REG_(M33_MPU_RLAR_A2_OFFSET) // M33_MPU_RLAR_A2 + // Provides indirect read and write access to the limit address of the currently selected MPU... + // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... + // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... + // 0x00000001 [0] EN (0) Region enable + io_rw_32 rlar_a2; + + _REG_(M33_MPU_RBAR_A3_OFFSET) // M33_MPU_RBAR_A3 + // Provides indirect read and write access to the base address of the MPU region selected by... + // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... + // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory + // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region + // 0x00000001 [0] XN (0) Defines whether code can be executed from this region + io_rw_32 rbar_a3; + + _REG_(M33_MPU_RLAR_A3_OFFSET) // M33_MPU_RLAR_A3 + // Provides indirect read and write access to the limit address of the currently selected MPU... + // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... + // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... + // 0x00000001 [0] EN (0) Region enable + io_rw_32 rlar_a3; + + uint32_t _pad0; + + // (Description copied from array index 0 register M33_MPU_MAIR0 applies similarly to other array indexes) + _REG_(M33_MPU_MAIR0_OFFSET) // M33_MPU_MAIR0 + // Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values + // 0xff000000 [31:24] ATTR3 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 3 + // 0x00ff0000 [23:16] ATTR2 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 2 + // 0x0000ff00 [15:8] ATTR1 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 1 + // 0x000000ff [7:0] ATTR0 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 0 + io_rw_32 mair[2]; +} mpu_hw_t; + +#define mpu_hw ((mpu_hw_t *)(PPB_BASE + M33_MPU_TYPE_OFFSET)) +#define mpu_ns_hw ((mpu_hw_t *)(PPB_NONSEC_BASE + M33_MPU_TYPE_OFFSET)) +static_assert(sizeof (mpu_hw_t) == 0x0038, ""); + +#endif // _HARDWARE_STRUCTS_MPU_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/nvic.h b/lib/pico-sdk/rp2350/hardware/structs/nvic.h new file mode 100644 index 00000000..c0c7b76b --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/nvic.h @@ -0,0 +1,94 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_NVIC_H +#define _HARDWARE_STRUCTS_NVIC_H + +/** + * \file rp2350/nvic.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/m33.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m33.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV +#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" +#endif + +typedef struct { + // (Description copied from array index 0 register M33_NVIC_ISER0 applies similarly to other array indexes) + _REG_(M33_NVIC_ISER0_OFFSET) // M33_NVIC_ISER0 + // Enables or reads the enabled state of each group of 32 interrupts + // 0xffffffff [31:0] SETENA (0x00000000) For SETENA[m] in NVIC_ISER*n, indicates whether... + io_rw_32 iser[2]; + + uint32_t _pad0[30]; + + // (Description copied from array index 0 register M33_NVIC_ICER0 applies similarly to other array indexes) + _REG_(M33_NVIC_ICER0_OFFSET) // M33_NVIC_ICER0 + // Clears or reads the enabled state of each group of 32 interrupts + // 0xffffffff [31:0] CLRENA (0x00000000) For CLRENA[m] in NVIC_ICER*n, indicates whether... + io_rw_32 icer[2]; + + uint32_t _pad1[30]; + + // (Description copied from array index 0 register M33_NVIC_ISPR0 applies similarly to other array indexes) + _REG_(M33_NVIC_ISPR0_OFFSET) // M33_NVIC_ISPR0 + // Enables or reads the pending state of each group of 32 interrupts + // 0xffffffff [31:0] SETPEND (0x00000000) For SETPEND[m] in NVIC_ISPR*n, indicates whether... + io_rw_32 ispr[2]; + + uint32_t _pad2[30]; + + // (Description copied from array index 0 register M33_NVIC_ICPR0 applies similarly to other array indexes) + _REG_(M33_NVIC_ICPR0_OFFSET) // M33_NVIC_ICPR0 + // Clears or reads the pending state of each group of 32 interrupts + // 0xffffffff [31:0] CLRPEND (0x00000000) For CLRPEND[m] in NVIC_ICPR*n, indicates whether... + io_rw_32 icpr[2]; + + uint32_t _pad3[30]; + + // (Description copied from array index 0 register M33_NVIC_IABR0 applies similarly to other array indexes) + _REG_(M33_NVIC_IABR0_OFFSET) // M33_NVIC_IABR0 + // For each group of 32 interrupts, shows the active state of each interrupt + // 0xffffffff [31:0] ACTIVE (0x00000000) For ACTIVE[m] in NVIC_IABR*n, indicates the active state... + io_rw_32 iabr[2]; + + uint32_t _pad4[30]; + + // (Description copied from array index 0 register M33_NVIC_ITNS0 applies similarly to other array indexes) + _REG_(M33_NVIC_ITNS0_OFFSET) // M33_NVIC_ITNS0 + // For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state + // 0xffffffff [31:0] ITNS (0x00000000) For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security... + io_rw_32 itns[2]; + + uint32_t _pad5[30]; + + // (Description copied from array index 0 register M33_NVIC_IPR0 applies similarly to other array indexes) + _REG_(M33_NVIC_IPR0_OFFSET) // M33_NVIC_IPR0 + // Sets or reads interrupt priorities + // 0xf0000000 [31:28] PRI_N3 (0x0) For register NVIC_IPRn, the priority of interrupt number... + // 0x00f00000 [23:20] PRI_N2 (0x0) For register NVIC_IPRn, the priority of interrupt number... + // 0x0000f000 [15:12] PRI_N1 (0x0) For register NVIC_IPRn, the priority of interrupt number... + // 0x000000f0 [7:4] PRI_N0 (0x0) For register NVIC_IPRn, the priority of interrupt number... + io_rw_32 ipr[16]; +} nvic_hw_t; + +#define nvic_hw ((nvic_hw_t *)(PPB_BASE + M33_NVIC_ISER0_OFFSET)) +#define nvic_ns_hw ((nvic_hw_t *)(PPB_NONSEC_BASE + M33_NVIC_ISER0_OFFSET)) +static_assert(sizeof (nvic_hw_t) == 0x0340, ""); + +#endif // _HARDWARE_STRUCTS_NVIC_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/otp.h b/lib/pico-sdk/rp2350/hardware/structs/otp.h new file mode 100644 index 00000000..803643b8 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/otp.h @@ -0,0 +1,192 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_OTP_H +#define _HARDWARE_STRUCTS_OTP_H + +/** + * \file rp2350/otp.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/otp.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_otp +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/otp.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + // (Description copied from array index 0 register OTP_SW_LOCK0 applies similarly to other array indexes) + _REG_(OTP_SW_LOCK0_OFFSET) // OTP_SW_LOCK0 + // Software lock register for page 0. + // 0x0000000c [3:2] NSEC (-) Non-secure lock status + // 0x00000003 [1:0] SEC (-) Secure lock status + io_rw_32 sw_lock[64]; + + _REG_(OTP_SBPI_INSTR_OFFSET) // OTP_SBPI_INSTR + // Dispatch instructions to the SBPI interface, used for programming the OTP fuses + // 0x40000000 [30] EXEC (0) Execute instruction + // 0x20000000 [29] IS_WR (0) Payload type is write + // 0x10000000 [28] HAS_PAYLOAD (0) Instruction has payload (data to be written or to be read) + // 0x0f000000 [27:24] PAYLOAD_SIZE_M1 (0x0) Instruction payload size in bytes minus 1 + // 0x00ff0000 [23:16] TARGET (0x00) Instruction target, it can be PMC (0x3a) or DAP (0x02) + // 0x0000ff00 [15:8] CMD (0x00) + // 0x000000ff [7:0] SHORT_WDATA (0x00) wdata to be used only when payload_size_m1=0 + io_rw_32 sbpi_instr; + + // (Description copied from array index 0 register OTP_SBPI_WDATA_0 applies similarly to other array indexes) + _REG_(OTP_SBPI_WDATA_0_OFFSET) // OTP_SBPI_WDATA_0 + // SBPI write payload bytes 3 + // 0xffffffff [31:0] SBPI_WDATA_0 (0x00000000) + io_rw_32 sbpi_wdata[4]; + + // (Description copied from array index 0 register OTP_SBPI_RDATA_0 applies similarly to other array indexes) + _REG_(OTP_SBPI_RDATA_0_OFFSET) // OTP_SBPI_RDATA_0 + // Read payload bytes 3 + // 0xffffffff [31:0] SBPI_RDATA_0 (0x00000000) + io_ro_32 sbpi_rdata[4]; + + _REG_(OTP_SBPI_STATUS_OFFSET) // OTP_SBPI_STATUS + // 0x00ff0000 [23:16] MISO (-) SBPI MISO (master in - slave out): response from SBPI + // 0x00001000 [12] FLAG (-) SBPI flag + // 0x00000100 [8] INSTR_MISS (0) Last instruction missed (dropped), as the previous has... + // 0x00000010 [4] INSTR_DONE (0) Last instruction done + // 0x00000001 [0] RDATA_VLD (0) Read command has returned data + io_rw_32 sbpi_status; + + _REG_(OTP_USR_OFFSET) // OTP_USR + // Controls for APB data read interface (USER interface) + // 0x00000010 [4] PD (0) Power-down; 1 disables current reference + // 0x00000001 [0] DCTRL (1) 1 enables USER interface; 0 disables USER interface... + io_rw_32 usr; + + _REG_(OTP_DBG_OFFSET) // OTP_DBG + // Debug for OTP power-on state machine + // 0x00001000 [12] CUSTOMER_RMA_FLAG (-) The chip is in RMA mode + // 0x000000f0 [7:4] PSM_STATE (-) Monitor the PSM FSM's state + // 0x00000008 [3] ROSC_UP (-) Ring oscillator is up and running + // 0x00000004 [2] ROSC_UP_SEEN (0) Ring oscillator was seen up and running + // 0x00000002 [1] BOOT_DONE (-) PSM boot done status flag + // 0x00000001 [0] PSM_DONE (-) PSM done status flag + io_rw_32 dbg; + + uint32_t _pad0; + + _REG_(OTP_BIST_OFFSET) // OTP_BIST + // During BIST, count address locations that have at least one leaky bit + // 0x40000000 [30] CNT_FAIL (-) Flag if the count of address locations with at least one... + // 0x20000000 [29] CNT_CLR (0) Clear counter before use + // 0x10000000 [28] CNT_ENA (0) Enable the counter before the BIST function is initiated + // 0x0fff0000 [27:16] CNT_MAX (0xfff) The cnt_fail flag will be set if the number of leaky... + // 0x00001fff [12:0] CNT (-) Number of locations that have at least one leaky bit + io_rw_32 bist; + + // (Description copied from array index 0 register OTP_CRT_KEY_W0 applies similarly to other array indexes) + _REG_(OTP_CRT_KEY_W0_OFFSET) // OTP_CRT_KEY_W0 + // Word 0 (bits 31 + // 0xffffffff [31:0] CRT_KEY_W0 (0x00000000) + io_wo_32 crt_key_w[4]; + + _REG_(OTP_CRITICAL_OFFSET) // OTP_CRITICAL + // Quickly check values of critical flags read during boot up + // 0x00020000 [17] RISCV_DISABLE (0) + // 0x00010000 [16] ARM_DISABLE (0) + // 0x00000060 [6:5] GLITCH_DETECTOR_SENS (0x0) + // 0x00000010 [4] GLITCH_DETECTOR_ENABLE (0) + // 0x00000008 [3] DEFAULT_ARCHSEL (0) + // 0x00000004 [2] DEBUG_DISABLE (0) + // 0x00000002 [1] SECURE_DEBUG_DISABLE (0) + // 0x00000001 [0] SECURE_BOOT_ENABLE (0) + io_ro_32 critical; + + _REG_(OTP_KEY_VALID_OFFSET) // OTP_KEY_VALID + // Which keys were valid (enrolled) at boot time + // 0x000000ff [7:0] KEY_VALID (0x00) + io_ro_32 key_valid; + + _REG_(OTP_DEBUGEN_OFFSET) // OTP_DEBUGEN + // Enable a debug feature that has been disabled. Debug features are disabled if one of the relevant critical boot flags is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug key is marked valid in OTP, and the matching key value has not been supplied over SWD. + // 0x00000100 [8] MISC (0) Enable other debug components + // 0x00000008 [3] PROC1_SECURE (0) Permit core 1's Mem-AP to generate Secure accesses,... + // 0x00000004 [2] PROC1 (0) Enable core 1's Mem-AP if it is currently disabled + // 0x00000002 [1] PROC0_SECURE (0) Permit core 0's Mem-AP to generate Secure accesses,... + // 0x00000001 [0] PROC0 (0) Enable core 0's Mem-AP if it is currently disabled + io_rw_32 debugen; + + _REG_(OTP_DEBUGEN_LOCK_OFFSET) // OTP_DEBUGEN_LOCK + // Write 1s to lock corresponding bits in DEBUGEN + // 0x00000100 [8] MISC (0) Write 1 to lock the MISC bit of DEBUGEN + // 0x00000008 [3] PROC1_SECURE (0) Write 1 to lock the PROC1_SECURE bit of DEBUGEN + // 0x00000004 [2] PROC1 (0) Write 1 to lock the PROC1 bit of DEBUGEN + // 0x00000002 [1] PROC0_SECURE (0) Write 1 to lock the PROC0_SECURE bit of DEBUGEN + // 0x00000001 [0] PROC0 (0) Write 1 to lock the PROC0 bit of DEBUGEN + io_rw_32 debugen_lock; + + _REG_(OTP_ARCHSEL_OFFSET) // OTP_ARCHSEL + // Architecture select (Arm/RISC-V), applied on next processor reset. The default and allowable values of this register are constrained by the critical boot flags. + // 0x00000002 [1] CORE1 (0) Select architecture for core 1 + // 0x00000001 [0] CORE0 (0) Select architecture for core 0 + io_rw_32 archsel; + + _REG_(OTP_ARCHSEL_STATUS_OFFSET) // OTP_ARCHSEL_STATUS + // Get the current architecture select state of each core + // 0x00000002 [1] CORE1 (0) Current architecture for core 0 + // 0x00000001 [0] CORE0 (0) Current architecture for core 0 + io_ro_32 archsel_status; + + _REG_(OTP_BOOTDIS_OFFSET) // OTP_BOOTDIS + // Tell the bootrom to ignore scratch register boot vectors (both power manager and watchdog) on the next power up. + // 0x00000002 [1] NEXT (0) This flag always ORs writes into its current contents + // 0x00000001 [0] NOW (0) When the core is powered down, the current value of... + io_rw_32 bootdis; + + _REG_(OTP_INTR_OFFSET) // OTP_INTR + // Raw Interrupts + // 0x00000010 [4] APB_RD_NSEC_FAIL (0) + // 0x00000008 [3] APB_RD_SEC_FAIL (0) + // 0x00000004 [2] APB_DCTRL_FAIL (0) + // 0x00000002 [1] SBPI_WR_FAIL (0) + // 0x00000001 [0] SBPI_FLAG_N (0) + io_rw_32 intr; + + _REG_(OTP_INTE_OFFSET) // OTP_INTE + // Interrupt Enable + // 0x00000010 [4] APB_RD_NSEC_FAIL (0) + // 0x00000008 [3] APB_RD_SEC_FAIL (0) + // 0x00000004 [2] APB_DCTRL_FAIL (0) + // 0x00000002 [1] SBPI_WR_FAIL (0) + // 0x00000001 [0] SBPI_FLAG_N (0) + io_rw_32 inte; + + _REG_(OTP_INTF_OFFSET) // OTP_INTF + // Interrupt Force + // 0x00000010 [4] APB_RD_NSEC_FAIL (0) + // 0x00000008 [3] APB_RD_SEC_FAIL (0) + // 0x00000004 [2] APB_DCTRL_FAIL (0) + // 0x00000002 [1] SBPI_WR_FAIL (0) + // 0x00000001 [0] SBPI_FLAG_N (0) + io_rw_32 intf; + + _REG_(OTP_INTS_OFFSET) // OTP_INTS + // Interrupt status after masking & forcing + // 0x00000010 [4] APB_RD_NSEC_FAIL (0) + // 0x00000008 [3] APB_RD_SEC_FAIL (0) + // 0x00000004 [2] APB_DCTRL_FAIL (0) + // 0x00000002 [1] SBPI_WR_FAIL (0) + // 0x00000001 [0] SBPI_FLAG_N (0) + io_ro_32 ints; +} otp_hw_t; + +#define otp_hw ((otp_hw_t *)OTP_BASE) +static_assert(sizeof (otp_hw_t) == 0x0174, ""); + +#endif // _HARDWARE_STRUCTS_OTP_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/pads_bank0.h b/lib/pico-sdk/rp2350/hardware/structs/pads_bank0.h new file mode 100644 index 00000000..bf0f4a53 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/pads_bank0.h @@ -0,0 +1,49 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_PADS_BANK0_H +#define _HARDWARE_STRUCTS_PADS_BANK0_H + +/** + * \file rp2350/pads_bank0.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/pads_bank0.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_pads_bank0 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pads_bank0.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(PADS_BANK0_VOLTAGE_SELECT_OFFSET) // PADS_BANK0_VOLTAGE_SELECT + // Voltage select + // 0x00000001 [0] VOLTAGE_SELECT (0) + io_rw_32 voltage_select; + + // (Description copied from array index 0 register PADS_BANK0_GPIO0 applies similarly to other array indexes) + _REG_(PADS_BANK0_GPIO0_OFFSET) // PADS_BANK0_GPIO0 + // 0x00000100 [8] ISO (1) Pad isolation control + // 0x00000080 [7] OD (0) Output disable + // 0x00000040 [6] IE (0) Input enable + // 0x00000030 [5:4] DRIVE (0x1) Drive strength + // 0x00000008 [3] PUE (0) Pull up enable + // 0x00000004 [2] PDE (1) Pull down enable + // 0x00000002 [1] SCHMITT (1) Enable schmitt trigger + // 0x00000001 [0] SLEWFAST (0) Slew rate control + io_rw_32 io[48]; +} pads_bank0_hw_t; + +#define pads_bank0_hw ((pads_bank0_hw_t *)PADS_BANK0_BASE) +static_assert(sizeof (pads_bank0_hw_t) == 0x00c4, ""); + +#endif // _HARDWARE_STRUCTS_PADS_BANK0_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/pads_qspi.h b/lib/pico-sdk/rp2350/hardware/structs/pads_qspi.h new file mode 100644 index 00000000..e6b0f681 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/pads_qspi.h @@ -0,0 +1,49 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_PADS_QSPI_H +#define _HARDWARE_STRUCTS_PADS_QSPI_H + +/** + * \file rp2350/pads_qspi.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/pads_qspi.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_pads_qspi +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pads_qspi.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(PADS_QSPI_VOLTAGE_SELECT_OFFSET) // PADS_QSPI_VOLTAGE_SELECT + // Voltage select + // 0x00000001 [0] VOLTAGE_SELECT (0) + io_rw_32 voltage_select; + + // (Description copied from array index 0 register PADS_QSPI_GPIO_QSPI_SCLK applies similarly to other array indexes) + _REG_(PADS_QSPI_GPIO_QSPI_SCLK_OFFSET) // PADS_QSPI_GPIO_QSPI_SCLK + // 0x00000100 [8] ISO (1) Pad isolation control + // 0x00000080 [7] OD (0) Output disable + // 0x00000040 [6] IE (1) Input enable + // 0x00000030 [5:4] DRIVE (0x1) Drive strength + // 0x00000008 [3] PUE (0) Pull up enable + // 0x00000004 [2] PDE (1) Pull down enable + // 0x00000002 [1] SCHMITT (1) Enable schmitt trigger + // 0x00000001 [0] SLEWFAST (0) Slew rate control + io_rw_32 io[6]; +} pads_qspi_hw_t; + +#define pads_qspi_hw ((pads_qspi_hw_t *)PADS_QSPI_BASE) +static_assert(sizeof (pads_qspi_hw_t) == 0x001c, ""); + +#endif // _HARDWARE_STRUCTS_PADS_QSPI_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/padsbank0.h b/lib/pico-sdk/rp2350/hardware/structs/padsbank0.h new file mode 100644 index 00000000..cb14e792 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/padsbank0.h @@ -0,0 +1,9 @@ +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// Support old header for compatibility (and if included, support old variable name) +#include "hardware/structs/pads_bank0.h" +#define padsbank0_hw pads_bank0_hw
\ No newline at end of file diff --git a/lib/pico-sdk/rp2350/hardware/structs/pio.h b/lib/pico-sdk/rp2350/hardware/structs/pio.h new file mode 100644 index 00000000..68e5bac0 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/pio.h @@ -0,0 +1,380 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_PIO_H +#define _HARDWARE_STRUCTS_PIO_H + +/** + * \file rp2350/pio.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/pio.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_pio +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pio.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(PIO_SM0_CLKDIV_OFFSET) // PIO_SM0_CLKDIV + // Clock divisor register for state machine 0 + + // 0xffff0000 [31:16] INT (0x0001) Effective frequency is sysclk/(int + frac/256) + // 0x0000ff00 [15:8] FRAC (0x00) Fractional part of clock divisor + io_rw_32 clkdiv; + + _REG_(PIO_SM0_EXECCTRL_OFFSET) // PIO_SM0_EXECCTRL + // Execution/behavioural settings for state machine 0 + // 0x80000000 [31] EXEC_STALLED (0) If 1, an instruction written to SMx_INSTR is stalled,... + // 0x40000000 [30] SIDE_EN (0) If 1, the MSB of the Delay/Side-set instruction field is... + // 0x20000000 [29] SIDE_PINDIR (0) If 1, side-set data is asserted to pin directions,... + // 0x1f000000 [28:24] JMP_PIN (0x00) The GPIO number to use as condition for JMP PIN + // 0x00f80000 [23:19] OUT_EN_SEL (0x00) Which data bit to use for inline OUT enable + // 0x00040000 [18] INLINE_OUT_EN (0) If 1, use a bit of OUT data as an auxiliary write enable + + // 0x00020000 [17] OUT_STICKY (0) Continuously assert the most recent OUT/SET to the pins + // 0x0001f000 [16:12] WRAP_TOP (0x1f) After reaching this address, execution is wrapped to wrap_bottom + // 0x00000f80 [11:7] WRAP_BOTTOM (0x00) After reaching wrap_top, execution is wrapped to this address + // 0x00000060 [6:5] STATUS_SEL (0x0) Comparison used for the MOV x, STATUS instruction + // 0x0000001f [4:0] STATUS_N (0x00) Comparison level or IRQ index for the MOV x, STATUS instruction + io_rw_32 execctrl; + + _REG_(PIO_SM0_SHIFTCTRL_OFFSET) // PIO_SM0_SHIFTCTRL + // Control behaviour of the input/output shift registers for state machine 0 + // 0x80000000 [31] FJOIN_RX (0) When 1, RX FIFO steals the TX FIFO's storage, and... + // 0x40000000 [30] FJOIN_TX (0) When 1, TX FIFO steals the RX FIFO's storage, and... + // 0x3e000000 [29:25] PULL_THRESH (0x00) Number of bits shifted out of OSR before autopull, or... + // 0x01f00000 [24:20] PUSH_THRESH (0x00) Number of bits shifted into ISR before autopush, or... + // 0x00080000 [19] OUT_SHIFTDIR (1) 1 = shift out of output shift register to right + // 0x00040000 [18] IN_SHIFTDIR (1) 1 = shift input shift register to right (data enters from left) + // 0x00020000 [17] AUTOPULL (0) Pull automatically when the output shift register is emptied, i + // 0x00010000 [16] AUTOPUSH (0) Push automatically when the input shift register is filled, i + // 0x00008000 [15] FJOIN_RX_PUT (0) If 1, disable this state machine's RX FIFO, make its... + // 0x00004000 [14] FJOIN_RX_GET (0) If 1, disable this state machine's RX FIFO, make its... + // 0x0000001f [4:0] IN_COUNT (0x00) Set the number of pins which are not masked to 0 when... + io_rw_32 shiftctrl; + + _REG_(PIO_SM0_ADDR_OFFSET) // PIO_SM0_ADDR + // Current instruction address of state machine 0 + // 0x0000001f [4:0] SM0_ADDR (0x00) + io_ro_32 addr; + + _REG_(PIO_SM0_INSTR_OFFSET) // PIO_SM0_INSTR + // Read to see the instruction currently addressed by state machine 0's program counter + + // 0x0000ffff [15:0] SM0_INSTR (-) + io_rw_32 instr; + + _REG_(PIO_SM0_PINCTRL_OFFSET) // PIO_SM0_PINCTRL + // State machine pin control + // 0xe0000000 [31:29] SIDESET_COUNT (0x0) The number of MSBs of the Delay/Side-set instruction... + // 0x1c000000 [28:26] SET_COUNT (0x5) The number of pins asserted by a SET + // 0x03f00000 [25:20] OUT_COUNT (0x00) The number of pins asserted by an OUT PINS, OUT PINDIRS... + // 0x000f8000 [19:15] IN_BASE (0x00) The pin which is mapped to the least-significant bit of... + // 0x00007c00 [14:10] SIDESET_BASE (0x00) The lowest-numbered pin that will be affected by a... + // 0x000003e0 [9:5] SET_BASE (0x00) The lowest-numbered pin that will be affected by a SET... + // 0x0000001f [4:0] OUT_BASE (0x00) The lowest-numbered pin that will be affected by an OUT... + io_rw_32 pinctrl; +} pio_sm_hw_t; + +typedef struct { + _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE + // Interrupt Enable for irq0 + // 0x00008000 [15] SM7 (0) + // 0x00004000 [14] SM6 (0) + // 0x00002000 [13] SM5 (0) + // 0x00001000 [12] SM4 (0) + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 inte; + + _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF + // Interrupt Force for irq0 + // 0x00008000 [15] SM7 (0) + // 0x00004000 [14] SM6 (0) + // 0x00002000 [13] SM5 (0) + // 0x00001000 [12] SM4 (0) + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 intf; + + _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS + // Interrupt status after masking & forcing for irq0 + // 0x00008000 [15] SM7 (0) + // 0x00004000 [14] SM6 (0) + // 0x00002000 [13] SM5 (0) + // 0x00001000 [12] SM4 (0) + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_ro_32 ints; +} pio_irq_ctrl_hw_t; + +typedef struct { + _REG_(PIO_CTRL_OFFSET) // PIO_CTRL + // PIO control register + // 0x04000000 [26] NEXTPREV_CLKDIV_RESTART (0) Write 1 to restart the clock dividers of state machines... + // 0x02000000 [25] NEXTPREV_SM_DISABLE (0) Write 1 to disable state machines in neighbouring PIO... + // 0x01000000 [24] NEXTPREV_SM_ENABLE (0) Write 1 to enable state machines in neighbouring PIO... + // 0x00f00000 [23:20] NEXT_PIO_MASK (0x0) A mask of state machines in the neighbouring... + // 0x000f0000 [19:16] PREV_PIO_MASK (0x0) A mask of state machines in the neighbouring... + // 0x00000f00 [11:8] CLKDIV_RESTART (0x0) Restart a state machine's clock divider from an initial... + // 0x000000f0 [7:4] SM_RESTART (0x0) Write 1 to instantly clear internal SM state which may... + // 0x0000000f [3:0] SM_ENABLE (0x0) Enable/disable each of the four state machines by... + io_rw_32 ctrl; + + _REG_(PIO_FSTAT_OFFSET) // PIO_FSTAT + // FIFO status register + // 0x0f000000 [27:24] TXEMPTY (0xf) State machine TX FIFO is empty + // 0x000f0000 [19:16] TXFULL (0x0) State machine TX FIFO is full + // 0x00000f00 [11:8] RXEMPTY (0xf) State machine RX FIFO is empty + // 0x0000000f [3:0] RXFULL (0x0) State machine RX FIFO is full + io_ro_32 fstat; + + _REG_(PIO_FDEBUG_OFFSET) // PIO_FDEBUG + // FIFO debug register + // 0x0f000000 [27:24] TXSTALL (0x0) State machine has stalled on empty TX FIFO during a... + // 0x000f0000 [19:16] TXOVER (0x0) TX FIFO overflow (i + // 0x00000f00 [11:8] RXUNDER (0x0) RX FIFO underflow (i + // 0x0000000f [3:0] RXSTALL (0x0) State machine has stalled on full RX FIFO during a... + io_rw_32 fdebug; + + _REG_(PIO_FLEVEL_OFFSET) // PIO_FLEVEL + // FIFO levels + // 0xf0000000 [31:28] RX3 (0x0) + // 0x0f000000 [27:24] TX3 (0x0) + // 0x00f00000 [23:20] RX2 (0x0) + // 0x000f0000 [19:16] TX2 (0x0) + // 0x0000f000 [15:12] RX1 (0x0) + // 0x00000f00 [11:8] TX1 (0x0) + // 0x000000f0 [7:4] RX0 (0x0) + // 0x0000000f [3:0] TX0 (0x0) + io_ro_32 flevel; + + // (Description copied from array index 0 register PIO_TXF0 applies similarly to other array indexes) + _REG_(PIO_TXF0_OFFSET) // PIO_TXF0 + // Direct write access to the TX FIFO for this state machine + // 0xffffffff [31:0] TXF0 (0x00000000) + io_wo_32 txf[4]; + + // (Description copied from array index 0 register PIO_RXF0 applies similarly to other array indexes) + _REG_(PIO_RXF0_OFFSET) // PIO_RXF0 + // Direct read access to the RX FIFO for this state machine + // 0xffffffff [31:0] RXF0 (-) + io_ro_32 rxf[4]; + + _REG_(PIO_IRQ_OFFSET) // PIO_IRQ + // State machine IRQ flags register + // 0x000000ff [7:0] IRQ (0x00) + io_rw_32 irq; + + _REG_(PIO_IRQ_FORCE_OFFSET) // PIO_IRQ_FORCE + // Writing a 1 to each of these bits will forcibly assert the corresponding IRQ + // 0x000000ff [7:0] IRQ_FORCE (0x00) + io_wo_32 irq_force; + + _REG_(PIO_INPUT_SYNC_BYPASS_OFFSET) // PIO_INPUT_SYNC_BYPASS + // There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities + // 0xffffffff [31:0] INPUT_SYNC_BYPASS (0x00000000) + io_rw_32 input_sync_bypass; + + _REG_(PIO_DBG_PADOUT_OFFSET) // PIO_DBG_PADOUT + // Read to sample the pad output values PIO is currently driving to the GPIOs + // 0xffffffff [31:0] DBG_PADOUT (0x00000000) + io_ro_32 dbg_padout; + + _REG_(PIO_DBG_PADOE_OFFSET) // PIO_DBG_PADOE + // Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs + // 0xffffffff [31:0] DBG_PADOE (0x00000000) + io_ro_32 dbg_padoe; + + _REG_(PIO_DBG_CFGINFO_OFFSET) // PIO_DBG_CFGINFO + // The PIO hardware has some free parameters that may vary between chip products + // 0xf0000000 [31:28] VERSION (0x1) Version of the core PIO hardware + // 0x003f0000 [21:16] IMEM_SIZE (-) The size of the instruction memory, measured in units of... + // 0x00000f00 [11:8] SM_COUNT (-) The number of state machines this PIO instance is equipped with + // 0x0000003f [5:0] FIFO_DEPTH (-) The depth of the state machine TX/RX FIFOs, measured in words + io_ro_32 dbg_cfginfo; + + // (Description copied from array index 0 register PIO_INSTR_MEM0 applies similarly to other array indexes) + _REG_(PIO_INSTR_MEM0_OFFSET) // PIO_INSTR_MEM0 + // Write-only access to instruction memory location 0 + // 0x0000ffff [15:0] INSTR_MEM0 (0x0000) + io_wo_32 instr_mem[32]; + + pio_sm_hw_t sm[4]; + + // (Description copied from array index 0 register PIO_RXF0_PUTGET0 applies similarly to other array indexes) + _REG_(PIO_RXF0_PUTGET0_OFFSET) // PIO_RXF0_PUTGET0 + // Direct read/write access to the RX FIFO on all SMs, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set + // 0xffffffff [31:0] RXF0_PUTGET0 (0x00000000) + io_rw_32 rxf_putget[4][4]; + + _REG_(PIO_GPIOBASE_OFFSET) // PIO_GPIOBASE + // Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering, to access more than 32... + // 0x00000010 [4] GPIOBASE (0) + io_rw_32 gpiobase; + + _REG_(PIO_INTR_OFFSET) // PIO_INTR + // Raw Interrupts + // 0x00008000 [15] SM7 (0) + // 0x00004000 [14] SM6 (0) + // 0x00002000 [13] SM5 (0) + // 0x00001000 [12] SM4 (0) + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_ro_32 intr; + + union { + struct { + _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE + // Interrupt Enable for irq0 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 inte0; + + _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF + // Interrupt Force for irq0 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 intf0; + + _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS + // Interrupt status after masking & forcing for irq0 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_ro_32 ints0; + + _REG_(PIO_IRQ1_INTE_OFFSET) // PIO_IRQ1_INTE + // Interrupt Enable for irq1 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 inte1; + + _REG_(PIO_IRQ1_INTF_OFFSET) // PIO_IRQ1_INTF + // Interrupt Force for irq1 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 intf1; + + _REG_(PIO_IRQ1_INTS_OFFSET) // PIO_IRQ1_INTS + // Interrupt status after masking & forcing for irq1 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_ro_32 ints1; + }; + pio_irq_ctrl_hw_t irq_ctrl[2]; + }; +} pio_hw_t; + +#define pio0_hw ((pio_hw_t *)PIO0_BASE) +#define pio1_hw ((pio_hw_t *)PIO1_BASE) +#define pio2_hw ((pio_hw_t *)PIO2_BASE) +static_assert(sizeof (pio_hw_t) == 0x0188, ""); + +#endif // _HARDWARE_STRUCTS_PIO_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/pll.h b/lib/pico-sdk/rp2350/hardware/structs/pll.h new file mode 100644 index 00000000..8a727604 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/pll.h @@ -0,0 +1,82 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_PLL_H +#define _HARDWARE_STRUCTS_PLL_H + +/** + * \file rp2350/pll.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/pll.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_pll +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pll.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/// \tag::pll_hw[] +typedef struct { + _REG_(PLL_CS_OFFSET) // PLL_CS + // Control and Status + // 0x80000000 [31] LOCK (0) PLL is locked + // 0x40000000 [30] LOCK_N (0) PLL is not locked + + // 0x00000100 [8] BYPASS (0) Passes the reference clock to the output instead of the... + // 0x0000003f [5:0] REFDIV (0x01) Divides the PLL input reference clock + io_rw_32 cs; + + _REG_(PLL_PWR_OFFSET) // PLL_PWR + // Controls the PLL power modes + // 0x00000020 [5] VCOPD (1) PLL VCO powerdown + + // 0x00000008 [3] POSTDIVPD (1) PLL post divider powerdown + + // 0x00000004 [2] DSMPD (1) PLL DSM powerdown + + // 0x00000001 [0] PD (1) PLL powerdown + + io_rw_32 pwr; + + _REG_(PLL_FBDIV_INT_OFFSET) // PLL_FBDIV_INT + // Feedback divisor + // 0x00000fff [11:0] FBDIV_INT (0x000) see ctrl reg description for constraints + io_rw_32 fbdiv_int; + + _REG_(PLL_PRIM_OFFSET) // PLL_PRIM + // Controls the PLL post dividers for the primary output + // 0x00070000 [18:16] POSTDIV1 (0x7) divide by 1-7 + // 0x00007000 [14:12] POSTDIV2 (0x7) divide by 1-7 + io_rw_32 prim; + + _REG_(PLL_INTR_OFFSET) // PLL_INTR + // Raw Interrupts + // 0x00000001 [0] LOCK_N_STICKY (0) + io_rw_32 intr; + + _REG_(PLL_INTE_OFFSET) // PLL_INTE + // Interrupt Enable + // 0x00000001 [0] LOCK_N_STICKY (0) + io_rw_32 inte; + + _REG_(PLL_INTF_OFFSET) // PLL_INTF + // Interrupt Force + // 0x00000001 [0] LOCK_N_STICKY (0) + io_rw_32 intf; + + _REG_(PLL_INTS_OFFSET) // PLL_INTS + // Interrupt status after masking & forcing + // 0x00000001 [0] LOCK_N_STICKY (0) + io_ro_32 ints; +} pll_hw_t; +/// \end::pll_hw[] + +#define pll_sys_hw ((pll_hw_t *)PLL_SYS_BASE) +#define pll_usb_hw ((pll_hw_t *)PLL_USB_BASE) +static_assert(sizeof (pll_hw_t) == 0x0020, ""); + +#endif // _HARDWARE_STRUCTS_PLL_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/powman.h b/lib/pico-sdk/rp2350/hardware/structs/powman.h new file mode 100644 index 00000000..a81890e3 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/powman.h @@ -0,0 +1,338 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_POWMAN_H +#define _HARDWARE_STRUCTS_POWMAN_H + +/** + * \file rp2350/powman.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/powman.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_powman +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/powman.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(POWMAN_BADPASSWD_OFFSET) // POWMAN_BADPASSWD + // Indicates a bad password has been used + // 0x00000001 [0] BADPASSWD (0) + io_rw_32 badpasswd; + + _REG_(POWMAN_VREG_CTRL_OFFSET) // POWMAN_VREG_CTRL + // Voltage Regulator Control + // 0x00008000 [15] RST_N (1) returns the regulator to its startup settings + + // 0x00002000 [13] UNLOCK (0) unlocks the VREG control interface after power up + + // 0x00001000 [12] ISOLATE (0) isolates the VREG control interface + + // 0x00000100 [8] DISABLE_VOLTAGE_LIMIT (0) 0=not disabled, 1=enabled + // 0x00000070 [6:4] HT_TH (0x5) high temperature protection threshold + + io_rw_32 vreg_ctrl; + + _REG_(POWMAN_VREG_STS_OFFSET) // POWMAN_VREG_STS + // Voltage Regulator Status + // 0x00000010 [4] VOUT_OK (0) output regulation status + + // 0x00000001 [0] STARTUP (0) startup status + + io_ro_32 vreg_sts; + + _REG_(POWMAN_VREG_OFFSET) // POWMAN_VREG + // Voltage Regulator Settings + // 0x00008000 [15] UPDATE_IN_PROGRESS (0) regulator state is being updated + + // 0x000001f0 [8:4] VSEL (0x0b) output voltage select + + // 0x00000002 [1] HIZ (0) high impedance mode select + + io_rw_32 vreg; + + _REG_(POWMAN_VREG_LP_ENTRY_OFFSET) // POWMAN_VREG_LP_ENTRY + // Voltage Regulator Low Power Entry Settings + // 0x000001f0 [8:4] VSEL (0x0b) output voltage select + + // 0x00000004 [2] MODE (1) selects either normal (switching) mode or low power... + // 0x00000002 [1] HIZ (0) high impedance mode select + + io_rw_32 vreg_lp_entry; + + _REG_(POWMAN_VREG_LP_EXIT_OFFSET) // POWMAN_VREG_LP_EXIT + // Voltage Regulator Low Power Exit Settings + // 0x000001f0 [8:4] VSEL (0x0b) output voltage select + + // 0x00000004 [2] MODE (0) selects either normal (switching) mode or low power... + // 0x00000002 [1] HIZ (0) high impedance mode select + + io_rw_32 vreg_lp_exit; + + _REG_(POWMAN_BOD_CTRL_OFFSET) // POWMAN_BOD_CTRL + // Brown-out Detection Control + // 0x00001000 [12] ISOLATE (0) isolates the brown-out detection control interface + + io_rw_32 bod_ctrl; + + _REG_(POWMAN_BOD_OFFSET) // POWMAN_BOD + // Brown-out Detection Settings + // 0x000001f0 [8:4] VSEL (0x0b) threshold select + + // 0x00000001 [0] EN (1) enable brown-out detection + + io_rw_32 bod; + + _REG_(POWMAN_BOD_LP_ENTRY_OFFSET) // POWMAN_BOD_LP_ENTRY + // Brown-out Detection Low Power Entry Settings + // 0x000001f0 [8:4] VSEL (0x0b) threshold select + + // 0x00000001 [0] EN (0) enable brown-out detection + + io_rw_32 bod_lp_entry; + + _REG_(POWMAN_BOD_LP_EXIT_OFFSET) // POWMAN_BOD_LP_EXIT + // Brown-out Detection Low Power Exit Settings + // 0x000001f0 [8:4] VSEL (0x0b) threshold select + + // 0x00000001 [0] EN (1) enable brown-out detection + + io_rw_32 bod_lp_exit; + + _REG_(POWMAN_LPOSC_OFFSET) // POWMAN_LPOSC + // Low power oscillator control register + // 0x000003f0 [9:4] TRIM (0x20) Frequency trim - the trim step is typically 1% of the... + // 0x00000003 [1:0] MODE (0x3) This feature has been removed + io_rw_32 lposc; + + _REG_(POWMAN_CHIP_RESET_OFFSET) // POWMAN_CHIP_RESET + // Chip reset control and status + // 0x10000000 [28] HAD_WATCHDOG_RESET_RSM (0) Last reset was a watchdog timeout which was configured... + // 0x08000000 [27] HAD_HZD_SYS_RESET_REQ (0) Last reset was a system reset from the hazard debugger + + // 0x04000000 [26] HAD_GLITCH_DETECT (0) Last reset was due to a power supply glitch + + // 0x02000000 [25] HAD_SWCORE_PD (0) Last reset was a switched core powerdown + + // 0x01000000 [24] HAD_WATCHDOG_RESET_SWCORE (0) Last reset was a watchdog timeout which was configured... + // 0x00800000 [23] HAD_WATCHDOG_RESET_POWMAN (0) Last reset was a watchdog timeout which was configured... + // 0x00400000 [22] HAD_WATCHDOG_RESET_POWMAN_ASYNC (0) Last reset was a watchdog timeout which was configured... + // 0x00200000 [21] HAD_RESCUE (0) Last reset was a rescue reset from the debugger + + // 0x00080000 [19] HAD_DP_RESET_REQ (0) Last reset was an reset request from the arm debugger + + // 0x00040000 [18] HAD_RUN_LOW (0) Last reset was from the RUN pin + + // 0x00020000 [17] HAD_BOR (0) Last reset was from the brown-out detection block + + // 0x00010000 [16] HAD_POR (0) Last reset was from the power-on reset + + // 0x00000010 [4] RESCUE_FLAG (0) This is set by a rescue reset from the RP-AP + // 0x00000001 [0] DOUBLE_TAP (0) This flag is set by double-tapping RUN + io_rw_32 chip_reset; + + _REG_(POWMAN_WDSEL_OFFSET) // POWMAN_WDSEL + // Allows a watchdog reset to reset the internal state of powman in addition to the power-on state... + // 0x00001000 [12] RESET_RSM (0) If set to 1, a watchdog reset will run the full power-on... + // 0x00000100 [8] RESET_SWCORE (0) If set to 1, a watchdog reset will reset the switched... + // 0x00000010 [4] RESET_POWMAN (0) If set to 1, a watchdog reset will restore powman... + // 0x00000001 [0] RESET_POWMAN_ASYNC (0) If set to 1, a watchdog reset will restore powman... + io_rw_32 wdsel; + + _REG_(POWMAN_SEQ_CFG_OFFSET) // POWMAN_SEQ_CFG + // For configuration of the power sequencer + + // 0x00100000 [20] USING_FAST_POWCK (1) 0 indicates the POWMAN clock is running from the low... + // 0x00020000 [17] USING_BOD_LP (0) Indicates the brown-out detector (BOD) mode + + // 0x00010000 [16] USING_VREG_LP (0) Indicates the voltage regulator (VREG) mode + + // 0x00001000 [12] USE_FAST_POWCK (1) selects the reference clock (clk_ref) as the source of... + // 0x00000100 [8] RUN_LPOSC_IN_LP (1) Set to 0 to stop the low power osc when the... + // 0x00000080 [7] USE_BOD_HP (1) Set to 0 to prevent automatic switching to bod high... + // 0x00000040 [6] USE_BOD_LP (1) Set to 0 to prevent automatic switching to bod low power... + // 0x00000020 [5] USE_VREG_HP (1) Set to 0 to prevent automatic switching to vreg high... + // 0x00000010 [4] USE_VREG_LP (1) Set to 0 to prevent automatic switching to vreg low... + // 0x00000002 [1] HW_PWRUP_SRAM0 (0) Specifies the power state of SRAM0 when powering up... + // 0x00000001 [0] HW_PWRUP_SRAM1 (0) Specifies the power state of SRAM1 when powering up... + io_rw_32 seq_cfg; + + _REG_(POWMAN_STATE_OFFSET) // POWMAN_STATE + // This register controls the power state of the 4 power domains + // 0x00002000 [13] CHANGING (0) + // 0x00001000 [12] WAITING (0) + // 0x00000800 [11] BAD_HW_REQ (0) Bad hardware initiated state request + // 0x00000400 [10] BAD_SW_REQ (0) Bad software initiated state request + // 0x00000200 [9] PWRUP_WHILE_WAITING (0) Request ignored because of a pending pwrup request + // 0x00000100 [8] REQ_IGNORED (0) + // 0x000000f0 [7:4] REQ (0x0) + // 0x0000000f [3:0] CURRENT (0xf) + io_rw_32 state; + + _REG_(POWMAN_POW_FASTDIV_OFFSET) // POWMAN_POW_FASTDIV + // 0x000007ff [10:0] POW_FASTDIV (0x040) divides the POWMAN clock to provide a tick for the delay... + io_rw_32 pow_fastdiv; + + _REG_(POWMAN_POW_DELAY_OFFSET) // POWMAN_POW_DELAY + // power state machine delays + // 0x0000ff00 [15:8] SRAM_STEP (0x20) timing between the sram0 and sram1 power state machine steps + + // 0x000000f0 [7:4] XIP_STEP (0x1) timing between the xip power state machine steps + + // 0x0000000f [3:0] SWCORE_STEP (0x1) timing between the swcore power state machine steps + + io_rw_32 pow_delay; + + // (Description copied from array index 0 register POWMAN_EXT_CTRL0 applies similarly to other array indexes) + _REG_(POWMAN_EXT_CTRL0_OFFSET) // POWMAN_EXT_CTRL0 + // Configures a gpio as a power mode aware control output + // 0x00004000 [14] LP_EXIT_STATE (0) output level when exiting the low power state + // 0x00002000 [13] LP_ENTRY_STATE (0) output level when entering the low power state + // 0x00001000 [12] INIT_STATE (0) + // 0x00000100 [8] INIT (0) + // 0x0000003f [5:0] GPIO_SELECT (0x3f) selects from gpio 0->30 + + io_rw_32 ext_ctrl[2]; + + _REG_(POWMAN_EXT_TIME_REF_OFFSET) // POWMAN_EXT_TIME_REF + // Select a GPIO to use as a time reference, the source can be used to drive the low power clock at... + // 0x00000010 [4] DRIVE_LPCK (0) Use the selected GPIO to drive the 32kHz low power... + // 0x00000003 [1:0] SOURCE_SEL (0x0) 0 -> gpio12 + + io_rw_32 ext_time_ref; + + _REG_(POWMAN_LPOSC_FREQ_KHZ_INT_OFFSET) // POWMAN_LPOSC_FREQ_KHZ_INT + // Informs the AON Timer of the integer component of the clock frequency when running off the LPOSC + // 0x0000003f [5:0] LPOSC_FREQ_KHZ_INT (0x20) Integer component of the LPOSC or GPIO clock source... + io_rw_32 lposc_freq_khz_int; + + _REG_(POWMAN_LPOSC_FREQ_KHZ_FRAC_OFFSET) // POWMAN_LPOSC_FREQ_KHZ_FRAC + // Informs the AON Timer of the fractional component of the clock frequency when running off the LPOSC + // 0x0000ffff [15:0] LPOSC_FREQ_KHZ_FRAC (0xc49c) Fractional component of the LPOSC or GPIO clock source... + io_rw_32 lposc_freq_khz_frac; + + _REG_(POWMAN_XOSC_FREQ_KHZ_INT_OFFSET) // POWMAN_XOSC_FREQ_KHZ_INT + // Informs the AON Timer of the integer component of the clock frequency when running off the XOSC + // 0x0000ffff [15:0] XOSC_FREQ_KHZ_INT (0x2ee0) Integer component of the XOSC frequency in kHz + io_rw_32 xosc_freq_khz_int; + + _REG_(POWMAN_XOSC_FREQ_KHZ_FRAC_OFFSET) // POWMAN_XOSC_FREQ_KHZ_FRAC + // Informs the AON Timer of the fractional component of the clock frequency when running off the XOSC + // 0x0000ffff [15:0] XOSC_FREQ_KHZ_FRAC (0x0000) Fractional component of the XOSC frequency in kHz + io_rw_32 xosc_freq_khz_frac; + + _REG_(POWMAN_SET_TIME_63TO48_OFFSET) // POWMAN_SET_TIME_63TO48 + // 0x0000ffff [15:0] SET_TIME_63TO48 (0x0000) For setting the time, do not use for reading the time,... + io_rw_32 set_time_63to48; + + _REG_(POWMAN_SET_TIME_47TO32_OFFSET) // POWMAN_SET_TIME_47TO32 + // 0x0000ffff [15:0] SET_TIME_47TO32 (0x0000) For setting the time, do not use for reading the time,... + io_rw_32 set_time_47to32; + + _REG_(POWMAN_SET_TIME_31TO16_OFFSET) // POWMAN_SET_TIME_31TO16 + // 0x0000ffff [15:0] SET_TIME_31TO16 (0x0000) For setting the time, do not use for reading the time,... + io_rw_32 set_time_31to16; + + _REG_(POWMAN_SET_TIME_15TO0_OFFSET) // POWMAN_SET_TIME_15TO0 + // 0x0000ffff [15:0] SET_TIME_15TO0 (0x0000) For setting the time, do not use for reading the time,... + io_rw_32 set_time_15to0; + + _REG_(POWMAN_READ_TIME_UPPER_OFFSET) // POWMAN_READ_TIME_UPPER + // 0xffffffff [31:0] READ_TIME_UPPER (0x00000000) For reading bits 63:32 of the timer + io_ro_32 read_time_upper; + + _REG_(POWMAN_READ_TIME_LOWER_OFFSET) // POWMAN_READ_TIME_LOWER + // 0xffffffff [31:0] READ_TIME_LOWER (0x00000000) For reading bits 31:0 of the timer + io_ro_32 read_time_lower; + + _REG_(POWMAN_ALARM_TIME_63TO48_OFFSET) // POWMAN_ALARM_TIME_63TO48 + // 0x0000ffff [15:0] ALARM_TIME_63TO48 (0x0000) This field must only be written when POWMAN_ALARM_ENAB=0 + io_rw_32 alarm_time_63to48; + + _REG_(POWMAN_ALARM_TIME_47TO32_OFFSET) // POWMAN_ALARM_TIME_47TO32 + // 0x0000ffff [15:0] ALARM_TIME_47TO32 (0x0000) This field must only be written when POWMAN_ALARM_ENAB=0 + io_rw_32 alarm_time_47to32; + + _REG_(POWMAN_ALARM_TIME_31TO16_OFFSET) // POWMAN_ALARM_TIME_31TO16 + // 0x0000ffff [15:0] ALARM_TIME_31TO16 (0x0000) This field must only be written when POWMAN_ALARM_ENAB=0 + io_rw_32 alarm_time_31to16; + + _REG_(POWMAN_ALARM_TIME_15TO0_OFFSET) // POWMAN_ALARM_TIME_15TO0 + // 0x0000ffff [15:0] ALARM_TIME_15TO0 (0x0000) This field must only be written when POWMAN_ALARM_ENAB=0 + io_rw_32 alarm_time_15to0; + + _REG_(POWMAN_TIMER_OFFSET) // POWMAN_TIMER + // 0x00080000 [19] USING_GPIO_1HZ (0) Timer is synchronised to a 1hz gpio source + // 0x00040000 [18] USING_GPIO_1KHZ (0) Timer is running from a 1khz gpio source + // 0x00020000 [17] USING_LPOSC (0) Timer is running from lposc + // 0x00010000 [16] USING_XOSC (0) Timer is running from xosc + // 0x00002000 [13] USE_GPIO_1HZ (0) Selects the gpio source as the reference for the sec counter + // 0x00000400 [10] USE_GPIO_1KHZ (0) switch to gpio as the source of the 1kHz timer tick + // 0x00000200 [9] USE_XOSC (0) switch to xosc as the source of the 1kHz timer tick + // 0x00000100 [8] USE_LPOSC (0) Switch to lposc as the source of the 1kHz timer tick + // 0x00000040 [6] ALARM (0) Alarm has fired + // 0x00000020 [5] PWRUP_ON_ALARM (0) Alarm wakes the chip from low power mode + // 0x00000010 [4] ALARM_ENAB (0) Enables the alarm + // 0x00000004 [2] CLEAR (0) Clears the timer, does not disable the timer and does... + // 0x00000002 [1] RUN (0) Timer enable + // 0x00000001 [0] NONSEC_WRITE (0) Control whether Non-secure software can write to the... + io_rw_32 timer; + + // (Description copied from array index 0 register POWMAN_PWRUP0 applies similarly to other array indexes) + _REG_(POWMAN_PWRUP0_OFFSET) // POWMAN_PWRUP0 + // 4 GPIO powerup events can be configured to wake the chip up from a low power state + // 0x00000400 [10] RAW_STATUS (0) Value of selected gpio pin (only if enable == 1) + // 0x00000200 [9] STATUS (0) Status of gpio wakeup + // 0x00000100 [8] MODE (0) Edge or level detect + // 0x00000080 [7] DIRECTION (0) + // 0x00000040 [6] ENABLE (0) Set to 1 to enable the wakeup source + // 0x0000003f [5:0] SOURCE (0x3f) + io_rw_32 pwrup[4]; + + _REG_(POWMAN_CURRENT_PWRUP_REQ_OFFSET) // POWMAN_CURRENT_PWRUP_REQ + // Indicates current powerup request state + + // 0x0000007f [6:0] CURRENT_PWRUP_REQ (0x00) + io_ro_32 current_pwrup_req; + + _REG_(POWMAN_LAST_SWCORE_PWRUP_OFFSET) // POWMAN_LAST_SWCORE_PWRUP + // Indicates which pwrup source triggered the last switched-core power up + + // 0x0000007f [6:0] LAST_SWCORE_PWRUP (0x00) + io_ro_32 last_swcore_pwrup; + + _REG_(POWMAN_DBG_PWRCFG_OFFSET) // POWMAN_DBG_PWRCFG + // 0x00000001 [0] IGNORE (0) Ignore pwrup req from debugger + io_rw_32 dbg_pwrcfg; + + _REG_(POWMAN_BOOTDIS_OFFSET) // POWMAN_BOOTDIS + // Tell the bootrom to ignore the BOOT0 + // 0x00000002 [1] NEXT (0) This flag always ORs writes into its current contents + // 0x00000001 [0] NOW (0) When powman resets the RSM, the current value of... + io_rw_32 bootdis; + + _REG_(POWMAN_DBGCONFIG_OFFSET) // POWMAN_DBGCONFIG + // 0x0000000f [3:0] DP_INSTID (0x0) Configure DP instance ID for SWD multidrop selection + io_rw_32 dbgconfig; + + // (Description copied from array index 0 register POWMAN_SCRATCH0 applies similarly to other array indexes) + _REG_(POWMAN_SCRATCH0_OFFSET) // POWMAN_SCRATCH0 + // Scratch register + // 0xffffffff [31:0] SCRATCH0 (0x00000000) + io_rw_32 scratch[8]; + + // (Description copied from array index 0 register POWMAN_BOOT0 applies similarly to other array indexes) + _REG_(POWMAN_BOOT0_OFFSET) // POWMAN_BOOT0 + // Scratch register + // 0xffffffff [31:0] BOOT0 (0x00000000) + io_rw_32 boot[4]; + + _REG_(POWMAN_INTR_OFFSET) // POWMAN_INTR + // Raw Interrupts + // 0x00000008 [3] PWRUP_WHILE_WAITING (0) Source is state + // 0x00000004 [2] STATE_REQ_IGNORED (0) Source is state + // 0x00000002 [1] TIMER (0) + // 0x00000001 [0] VREG_OUTPUT_LOW (0) + io_rw_32 intr; + + _REG_(POWMAN_INTE_OFFSET) // POWMAN_INTE + // Interrupt Enable + // 0x00000008 [3] PWRUP_WHILE_WAITING (0) Source is state + // 0x00000004 [2] STATE_REQ_IGNORED (0) Source is state + // 0x00000002 [1] TIMER (0) + // 0x00000001 [0] VREG_OUTPUT_LOW (0) + io_rw_32 inte; + + _REG_(POWMAN_INTF_OFFSET) // POWMAN_INTF + // Interrupt Force + // 0x00000008 [3] PWRUP_WHILE_WAITING (0) Source is state + // 0x00000004 [2] STATE_REQ_IGNORED (0) Source is state + // 0x00000002 [1] TIMER (0) + // 0x00000001 [0] VREG_OUTPUT_LOW (0) + io_rw_32 intf; + + _REG_(POWMAN_INTS_OFFSET) // POWMAN_INTS + // Interrupt status after masking & forcing + // 0x00000008 [3] PWRUP_WHILE_WAITING (0) Source is state + // 0x00000004 [2] STATE_REQ_IGNORED (0) Source is state + // 0x00000002 [1] TIMER (0) + // 0x00000001 [0] VREG_OUTPUT_LOW (0) + io_ro_32 ints; +} powman_hw_t; + +#define powman_hw ((powman_hw_t *)POWMAN_BASE) +static_assert(sizeof (powman_hw_t) == 0x00f0, ""); + +#endif // _HARDWARE_STRUCTS_POWMAN_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/psm.h b/lib/pico-sdk/rp2350/hardware/structs/psm.h new file mode 100644 index 00000000..92144ac6 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/psm.h @@ -0,0 +1,148 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_PSM_H +#define _HARDWARE_STRUCTS_PSM_H + +/** + * \file rp2350/psm.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/psm.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_psm +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/psm.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(PSM_FRCE_ON_OFFSET) // PSM_FRCE_ON + // Force block out of reset (i + // 0x01000000 [24] PROC1 (0) + // 0x00800000 [23] PROC0 (0) + // 0x00400000 [22] ACCESSCTRL (0) + // 0x00200000 [21] SIO (0) + // 0x00100000 [20] XIP (0) + // 0x00080000 [19] SRAM9 (0) + // 0x00040000 [18] SRAM8 (0) + // 0x00020000 [17] SRAM7 (0) + // 0x00010000 [16] SRAM6 (0) + // 0x00008000 [15] SRAM5 (0) + // 0x00004000 [14] SRAM4 (0) + // 0x00002000 [13] SRAM3 (0) + // 0x00001000 [12] SRAM2 (0) + // 0x00000800 [11] SRAM1 (0) + // 0x00000400 [10] SRAM0 (0) + // 0x00000200 [9] BOOTRAM (0) + // 0x00000100 [8] ROM (0) + // 0x00000080 [7] BUSFABRIC (0) + // 0x00000040 [6] PSM_READY (0) + // 0x00000020 [5] CLOCKS (0) + // 0x00000010 [4] RESETS (0) + // 0x00000008 [3] XOSC (0) + // 0x00000004 [2] ROSC (0) + // 0x00000002 [1] OTP (0) + // 0x00000001 [0] PROC_COLD (0) + io_rw_32 frce_on; + + _REG_(PSM_FRCE_OFF_OFFSET) // PSM_FRCE_OFF + // Force into reset (i + // 0x01000000 [24] PROC1 (0) + // 0x00800000 [23] PROC0 (0) + // 0x00400000 [22] ACCESSCTRL (0) + // 0x00200000 [21] SIO (0) + // 0x00100000 [20] XIP (0) + // 0x00080000 [19] SRAM9 (0) + // 0x00040000 [18] SRAM8 (0) + // 0x00020000 [17] SRAM7 (0) + // 0x00010000 [16] SRAM6 (0) + // 0x00008000 [15] SRAM5 (0) + // 0x00004000 [14] SRAM4 (0) + // 0x00002000 [13] SRAM3 (0) + // 0x00001000 [12] SRAM2 (0) + // 0x00000800 [11] SRAM1 (0) + // 0x00000400 [10] SRAM0 (0) + // 0x00000200 [9] BOOTRAM (0) + // 0x00000100 [8] ROM (0) + // 0x00000080 [7] BUSFABRIC (0) + // 0x00000040 [6] PSM_READY (0) + // 0x00000020 [5] CLOCKS (0) + // 0x00000010 [4] RESETS (0) + // 0x00000008 [3] XOSC (0) + // 0x00000004 [2] ROSC (0) + // 0x00000002 [1] OTP (0) + // 0x00000001 [0] PROC_COLD (0) + io_rw_32 frce_off; + + _REG_(PSM_WDSEL_OFFSET) // PSM_WDSEL + // Set to 1 if the watchdog should reset this + // 0x01000000 [24] PROC1 (0) + // 0x00800000 [23] PROC0 (0) + // 0x00400000 [22] ACCESSCTRL (0) + // 0x00200000 [21] SIO (0) + // 0x00100000 [20] XIP (0) + // 0x00080000 [19] SRAM9 (0) + // 0x00040000 [18] SRAM8 (0) + // 0x00020000 [17] SRAM7 (0) + // 0x00010000 [16] SRAM6 (0) + // 0x00008000 [15] SRAM5 (0) + // 0x00004000 [14] SRAM4 (0) + // 0x00002000 [13] SRAM3 (0) + // 0x00001000 [12] SRAM2 (0) + // 0x00000800 [11] SRAM1 (0) + // 0x00000400 [10] SRAM0 (0) + // 0x00000200 [9] BOOTRAM (0) + // 0x00000100 [8] ROM (0) + // 0x00000080 [7] BUSFABRIC (0) + // 0x00000040 [6] PSM_READY (0) + // 0x00000020 [5] CLOCKS (0) + // 0x00000010 [4] RESETS (0) + // 0x00000008 [3] XOSC (0) + // 0x00000004 [2] ROSC (0) + // 0x00000002 [1] OTP (0) + // 0x00000001 [0] PROC_COLD (0) + io_rw_32 wdsel; + + _REG_(PSM_DONE_OFFSET) // PSM_DONE + // Is the subsystem ready? + // 0x01000000 [24] PROC1 (0) + // 0x00800000 [23] PROC0 (0) + // 0x00400000 [22] ACCESSCTRL (0) + // 0x00200000 [21] SIO (0) + // 0x00100000 [20] XIP (0) + // 0x00080000 [19] SRAM9 (0) + // 0x00040000 [18] SRAM8 (0) + // 0x00020000 [17] SRAM7 (0) + // 0x00010000 [16] SRAM6 (0) + // 0x00008000 [15] SRAM5 (0) + // 0x00004000 [14] SRAM4 (0) + // 0x00002000 [13] SRAM3 (0) + // 0x00001000 [12] SRAM2 (0) + // 0x00000800 [11] SRAM1 (0) + // 0x00000400 [10] SRAM0 (0) + // 0x00000200 [9] BOOTRAM (0) + // 0x00000100 [8] ROM (0) + // 0x00000080 [7] BUSFABRIC (0) + // 0x00000040 [6] PSM_READY (0) + // 0x00000020 [5] CLOCKS (0) + // 0x00000010 [4] RESETS (0) + // 0x00000008 [3] XOSC (0) + // 0x00000004 [2] ROSC (0) + // 0x00000002 [1] OTP (0) + // 0x00000001 [0] PROC_COLD (0) + io_ro_32 done; +} psm_hw_t; + +#define psm_hw ((psm_hw_t *)PSM_BASE) +static_assert(sizeof (psm_hw_t) == 0x0010, ""); + +#endif // _HARDWARE_STRUCTS_PSM_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/pwm.h b/lib/pico-sdk/rp2350/hardware/structs/pwm.h new file mode 100644 index 00000000..be0e24e5 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/pwm.h @@ -0,0 +1,252 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_PWM_H +#define _HARDWARE_STRUCTS_PWM_H + +/** + * \file rp2350/pwm.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/pwm.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_pwm +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pwm.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(PWM_CH0_CSR_OFFSET) // PWM_CH0_CSR + // Control and status register + // 0x00000080 [7] PH_ADV (0) Advance the phase of the counter by 1 count, while it is running + // 0x00000040 [6] PH_RET (0) Retard the phase of the counter by 1 count, while it is running + // 0x00000030 [5:4] DIVMODE (0x0) + // 0x00000008 [3] B_INV (0) Invert output B + // 0x00000004 [2] A_INV (0) Invert output A + // 0x00000002 [1] PH_CORRECT (0) 1: Enable phase-correct modulation + // 0x00000001 [0] EN (0) Enable the PWM channel + io_rw_32 csr; + + _REG_(PWM_CH0_DIV_OFFSET) // PWM_CH0_DIV + // INT and FRAC form a fixed-point fractional number + // 0x00000ff0 [11:4] INT (0x01) + // 0x0000000f [3:0] FRAC (0x0) + io_rw_32 div; + + _REG_(PWM_CH0_CTR_OFFSET) // PWM_CH0_CTR + // Direct access to the PWM counter + // 0x0000ffff [15:0] CH0_CTR (0x0000) + io_rw_32 ctr; + + _REG_(PWM_CH0_CC_OFFSET) // PWM_CH0_CC + // Counter compare values + // 0xffff0000 [31:16] B (0x0000) + // 0x0000ffff [15:0] A (0x0000) + io_rw_32 cc; + + _REG_(PWM_CH0_TOP_OFFSET) // PWM_CH0_TOP + // Counter wrap value + // 0x0000ffff [15:0] CH0_TOP (0xffff) + io_rw_32 top; +} pwm_slice_hw_t; + +typedef struct { + _REG_(PWM_IRQ0_INTE_OFFSET) // PWM_IRQ0_INTE + // Interrupt Enable for irq0 + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 inte; + + _REG_(PWM_IRQ0_INTF_OFFSET) // PWM_IRQ0_INTF + // Interrupt Force for irq0 + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 intf; + + _REG_(PWM_IRQ0_INTS_OFFSET) // PWM_IRQ0_INTS + // Interrupt status after masking & forcing for irq0 + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_ro_32 ints; +} pwm_irq_ctrl_hw_t; + +typedef struct { + pwm_slice_hw_t slice[12]; + + _REG_(PWM_EN_OFFSET) // PWM_EN + // This register aliases the CSR_EN bits for all channels + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 en; + + _REG_(PWM_INTR_OFFSET) // PWM_INTR + // Raw Interrupts + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 intr; + + union { + struct { + _REG_(PWM_IRQ0_INTE_OFFSET) // PWM_IRQ0_INTE + // Interrupt Enable for irq0 + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 inte; + + _REG_(PWM_IRQ0_INTF_OFFSET) // PWM_IRQ0_INTF + // Interrupt Force for irq0 + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 intf; + + _REG_(PWM_IRQ0_INTS_OFFSET) // PWM_IRQ0_INTS + // Interrupt status after masking & forcing for irq0 + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 ints; + + _REG_(PWM_IRQ1_INTE_OFFSET) // PWM_IRQ1_INTE + // Interrupt Enable for irq1 + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 inte1; + + _REG_(PWM_IRQ1_INTF_OFFSET) // PWM_IRQ1_INTF + // Interrupt Force for irq1 + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 intf1; + + _REG_(PWM_IRQ1_INTS_OFFSET) // PWM_IRQ1_INTS + // Interrupt status after masking & forcing for irq1 + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 ints1; + }; + pwm_irq_ctrl_hw_t irq_ctrl[2]; + }; +} pwm_hw_t; + +#define pwm_hw ((pwm_hw_t *)PWM_BASE) +static_assert(sizeof (pwm_hw_t) == 0x0110, ""); + +#endif // _HARDWARE_STRUCTS_PWM_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/qmi.h b/lib/pico-sdk/rp2350/hardware/structs/qmi.h new file mode 100644 index 00000000..bbcbd769 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/qmi.h @@ -0,0 +1,125 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_QMI_H +#define _HARDWARE_STRUCTS_QMI_H + +/** + * \file rp2350/qmi.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/qmi.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_qmi +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/qmi.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(QMI_M0_TIMING_OFFSET) // QMI_M0_TIMING + // Timing configuration register for memory address window 0 + // 0xc0000000 [31:30] COOLDOWN (0x1) Chip select cooldown period + // 0x30000000 [29:28] PAGEBREAK (0x0) When page break is enabled, chip select will... + // 0x02000000 [25] SELECT_SETUP (0) Add up to one additional system clock cycle of setup... + // 0x01800000 [24:23] SELECT_HOLD (0x0) Add up to three additional system clock cycles of active... + // 0x007e0000 [22:17] MAX_SELECT (0x00) Enforce a maximum assertion duration for this window's... + // 0x0001f000 [16:12] MIN_DESELECT (0x00) After this window's chip select is deasserted, it... + // 0x00000700 [10:8] RXDELAY (0x0) Delay the read data sample timing, in units of one half... + // 0x000000ff [7:0] CLKDIV (0x04) Clock divisor + io_rw_32 timing; + + _REG_(QMI_M0_RFMT_OFFSET) // QMI_M0_RFMT + // Read transfer format configuration for memory address window 0. + // 0x10000000 [28] DTR (0) Enable double transfer rate (DTR) for read commands:... + // 0x00070000 [18:16] DUMMY_LEN (0x0) Length of dummy phase between command suffix and data... + // 0x0000c000 [15:14] SUFFIX_LEN (0x0) Length of post-address command suffix, in units of 4 bits + // 0x00001000 [12] PREFIX_LEN (1) Length of command prefix, in units of 8 bits + // 0x00000300 [9:8] DATA_WIDTH (0x0) The width used for the data transfer + // 0x000000c0 [7:6] DUMMY_WIDTH (0x0) The width used for the dummy phase, if any + // 0x00000030 [5:4] SUFFIX_WIDTH (0x0) The width used for the post-address command suffix, if any + // 0x0000000c [3:2] ADDR_WIDTH (0x0) The transfer width used for the address + // 0x00000003 [1:0] PREFIX_WIDTH (0x0) The transfer width used for the command prefix, if any + io_rw_32 rfmt; + + _REG_(QMI_M0_RCMD_OFFSET) // QMI_M0_RCMD + // Command constants used for reads from memory address window 0. + // 0x0000ff00 [15:8] SUFFIX (0xa0) The command suffix bits following the address, if... + // 0x000000ff [7:0] PREFIX (0x03) The command prefix bits to prepend on each new transfer,... + io_rw_32 rcmd; + + _REG_(QMI_M0_WFMT_OFFSET) // QMI_M0_WFMT + // Write transfer format configuration for memory address window 0. + // 0x10000000 [28] DTR (0) Enable double transfer rate (DTR) for write commands:... + // 0x00070000 [18:16] DUMMY_LEN (0x0) Length of dummy phase between command suffix and data... + // 0x0000c000 [15:14] SUFFIX_LEN (0x0) Length of post-address command suffix, in units of 4 bits + // 0x00001000 [12] PREFIX_LEN (1) Length of command prefix, in units of 8 bits + // 0x00000300 [9:8] DATA_WIDTH (0x0) The width used for the data transfer + // 0x000000c0 [7:6] DUMMY_WIDTH (0x0) The width used for the dummy phase, if any + // 0x00000030 [5:4] SUFFIX_WIDTH (0x0) The width used for the post-address command suffix, if any + // 0x0000000c [3:2] ADDR_WIDTH (0x0) The transfer width used for the address + // 0x00000003 [1:0] PREFIX_WIDTH (0x0) The transfer width used for the command prefix, if any + io_rw_32 wfmt; + + _REG_(QMI_M0_WCMD_OFFSET) // QMI_M0_WCMD + // Command constants used for writes to memory address window 0. + // 0x0000ff00 [15:8] SUFFIX (0xa0) The command suffix bits following the address, if... + // 0x000000ff [7:0] PREFIX (0x02) The command prefix bits to prepend on each new transfer,... + io_rw_32 wcmd; +} qmi_mem_hw_t; + +typedef struct { + _REG_(QMI_DIRECT_CSR_OFFSET) // QMI_DIRECT_CSR + // Control and status for direct serial mode + // 0xc0000000 [31:30] RXDELAY (0x0) Delay the read data sample timing, in units of one half... + // 0x3fc00000 [29:22] CLKDIV (0x06) Clock divisor for direct serial mode + // 0x001c0000 [20:18] RXLEVEL (0x0) Current level of DIRECT_RX FIFO + // 0x00020000 [17] RXFULL (0) When 1, the DIRECT_RX FIFO is currently full + // 0x00010000 [16] RXEMPTY (0) When 1, the DIRECT_RX FIFO is currently empty + // 0x00007000 [14:12] TXLEVEL (0x0) Current level of DIRECT_TX FIFO + // 0x00000800 [11] TXEMPTY (0) When 1, the DIRECT_TX FIFO is currently empty + // 0x00000400 [10] TXFULL (0) When 1, the DIRECT_TX FIFO is currently full + // 0x00000080 [7] AUTO_CS1N (0) When 1, automatically assert the CS1n chip select line... + // 0x00000040 [6] AUTO_CS0N (0) When 1, automatically assert the CS0n chip select line... + // 0x00000008 [3] ASSERT_CS1N (0) When 1, assert (i + // 0x00000004 [2] ASSERT_CS0N (0) When 1, assert (i + // 0x00000002 [1] BUSY (0) Direct mode busy flag + // 0x00000001 [0] EN (0) Enable direct mode + io_rw_32 direct_csr; + + _REG_(QMI_DIRECT_TX_OFFSET) // QMI_DIRECT_TX + // Transmit FIFO for direct mode + // 0x00100000 [20] NOPUSH (0) Inhibit the RX FIFO push that would correspond to this... + // 0x00080000 [19] OE (0) Output enable (active-high) + // 0x00040000 [18] DWIDTH (0) Data width + // 0x00030000 [17:16] IWIDTH (0x0) Configure whether this FIFO record is transferred with... + // 0x0000ffff [15:0] DATA (0x0000) Data pushed here will be clocked out falling edges of... + io_wo_32 direct_tx; + + _REG_(QMI_DIRECT_RX_OFFSET) // QMI_DIRECT_RX + // Receive FIFO for direct mode + // 0x0000ffff [15:0] DIRECT_RX (0x0000) With each byte clocked out on the serial interface, one... + io_ro_32 direct_rx; + + qmi_mem_hw_t m[2]; + + // (Description copied from array index 0 register QMI_ATRANS0 applies similarly to other array indexes) + _REG_(QMI_ATRANS0_OFFSET) // QMI_ATRANS0 + // Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB). + // 0x07ff0000 [26:16] SIZE (0x400) Translation aperture size for this virtual address... + // 0x00000fff [11:0] BASE (0x000) Physical address base for this virtual address range, in... + io_rw_32 atrans[8]; +} qmi_hw_t; + +#define qmi_hw ((qmi_hw_t *)XIP_QMI_BASE) +static_assert(sizeof (qmi_hw_t) == 0x0054, ""); + +#endif // _HARDWARE_STRUCTS_QMI_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/resets.h b/lib/pico-sdk/rp2350/hardware/structs/resets.h new file mode 100644 index 00000000..5d5d0e69 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/resets.h @@ -0,0 +1,166 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_RESETS_H +#define _HARDWARE_STRUCTS_RESETS_H + +/** + * \file rp2350/resets.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/resets.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_resets +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/resets.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/** \brief Resettable component numbers on RP2350 (used as typedef \ref reset_num_t) + * \ingroup hardware_resets + */ +typedef enum reset_num_rp2350 { + RESET_ADC = 0, ///< Select ADC to be reset + RESET_BUSCTRL = 1, ///< Select BUSCTRL to be reset + RESET_DMA = 2, ///< Select DMA to be reset + RESET_HSTX = 3, ///< Select HSTX to be reset + RESET_I2C0 = 4, ///< Select I2C0 to be reset + RESET_I2C1 = 5, ///< Select I2C1 to be reset + RESET_IO_BANK0 = 6, ///< Select IO_BANK0 to be reset + RESET_IO_QSPI = 7, ///< Select IO_QSPI to be reset + RESET_JTAG = 8, ///< Select JTAG to be reset + RESET_PADS_BANK0 = 9, ///< Select PADS_BANK0 to be reset + RESET_PADS_QSPI = 10, ///< Select PADS_QSPI to be reset + RESET_PIO0 = 11, ///< Select PIO0 to be reset + RESET_PIO1 = 12, ///< Select PIO1 to be reset + RESET_PIO2 = 13, ///< Select PIO2 to be reset + RESET_PLL_SYS = 14, ///< Select PLL_SYS to be reset + RESET_PLL_USB = 15, ///< Select PLL_USB to be reset + RESET_PWM = 16, ///< Select PWM to be reset + RESET_SHA256 = 17, ///< Select SHA256 to be reset + RESET_SPI0 = 18, ///< Select SPI0 to be reset + RESET_SPI1 = 19, ///< Select SPI1 to be reset + RESET_SYSCFG = 20, ///< Select SYSCFG to be reset + RESET_SYSINFO = 21, ///< Select SYSINFO to be reset + RESET_TBMAN = 22, ///< Select TBMAN to be reset + RESET_TIMER0 = 23, ///< Select TIMER0 to be reset + RESET_TIMER1 = 24, ///< Select TIMER1 to be reset + RESET_TRNG = 25, ///< Select TRNG to be reset + RESET_UART0 = 26, ///< Select UART0 to be reset + RESET_UART1 = 27, ///< Select UART1 to be reset + RESET_USBCTRL = 28, ///< Select USBCTRL to be reset + RESET_COUNT +} reset_num_t; + +/// \tag::resets_hw[] +typedef struct { + _REG_(RESETS_RESET_OFFSET) // RESETS_RESET + // 0x10000000 [28] USBCTRL (1) + // 0x08000000 [27] UART1 (1) + // 0x04000000 [26] UART0 (1) + // 0x02000000 [25] TRNG (1) + // 0x01000000 [24] TIMER1 (1) + // 0x00800000 [23] TIMER0 (1) + // 0x00400000 [22] TBMAN (1) + // 0x00200000 [21] SYSINFO (1) + // 0x00100000 [20] SYSCFG (1) + // 0x00080000 [19] SPI1 (1) + // 0x00040000 [18] SPI0 (1) + // 0x00020000 [17] SHA256 (1) + // 0x00010000 [16] PWM (1) + // 0x00008000 [15] PLL_USB (1) + // 0x00004000 [14] PLL_SYS (1) + // 0x00002000 [13] PIO2 (1) + // 0x00001000 [12] PIO1 (1) + // 0x00000800 [11] PIO0 (1) + // 0x00000400 [10] PADS_QSPI (1) + // 0x00000200 [9] PADS_BANK0 (1) + // 0x00000100 [8] JTAG (1) + // 0x00000080 [7] IO_QSPI (1) + // 0x00000040 [6] IO_BANK0 (1) + // 0x00000020 [5] I2C1 (1) + // 0x00000010 [4] I2C0 (1) + // 0x00000008 [3] HSTX (1) + // 0x00000004 [2] DMA (1) + // 0x00000002 [1] BUSCTRL (1) + // 0x00000001 [0] ADC (1) + io_rw_32 reset; + + _REG_(RESETS_WDSEL_OFFSET) // RESETS_WDSEL + // 0x10000000 [28] USBCTRL (0) + // 0x08000000 [27] UART1 (0) + // 0x04000000 [26] UART0 (0) + // 0x02000000 [25] TRNG (0) + // 0x01000000 [24] TIMER1 (0) + // 0x00800000 [23] TIMER0 (0) + // 0x00400000 [22] TBMAN (0) + // 0x00200000 [21] SYSINFO (0) + // 0x00100000 [20] SYSCFG (0) + // 0x00080000 [19] SPI1 (0) + // 0x00040000 [18] SPI0 (0) + // 0x00020000 [17] SHA256 (0) + // 0x00010000 [16] PWM (0) + // 0x00008000 [15] PLL_USB (0) + // 0x00004000 [14] PLL_SYS (0) + // 0x00002000 [13] PIO2 (0) + // 0x00001000 [12] PIO1 (0) + // 0x00000800 [11] PIO0 (0) + // 0x00000400 [10] PADS_QSPI (0) + // 0x00000200 [9] PADS_BANK0 (0) + // 0x00000100 [8] JTAG (0) + // 0x00000080 [7] IO_QSPI (0) + // 0x00000040 [6] IO_BANK0 (0) + // 0x00000020 [5] I2C1 (0) + // 0x00000010 [4] I2C0 (0) + // 0x00000008 [3] HSTX (0) + // 0x00000004 [2] DMA (0) + // 0x00000002 [1] BUSCTRL (0) + // 0x00000001 [0] ADC (0) + io_rw_32 wdsel; + + _REG_(RESETS_RESET_DONE_OFFSET) // RESETS_RESET_DONE + // 0x10000000 [28] USBCTRL (0) + // 0x08000000 [27] UART1 (0) + // 0x04000000 [26] UART0 (0) + // 0x02000000 [25] TRNG (0) + // 0x01000000 [24] TIMER1 (0) + // 0x00800000 [23] TIMER0 (0) + // 0x00400000 [22] TBMAN (0) + // 0x00200000 [21] SYSINFO (0) + // 0x00100000 [20] SYSCFG (0) + // 0x00080000 [19] SPI1 (0) + // 0x00040000 [18] SPI0 (0) + // 0x00020000 [17] SHA256 (0) + // 0x00010000 [16] PWM (0) + // 0x00008000 [15] PLL_USB (0) + // 0x00004000 [14] PLL_SYS (0) + // 0x00002000 [13] PIO2 (0) + // 0x00001000 [12] PIO1 (0) + // 0x00000800 [11] PIO0 (0) + // 0x00000400 [10] PADS_QSPI (0) + // 0x00000200 [9] PADS_BANK0 (0) + // 0x00000100 [8] JTAG (0) + // 0x00000080 [7] IO_QSPI (0) + // 0x00000040 [6] IO_BANK0 (0) + // 0x00000020 [5] I2C1 (0) + // 0x00000010 [4] I2C0 (0) + // 0x00000008 [3] HSTX (0) + // 0x00000004 [2] DMA (0) + // 0x00000002 [1] BUSCTRL (0) + // 0x00000001 [0] ADC (0) + io_ro_32 reset_done; +} resets_hw_t; +/// \end::resets_hw[] + +#define resets_hw ((resets_hw_t *)RESETS_BASE) +static_assert(sizeof (resets_hw_t) == 0x000c, ""); + +#endif // _HARDWARE_STRUCTS_RESETS_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/rosc.h b/lib/pico-sdk/rp2350/hardware/structs/rosc.h new file mode 100644 index 00000000..73503cc1 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/rosc.h @@ -0,0 +1,99 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_ROSC_H +#define _HARDWARE_STRUCTS_ROSC_H + +/** + * \file rp2350/rosc.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/rosc.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_rosc +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/rosc.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(ROSC_CTRL_OFFSET) // ROSC_CTRL + // Ring Oscillator control + // 0x00fff000 [23:12] ENABLE (-) On power-up this field is initialised to ENABLE + + // 0x00000fff [11:0] FREQ_RANGE (0xaa0) Controls the number of delay stages in the ROSC ring + + io_rw_32 ctrl; + + _REG_(ROSC_FREQA_OFFSET) // ROSC_FREQA + // Ring Oscillator frequency control A + // 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings + + // 0x00007000 [14:12] DS3 (0x0) Stage 3 drive strength + // 0x00000700 [10:8] DS2 (0x0) Stage 2 drive strength + // 0x00000080 [7] DS1_RANDOM (0) Randomises the stage 1 drive strength + // 0x00000070 [6:4] DS1 (0x0) Stage 1 drive strength + // 0x00000008 [3] DS0_RANDOM (0) Randomises the stage 0 drive strength + // 0x00000007 [2:0] DS0 (0x0) Stage 0 drive strength + io_rw_32 freqa; + + _REG_(ROSC_FREQB_OFFSET) // ROSC_FREQB + // Ring Oscillator frequency control B + // 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings + + // 0x00007000 [14:12] DS7 (0x0) Stage 7 drive strength + // 0x00000700 [10:8] DS6 (0x0) Stage 6 drive strength + // 0x00000070 [6:4] DS5 (0x0) Stage 5 drive strength + // 0x00000007 [2:0] DS4 (0x0) Stage 4 drive strength + io_rw_32 freqb; + + _REG_(ROSC_RANDOM_OFFSET) // ROSC_RANDOM + // Loads a value to the LFSR randomiser + // 0xffffffff [31:0] SEED (0x3f04b16d) + io_rw_32 random; + + _REG_(ROSC_DORMANT_OFFSET) // ROSC_DORMANT + // Ring Oscillator pause control + // 0xffffffff [31:0] DORMANT (-) This is used to save power by pausing the ROSC + + io_rw_32 dormant; + + _REG_(ROSC_DIV_OFFSET) // ROSC_DIV + // Controls the output divider + // 0x0000ffff [15:0] DIV (-) set to 0xaa00 + div where + + io_rw_32 div; + + _REG_(ROSC_PHASE_OFFSET) // ROSC_PHASE + // Controls the phase shifted output + // 0x00000ff0 [11:4] PASSWD (0x00) set to 0xaa + + // 0x00000008 [3] ENABLE (1) enable the phase-shifted output + + // 0x00000004 [2] FLIP (0) invert the phase-shifted output + + // 0x00000003 [1:0] SHIFT (0x0) phase shift the phase-shifted output by SHIFT input clocks + + io_rw_32 phase; + + _REG_(ROSC_STATUS_OFFSET) // ROSC_STATUS + // Ring Oscillator Status + // 0x80000000 [31] STABLE (0) Oscillator is running and stable + // 0x01000000 [24] BADWRITE (0) An invalid value has been written to CTRL_ENABLE or... + // 0x00010000 [16] DIV_RUNNING (-) post-divider is running + + // 0x00001000 [12] ENABLED (-) Oscillator is enabled but not necessarily running and stable + + io_rw_32 status; + + _REG_(ROSC_RANDOMBIT_OFFSET) // ROSC_RANDOMBIT + // Returns a 1 bit random value + // 0x00000001 [0] RANDOMBIT (1) + io_ro_32 randombit; + + _REG_(ROSC_COUNT_OFFSET) // ROSC_COUNT + // A down counter running at the ROSC frequency which counts to zero and stops. + // 0x0000ffff [15:0] COUNT (0x0000) + io_rw_32 count; +} rosc_hw_t; + +#define rosc_hw ((rosc_hw_t *)ROSC_BASE) +static_assert(sizeof (rosc_hw_t) == 0x0028, ""); + +#endif // _HARDWARE_STRUCTS_ROSC_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/sau.h b/lib/pico-sdk/rp2350/hardware/structs/sau.h new file mode 100644 index 00000000..803f3563 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/sau.h @@ -0,0 +1,65 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SAU_H +#define _HARDWARE_STRUCTS_SAU_H + +/** + * \file rp2350/sau.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/m33.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m33.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV +#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" +#endif + +typedef struct { + _REG_(M33_SAU_CTRL_OFFSET) // M33_SAU_CTRL + // Allows enabling of the Security Attribution Unit + // 0x00000002 [1] ALLNS (0) When SAU_CTRL + // 0x00000001 [0] ENABLE (0) Enables the SAU + io_rw_32 ctrl; + + _REG_(M33_SAU_TYPE_OFFSET) // M33_SAU_TYPE + // Indicates the number of regions implemented by the Security Attribution Unit + // 0x000000ff [7:0] SREGION (0x08) The number of implemented SAU regions + io_ro_32 type; + + _REG_(M33_SAU_RNR_OFFSET) // M33_SAU_RNR + // Selects the region currently accessed by SAU_RBAR and SAU_RLAR + // 0x000000ff [7:0] REGION (0x00) Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR + io_rw_32 rnr; + + _REG_(M33_SAU_RBAR_OFFSET) // M33_SAU_RBAR + // Provides indirect read and write access to the base address of the currently selected SAU region + // 0xffffffe0 [31:5] BADDR (0x0000000) Holds bits [31:5] of the base address for the selected SAU region + io_rw_32 rbar; + + _REG_(M33_SAU_RLAR_OFFSET) // M33_SAU_RLAR + // Provides indirect read and write access to the limit address of the currently selected SAU region + // 0xffffffe0 [31:5] LADDR (0x0000000) Holds bits [31:5] of the limit address for the selected... + // 0x00000002 [1] NSC (0) Controls whether Non-secure state is permitted to... + // 0x00000001 [0] ENABLE (0) SAU region enable + io_rw_32 rlar; +} armv8m_sau_hw_t; + +#define sau_hw ((armv8m_sau_hw_t *)(PPB_BASE + M33_SAU_CTRL_OFFSET)) +#define sau_ns_hw ((armv8m_sau_hw_t *)(PPB_NONSEC_BASE + M33_SAU_CTRL_OFFSET)) +static_assert(sizeof (armv8m_sau_hw_t) == 0x0014, ""); + +#endif // _HARDWARE_STRUCTS_SAU_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/scb.h b/lib/pico-sdk/rp2350/hardware/structs/scb.h new file mode 100644 index 00000000..9777023d --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/scb.h @@ -0,0 +1,264 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SCB_H +#define _HARDWARE_STRUCTS_SCB_H + +/** + * \file rp2350/scb.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/m33.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m33.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV +#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" +#endif + +typedef struct { + _REG_(M33_CPUID_OFFSET) // M33_CPUID + // Provides identification information for the PE, including an implementer code for the device and... + // 0xff000000 [31:24] IMPLEMENTER (0x41) This field must hold an implementer code that has been... + // 0x00f00000 [23:20] VARIANT (0x1) IMPLEMENTATION DEFINED variant number + // 0x000f0000 [19:16] ARCHITECTURE (0xf) Defines the Architecture implemented by the PE + // 0x0000fff0 [15:4] PARTNO (0xd21) IMPLEMENTATION DEFINED primary part number for the device + // 0x0000000f [3:0] REVISION (0x0) IMPLEMENTATION DEFINED revision number for the device + io_ro_32 cpuid; + + _REG_(M33_ICSR_OFFSET) // M33_ICSR + // Controls and provides status information for NMI, PendSV, SysTick and interrupts + // 0x80000000 [31] PENDNMISET (0) Indicates whether the NMI exception is pending + // 0x40000000 [30] PENDNMICLR (0) Allows the NMI exception pend state to be cleared + // 0x10000000 [28] PENDSVSET (0) Indicates whether the PendSV `FTSSS exception is pending + // 0x08000000 [27] PENDSVCLR (0) Allows the PendSV exception pend state to be cleared `FTSSS + // 0x04000000 [26] PENDSTSET (0) Indicates whether the SysTick `FTSSS exception is pending + // 0x02000000 [25] PENDSTCLR (0) Allows the SysTick exception pend state to be cleared `FTSSS + // 0x01000000 [24] STTNS (0) Controls whether in a single SysTick implementation, the... + // 0x00800000 [23] ISRPREEMPT (0) Indicates whether a pending exception will be serviced... + // 0x00400000 [22] ISRPENDING (0) Indicates whether an external interrupt, generated by... + // 0x001ff000 [20:12] VECTPENDING (0x000) The exception number of the highest priority pending and... + // 0x00000800 [11] RETTOBASE (0) In Handler mode, indicates whether there is more than... + // 0x000001ff [8:0] VECTACTIVE (0x000) The exception number of the current executing exception + io_rw_32 icsr; + + _REG_(M33_VTOR_OFFSET) // M33_VTOR + // Vector Table Offset Register + // 0xffffff80 [31:7] TBLOFF (0x0000000) Vector table base offset field + io_rw_32 vtor; + + _REG_(M33_AIRCR_OFFSET) // M33_AIRCR + // Application Interrupt and Reset Control Register + // 0xffff0000 [31:16] VECTKEY (0x0000) Register key: + + // 0x00008000 [15] ENDIANESS (0) Data endianness implemented: + + // 0x00004000 [14] PRIS (0) Prioritize Secure exceptions + // 0x00002000 [13] BFHFNMINS (0) BusFault, HardFault, and NMI Non-secure enable + // 0x00000700 [10:8] PRIGROUP (0x0) Interrupt priority grouping field + // 0x00000008 [3] SYSRESETREQS (0) System reset request, Secure state only + // 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to... + // 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and... + io_rw_32 aircr; + + _REG_(M33_SCR_OFFSET) // M33_SCR + // System Control Register + // 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: + + // 0x00000008 [3] SLEEPDEEPS (0) 0 SLEEPDEEP is available to both security states + + // 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep... + // 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode... + io_rw_32 scr; + + _REG_(M33_CCR_OFFSET) // M33_CCR + // Sets or returns configuration and control data + // 0x00040000 [18] BP (0) Enables program flow prediction `FTSSS + // 0x00020000 [17] IC (0) This is a global enable bit for instruction caches in... + // 0x00010000 [16] DC (0) Enables data caching of all data accesses to Normal memory `FTSSS + // 0x00000400 [10] STKOFHFNMIGN (0) Controls the effect of a stack limit violation while... + // 0x00000200 [9] RES1 (1) Reserved, RES1 + // 0x00000100 [8] BFHFNMIGN (0) Determines the effect of precise BusFaults on handlers... + // 0x00000010 [4] DIV_0_TRP (0) Controls the generation of a DIVBYZERO UsageFault when... + // 0x00000008 [3] UNALIGN_TRP (0) Controls the trapping of unaligned word or halfword accesses + // 0x00000002 [1] USERSETMPEND (0) Determines whether unprivileged accesses are permitted... + // 0x00000001 [0] RES1_1 (1) Reserved, RES1 + io_rw_32 ccr; + + // (Description copied from array index 0 register M33_SHPR1 applies similarly to other array indexes) + _REG_(M33_SHPR1_OFFSET) // M33_SHPR1 + // Sets or returns priority for system handlers 4 - 7 + // 0xe0000000 [31:29] PRI_7_3 (0x0) Priority of system handler 7, SecureFault + // 0x00e00000 [23:21] PRI_6_3 (0x0) Priority of system handler 6, SecureFault + // 0x0000e000 [15:13] PRI_5_3 (0x0) Priority of system handler 5, SecureFault + // 0x000000e0 [7:5] PRI_4_3 (0x0) Priority of system handler 4, SecureFault + io_rw_32 shpr[3]; + + _REG_(M33_SHCSR_OFFSET) // M33_SHCSR + // Provides access to the active and pending status of system exceptions + // 0x00200000 [21] HARDFAULTPENDED (0) `IAAMO the pending state of the HardFault exception `CTTSSS + // 0x00100000 [20] SECUREFAULTPENDED (0) `IAAMO the pending state of the SecureFault exception + // 0x00080000 [19] SECUREFAULTENA (0) `DW the SecureFault exception is enabled + // 0x00040000 [18] USGFAULTENA (0) `DW the UsageFault exception is enabled `FTSSS + // 0x00020000 [17] BUSFAULTENA (0) `DW the BusFault exception is enabled + // 0x00010000 [16] MEMFAULTENA (0) `DW the MemManage exception is enabled `FTSSS + // 0x00008000 [15] SVCALLPENDED (0) `IAAMO the pending state of the SVCall exception `FTSSS + // 0x00004000 [14] BUSFAULTPENDED (0) `IAAMO the pending state of the BusFault exception + // 0x00002000 [13] MEMFAULTPENDED (0) `IAAMO the pending state of the MemManage exception `FTSSS + // 0x00001000 [12] USGFAULTPENDED (0) The UsageFault exception is banked between Security... + // 0x00000800 [11] SYSTICKACT (0) `IAAMO the active state of the SysTick exception `FTSSS + // 0x00000400 [10] PENDSVACT (0) `IAAMO the active state of the PendSV exception `FTSSS + // 0x00000100 [8] MONITORACT (0) `IAAMO the active state of the DebugMonitor exception + // 0x00000080 [7] SVCALLACT (0) `IAAMO the active state of the SVCall exception `FTSSS + // 0x00000020 [5] NMIACT (0) `IAAMO the active state of the NMI exception + // 0x00000010 [4] SECUREFAULTACT (0) `IAAMO the active state of the SecureFault exception + // 0x00000008 [3] USGFAULTACT (0) `IAAMO the active state of the UsageFault exception `FTSSS + // 0x00000004 [2] HARDFAULTACT (0) Indicates and allows limited modification of the active... + // 0x00000002 [1] BUSFAULTACT (0) `IAAMO the active state of the BusFault exception + // 0x00000001 [0] MEMFAULTACT (0) `IAAMO the active state of the MemManage exception `FTSSS + io_rw_32 shcsr; + + _REG_(M33_CFSR_OFFSET) // M33_CFSR + // Contains the three Configurable Fault Status Registers + // 0x02000000 [25] UFSR_DIVBYZERO (0) Sticky flag indicating whether an integer division by... + // 0x01000000 [24] UFSR_UNALIGNED (0) Sticky flag indicating whether an unaligned access error... + // 0x00100000 [20] UFSR_STKOF (0) Sticky flag indicating whether a stack overflow error... + // 0x00080000 [19] UFSR_NOCP (0) Sticky flag indicating whether a coprocessor disabled or... + // 0x00040000 [18] UFSR_INVPC (0) Sticky flag indicating whether an integrity check error... + // 0x00020000 [17] UFSR_INVSTATE (0) Sticky flag indicating whether an EPSR + // 0x00010000 [16] UFSR_UNDEFINSTR (0) Sticky flag indicating whether an undefined instruction... + // 0x00008000 [15] BFSR_BFARVALID (0) Indicates validity of the contents of the BFAR register + // 0x00002000 [13] BFSR_LSPERR (0) Records whether a BusFault occurred during FP lazy state... + // 0x00001000 [12] BFSR_STKERR (0) Records whether a derived BusFault occurred during... + // 0x00000800 [11] BFSR_UNSTKERR (0) Records whether a derived BusFault occurred during... + // 0x00000400 [10] BFSR_IMPRECISERR (0) Records whether an imprecise data access error has occurred + // 0x00000200 [9] BFSR_PRECISERR (0) Records whether a precise data access error has occurred + // 0x00000100 [8] BFSR_IBUSERR (0) Records whether a BusFault on an instruction prefetch... + // 0x000000ff [7:0] MMFSR (0x00) Provides information on MemManage exceptions + io_rw_32 cfsr; + + _REG_(M33_HFSR_OFFSET) // M33_HFSR + // Shows the cause of any HardFaults + // 0x80000000 [31] DEBUGEVT (0) Indicates when a Debug event has occurred + // 0x40000000 [30] FORCED (0) Indicates that a fault with configurable priority has... + // 0x00000002 [1] VECTTBL (0) Indicates when a fault has occurred because of a vector... + io_rw_32 hfsr; + + _REG_(M33_DFSR_OFFSET) // M33_DFSR + // Shows which debug event occurred + // 0x00000010 [4] EXTERNAL (0) Sticky flag indicating whether an External debug request... + // 0x00000008 [3] VCATCH (0) Sticky flag indicating whether a Vector catch debug... + // 0x00000004 [2] DWTTRAP (0) Sticky flag indicating whether a Watchpoint debug event... + // 0x00000002 [1] BKPT (0) Sticky flag indicating whether a Breakpoint debug event... + // 0x00000001 [0] HALTED (0) Sticky flag indicating that a Halt request debug event... + io_rw_32 dfsr; + + _REG_(M33_MMFAR_OFFSET) // M33_MMFAR + // Shows the address of the memory location that caused an MPU fault + // 0xffffffff [31:0] ADDRESS (0x00000000) This register is updated with the address of a location... + io_rw_32 mmfar; + + _REG_(M33_BFAR_OFFSET) // M33_BFAR + // Shows the address associated with a precise data access BusFault + // 0xffffffff [31:0] ADDRESS (0x00000000) This register is updated with the address of a location... + io_rw_32 bfar; + + uint32_t _pad0; + + // (Description copied from array index 0 register M33_ID_PFR0 applies similarly to other array indexes) + _REG_(M33_ID_PFR0_OFFSET) // M33_ID_PFR0 + // Gives top-level information about the instruction set supported by the PE + // 0x000000f0 [7:4] STATE1 (0x3) T32 instruction set support + // 0x0000000f [3:0] STATE0 (0x0) A32 instruction set support + io_ro_32 id_pfr[2]; + + _REG_(M33_ID_DFR0_OFFSET) // M33_ID_DFR0 + // Provides top level information about the debug system + // 0x00f00000 [23:20] MPROFDBG (0x2) Indicates the supported M-profile debug architecture + io_ro_32 id_dfr0; + + _REG_(M33_ID_AFR0_OFFSET) // M33_ID_AFR0 + // Provides information about the IMPLEMENTATION DEFINED features of the PE + // 0x0000f000 [15:12] IMPDEF3 (0x0) IMPLEMENTATION DEFINED meaning + // 0x00000f00 [11:8] IMPDEF2 (0x0) IMPLEMENTATION DEFINED meaning + // 0x000000f0 [7:4] IMPDEF1 (0x0) IMPLEMENTATION DEFINED meaning + // 0x0000000f [3:0] IMPDEF0 (0x0) IMPLEMENTATION DEFINED meaning + io_ro_32 id_afr0; + + // (Description copied from array index 0 register M33_ID_MMFR0 applies similarly to other array indexes) + _REG_(M33_ID_MMFR0_OFFSET) // M33_ID_MMFR0 + // Provides information about the implemented memory model and memory management support + // 0x00f00000 [23:20] AUXREG (0x1) Indicates support for Auxiliary Control Registers + // 0x000f0000 [19:16] TCM (0x0) Indicates support for tightly coupled memories (TCMs) + // 0x0000f000 [15:12] SHARELVL (0x1) Indicates the number of shareability levels implemented + // 0x00000f00 [11:8] OUTERSHR (0xf) Indicates the outermost shareability domain implemented + // 0x000000f0 [7:4] PMSA (0x4) Indicates support for the protected memory system... + io_ro_32 id_mmfr[4]; + + // (Description copied from array index 0 register M33_ID_ISAR0 applies similarly to other array indexes) + _REG_(M33_ID_ISAR0_OFFSET) // M33_ID_ISAR0 + // Provides information about the instruction set implemented by the PE + // 0x0f000000 [27:24] DIVIDE (0x8) Indicates the supported Divide instructions + // 0x00f00000 [23:20] DEBUG (0x0) Indicates the implemented Debug instructions + // 0x000f0000 [19:16] COPROC (0x9) Indicates the supported Coprocessor instructions + // 0x0000f000 [15:12] CMPBRANCH (0x2) Indicates the supported combined Compare and Branch instructions + // 0x00000f00 [11:8] BITFIELD (0x3) Indicates the supported bit field instructions + // 0x000000f0 [7:4] BITCOUNT (0x0) Indicates the supported bit count instructions + io_ro_32 id_isar[6]; + + uint32_t _pad1; + + _REG_(M33_CTR_OFFSET) // M33_CTR + // Provides information about the architecture of the caches + // 0x80000000 [31] RES1 (1) Reserved, RES1 + // 0x0f000000 [27:24] CWG (0x0) Log2 of the number of words of the maximum size of... + // 0x00f00000 [23:20] ERG (0x0) Log2 of the number of words of the maximum size of the... + // 0x000f0000 [19:16] DMINLINE (0x0) Log2 of the number of words in the smallest cache line... + // 0x0000c000 [15:14] RES1_1 (0x3) Reserved, RES1 + // 0x0000000f [3:0] IMINLINE (0x0) Log2 of the number of words in the smallest cache line... + io_ro_32 ctr; + + uint32_t _pad2[2]; + + _REG_(M33_CPACR_OFFSET) // M33_CPACR + // Specifies the access privileges for coprocessors and the FP Extension + // 0x00c00000 [23:22] CP11 (0x0) The value in this field is ignored + // 0x00300000 [21:20] CP10 (0x0) Defines the access rights for the floating-point functionality + // 0x0000c000 [15:14] CP7 (0x0) Controls access privileges for coprocessor 7 + // 0x00003000 [13:12] CP6 (0x0) Controls access privileges for coprocessor 6 + // 0x00000c00 [11:10] CP5 (0x0) Controls access privileges for coprocessor 5 + // 0x00000300 [9:8] CP4 (0x0) Controls access privileges for coprocessor 4 + // 0x000000c0 [7:6] CP3 (0x0) Controls access privileges for coprocessor 3 + // 0x00000030 [5:4] CP2 (0x0) Controls access privileges for coprocessor 2 + // 0x0000000c [3:2] CP1 (0x0) Controls access privileges for coprocessor 1 + // 0x00000003 [1:0] CP0 (0x0) Controls access privileges for coprocessor 0 + io_rw_32 cpacr; + + _REG_(M33_NSACR_OFFSET) // M33_NSACR + // Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7 + // 0x00000800 [11] CP11 (0) Enables Non-secure access to the Floating-point Extension + // 0x00000400 [10] CP10 (0) Enables Non-secure access to the Floating-point Extension + // 0x00000080 [7] CP7 (0) Enables Non-secure access to coprocessor CP7 + // 0x00000040 [6] CP6 (0) Enables Non-secure access to coprocessor CP6 + // 0x00000020 [5] CP5 (0) Enables Non-secure access to coprocessor CP5 + // 0x00000010 [4] CP4 (0) Enables Non-secure access to coprocessor CP4 + // 0x00000008 [3] CP3 (0) Enables Non-secure access to coprocessor CP3 + // 0x00000004 [2] CP2 (0) Enables Non-secure access to coprocessor CP2 + // 0x00000002 [1] CP1 (0) Enables Non-secure access to coprocessor CP1 + // 0x00000001 [0] CP0 (0) Enables Non-secure access to coprocessor CP0 + io_rw_32 nsacr; +} armv8m_scb_hw_t; + +#define scb_hw ((armv8m_scb_hw_t *)(PPB_BASE + M33_CPUID_OFFSET)) +#define scb_ns_hw ((armv8m_scb_hw_t *)(PPB_NONSEC_BASE + M33_CPUID_OFFSET)) +static_assert(sizeof (armv8m_scb_hw_t) == 0x0090, ""); + +#endif // _HARDWARE_STRUCTS_SCB_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/sha256.h b/lib/pico-sdk/rp2350/hardware/structs/sha256.h new file mode 100644 index 00000000..248a00ab --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/sha256.h @@ -0,0 +1,53 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SHA256_H +#define _HARDWARE_STRUCTS_SHA256_H + +/** + * \file rp2350/sha256.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/sha256.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sha256 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/sha256.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(SHA256_CSR_OFFSET) // SHA256_CSR + // Control and status register + // 0x00001000 [12] BSWAP (1) Enable byte swapping of 32-bit values at the point they... + // 0x00000300 [9:8] DMA_SIZE (0x2) Configure DREQ logic for the correct DMA data size + // 0x00000010 [4] ERR_WDATA_NOT_RDY (0) Set when a write occurs whilst the SHA-256 core is not... + // 0x00000004 [2] SUM_VLD (1) If 1, the SHA-256 checksum presented in registers SUM0... + // 0x00000002 [1] WDATA_RDY (1) If 1, the SHA-256 core is ready to accept more data... + // 0x00000001 [0] START (0) Write 1 to prepare the SHA-256 core for a new checksum + io_rw_32 csr; + + _REG_(SHA256_WDATA_OFFSET) // SHA256_WDATA + // Write data register + // 0xffffffff [31:0] WDATA (0x00000000) After pulsing START and writing 16 words of data to this... + io_wo_32 wdata; + + // (Description copied from array index 0 register SHA256_SUM0 applies similarly to other array indexes) + _REG_(SHA256_SUM0_OFFSET) // SHA256_SUM0 + // 256-bit checksum result + // 0xffffffff [31:0] SUM0 (0x00000000) + io_ro_32 sum[8]; +} sha256_hw_t; + +#define sha256_hw ((sha256_hw_t *)SHA256_BASE) +static_assert(sizeof (sha256_hw_t) == 0x0028, ""); + +#endif // _HARDWARE_STRUCTS_SHA256_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/sio.h b/lib/pico-sdk/rp2350/hardware/structs/sio.h new file mode 100644 index 00000000..49a452c8 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/sio.h @@ -0,0 +1,336 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SIO_H +#define _HARDWARE_STRUCTS_SIO_H + +/** + * \file rp2350/sio.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/sio.h" +#include "hardware/structs/interp.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sio +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/sio.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + + +typedef struct { + _REG_(SIO_CPUID_OFFSET) // SIO_CPUID + // Processor core identifier + // 0xffffffff [31:0] CPUID (-) Value is 0 when read from processor core 0, and 1 when... + io_ro_32 cpuid; + + _REG_(SIO_GPIO_IN_OFFSET) // SIO_GPIO_IN + // Input value for GPIO0 + // 0xffffffff [31:0] GPIO_IN (0x00000000) + io_ro_32 gpio_in; + + _REG_(SIO_GPIO_HI_IN_OFFSET) // SIO_GPIO_HI_IN + // Input value on GPIO32 + // 0xf0000000 [31:28] QSPI_SD (0x0) Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins + // 0x08000000 [27] QSPI_CSN (0) Input value on QSPI CSn pin + // 0x04000000 [26] QSPI_SCK (0) Input value on QSPI SCK pin + // 0x02000000 [25] USB_DM (0) Input value on USB D- pin + // 0x01000000 [24] USB_DP (0) Input value on USB D+ pin + // 0x0000ffff [15:0] GPIO (0x0000) Input value on GPIO32 + io_ro_32 gpio_hi_in; + + uint32_t _pad0; + + _REG_(SIO_GPIO_OUT_OFFSET) // SIO_GPIO_OUT + // GPIO0 + // 0xffffffff [31:0] GPIO_OUT (0x00000000) Set output level (1/0 -> high/low) for GPIO0 + io_rw_32 gpio_out; + + _REG_(SIO_GPIO_HI_OUT_OFFSET) // SIO_GPIO_HI_OUT + // Output value for GPIO32 + // 0xf0000000 [31:28] QSPI_SD (0x0) Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins + // 0x08000000 [27] QSPI_CSN (0) Output value for QSPI CSn pin + // 0x04000000 [26] QSPI_SCK (0) Output value for QSPI SCK pin + // 0x02000000 [25] USB_DM (0) Output value for USB D- pin + // 0x01000000 [24] USB_DP (0) Output value for USB D+ pin + // 0x0000ffff [15:0] GPIO (0x0000) Output value for GPIO32 + io_rw_32 gpio_hi_out; + + _REG_(SIO_GPIO_OUT_SET_OFFSET) // SIO_GPIO_OUT_SET + // GPIO0 + // 0xffffffff [31:0] GPIO_OUT_SET (0x00000000) Perform an atomic bit-set on GPIO_OUT, i + io_wo_32 gpio_set; + + _REG_(SIO_GPIO_HI_OUT_SET_OFFSET) // SIO_GPIO_HI_OUT_SET + // Output value set for GPIO32 + // 0xf0000000 [31:28] QSPI_SD (0x0) + // 0x08000000 [27] QSPI_CSN (0) + // 0x04000000 [26] QSPI_SCK (0) + // 0x02000000 [25] USB_DM (0) + // 0x01000000 [24] USB_DP (0) + // 0x0000ffff [15:0] GPIO (0x0000) + io_wo_32 gpio_hi_set; + + _REG_(SIO_GPIO_OUT_CLR_OFFSET) // SIO_GPIO_OUT_CLR + // GPIO0 + // 0xffffffff [31:0] GPIO_OUT_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OUT, i + io_wo_32 gpio_clr; + + _REG_(SIO_GPIO_HI_OUT_CLR_OFFSET) // SIO_GPIO_HI_OUT_CLR + // Output value clear for GPIO32 + // 0xf0000000 [31:28] QSPI_SD (0x0) + // 0x08000000 [27] QSPI_CSN (0) + // 0x04000000 [26] QSPI_SCK (0) + // 0x02000000 [25] USB_DM (0) + // 0x01000000 [24] USB_DP (0) + // 0x0000ffff [15:0] GPIO (0x0000) + io_wo_32 gpio_hi_clr; + + _REG_(SIO_GPIO_OUT_XOR_OFFSET) // SIO_GPIO_OUT_XOR + // GPIO0 + // 0xffffffff [31:0] GPIO_OUT_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OUT, i + io_wo_32 gpio_togl; + + _REG_(SIO_GPIO_HI_OUT_XOR_OFFSET) // SIO_GPIO_HI_OUT_XOR + // Output value XOR for GPIO32 + // 0xf0000000 [31:28] QSPI_SD (0x0) + // 0x08000000 [27] QSPI_CSN (0) + // 0x04000000 [26] QSPI_SCK (0) + // 0x02000000 [25] USB_DM (0) + // 0x01000000 [24] USB_DP (0) + // 0x0000ffff [15:0] GPIO (0x0000) + io_wo_32 gpio_hi_togl; + + _REG_(SIO_GPIO_OE_OFFSET) // SIO_GPIO_OE + // GPIO0 + // 0xffffffff [31:0] GPIO_OE (0x00000000) Set output enable (1/0 -> output/input) for GPIO0 + io_rw_32 gpio_oe; + + _REG_(SIO_GPIO_HI_OE_OFFSET) // SIO_GPIO_HI_OE + // Output enable value for GPIO32 + // 0xf0000000 [31:28] QSPI_SD (0x0) Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2... + // 0x08000000 [27] QSPI_CSN (0) Output enable value for QSPI CSn pin + // 0x04000000 [26] QSPI_SCK (0) Output enable value for QSPI SCK pin + // 0x02000000 [25] USB_DM (0) Output enable value for USB D- pin + // 0x01000000 [24] USB_DP (0) Output enable value for USB D+ pin + // 0x0000ffff [15:0] GPIO (0x0000) Output enable value for GPIO32 + io_rw_32 gpio_hi_oe; + + _REG_(SIO_GPIO_OE_SET_OFFSET) // SIO_GPIO_OE_SET + // GPIO0 + // 0xffffffff [31:0] GPIO_OE_SET (0x00000000) Perform an atomic bit-set on GPIO_OE, i + io_wo_32 gpio_oe_set; + + _REG_(SIO_GPIO_HI_OE_SET_OFFSET) // SIO_GPIO_HI_OE_SET + // Output enable set for GPIO32 + // 0xf0000000 [31:28] QSPI_SD (0x0) + // 0x08000000 [27] QSPI_CSN (0) + // 0x04000000 [26] QSPI_SCK (0) + // 0x02000000 [25] USB_DM (0) + // 0x01000000 [24] USB_DP (0) + // 0x0000ffff [15:0] GPIO (0x0000) + io_wo_32 gpio_hi_oe_set; + + _REG_(SIO_GPIO_OE_CLR_OFFSET) // SIO_GPIO_OE_CLR + // GPIO0 + // 0xffffffff [31:0] GPIO_OE_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OE, i + io_wo_32 gpio_oe_clr; + + _REG_(SIO_GPIO_HI_OE_CLR_OFFSET) // SIO_GPIO_HI_OE_CLR + // Output enable clear for GPIO32 + // 0xf0000000 [31:28] QSPI_SD (0x0) + // 0x08000000 [27] QSPI_CSN (0) + // 0x04000000 [26] QSPI_SCK (0) + // 0x02000000 [25] USB_DM (0) + // 0x01000000 [24] USB_DP (0) + // 0x0000ffff [15:0] GPIO (0x0000) + io_wo_32 gpio_hi_oe_clr; + + _REG_(SIO_GPIO_OE_XOR_OFFSET) // SIO_GPIO_OE_XOR + // GPIO0 + // 0xffffffff [31:0] GPIO_OE_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OE, i + io_wo_32 gpio_oe_togl; + + _REG_(SIO_GPIO_HI_OE_XOR_OFFSET) // SIO_GPIO_HI_OE_XOR + // Output enable XOR for GPIO32 + // 0xf0000000 [31:28] QSPI_SD (0x0) + // 0x08000000 [27] QSPI_CSN (0) + // 0x04000000 [26] QSPI_SCK (0) + // 0x02000000 [25] USB_DM (0) + // 0x01000000 [24] USB_DP (0) + // 0x0000ffff [15:0] GPIO (0x0000) + io_wo_32 gpio_hi_oe_togl; + + _REG_(SIO_FIFO_ST_OFFSET) // SIO_FIFO_ST + // Status register for inter-core FIFOs (mailboxes). + // 0x00000008 [3] ROE (0) Sticky flag indicating the RX FIFO was read when empty + // 0x00000004 [2] WOF (0) Sticky flag indicating the TX FIFO was written when full + // 0x00000002 [1] RDY (1) Value is 1 if this core's TX FIFO is not full (i + // 0x00000001 [0] VLD (0) Value is 1 if this core's RX FIFO is not empty (i + io_rw_32 fifo_st; + + _REG_(SIO_FIFO_WR_OFFSET) // SIO_FIFO_WR + // Write access to this core's TX FIFO + // 0xffffffff [31:0] FIFO_WR (0x00000000) + io_wo_32 fifo_wr; + + _REG_(SIO_FIFO_RD_OFFSET) // SIO_FIFO_RD + // Read access to this core's RX FIFO + // 0xffffffff [31:0] FIFO_RD (-) + io_ro_32 fifo_rd; + + _REG_(SIO_SPINLOCK_ST_OFFSET) // SIO_SPINLOCK_ST + // Spinlock state + // 0xffffffff [31:0] SPINLOCK_ST (0x00000000) + io_ro_32 spinlock_st; + + uint32_t _pad1[8]; + + interp_hw_t interp[2]; + + // (Description copied from array index 0 register SIO_SPINLOCK0 applies similarly to other array indexes) + _REG_(SIO_SPINLOCK0_OFFSET) // SIO_SPINLOCK0 + // Spinlock register 0 + // 0xffffffff [31:0] SPINLOCK0 (0x00000000) + io_rw_32 spinlock[32]; + + _REG_(SIO_DOORBELL_OUT_SET_OFFSET) // SIO_DOORBELL_OUT_SET + // Trigger a doorbell interrupt on the opposite core + // 0x000000ff [7:0] DOORBELL_OUT_SET (0x00) + io_rw_32 doorbell_out_set; + + _REG_(SIO_DOORBELL_OUT_CLR_OFFSET) // SIO_DOORBELL_OUT_CLR + // Clear doorbells which have been posted to the opposite core + // 0x000000ff [7:0] DOORBELL_OUT_CLR (0x00) + io_rw_32 doorbell_out_clr; + + _REG_(SIO_DOORBELL_IN_SET_OFFSET) // SIO_DOORBELL_IN_SET + // Write 1s to trigger doorbell interrupts on this core + // 0x000000ff [7:0] DOORBELL_IN_SET (0x00) + io_rw_32 doorbell_in_set; + + _REG_(SIO_DOORBELL_IN_CLR_OFFSET) // SIO_DOORBELL_IN_CLR + // Check and acknowledge doorbells posted to this core + // 0x000000ff [7:0] DOORBELL_IN_CLR (0x00) + io_rw_32 doorbell_in_clr; + + _REG_(SIO_PERI_NONSEC_OFFSET) // SIO_PERI_NONSEC + // Detach certain core-local peripherals from Secure SIO, and attach them to Non-secure SIO, so... + // 0x00000020 [5] TMDS (0) IF 1, detach TMDS encoder (of this core) from the Secure... + // 0x00000002 [1] INTERP1 (0) If 1, detach interpolator 1 (of this core) from the... + // 0x00000001 [0] INTERP0 (0) If 1, detach interpolator 0 (of this core) from the... + io_rw_32 peri_nonsec; + + uint32_t _pad2[3]; + + _REG_(SIO_RISCV_SOFTIRQ_OFFSET) // SIO_RISCV_SOFTIRQ + // Control the assertion of the standard software interrupt (MIP + // 0x00000200 [9] CORE1_CLR (0) Write 1 to atomically clear the core 1 software interrupt flag + // 0x00000100 [8] CORE0_CLR (0) Write 1 to atomically clear the core 0 software interrupt flag + // 0x00000002 [1] CORE1_SET (0) Write 1 to atomically set the core 1 software interrupt flag + // 0x00000001 [0] CORE0_SET (0) Write 1 to atomically set the core 0 software interrupt flag + io_rw_32 riscv_softirq; + + _REG_(SIO_MTIME_CTRL_OFFSET) // SIO_MTIME_CTRL + // Control register for the RISC-V 64-bit Machine-mode timer + // 0x00000008 [3] DBGPAUSE_CORE1 (1) If 1, the timer pauses when core 1 is in the debug halt state + // 0x00000004 [2] DBGPAUSE_CORE0 (1) If 1, the timer pauses when core 0 is in the debug halt state + // 0x00000002 [1] FULLSPEED (0) If 1, increment the timer every cycle (i + // 0x00000001 [0] EN (1) Timer enable bit + io_rw_32 mtime_ctrl; + + uint32_t _pad3[2]; + + _REG_(SIO_MTIME_OFFSET) // SIO_MTIME + // Read/write access to the high half of RISC-V Machine-mode timer + // 0xffffffff [31:0] MTIME (0x00000000) + io_rw_32 mtime; + + _REG_(SIO_MTIMEH_OFFSET) // SIO_MTIMEH + // Read/write access to the high half of RISC-V Machine-mode timer + // 0xffffffff [31:0] MTIMEH (0x00000000) + io_rw_32 mtimeh; + + _REG_(SIO_MTIMECMP_OFFSET) // SIO_MTIMECMP + // Low half of RISC-V Machine-mode timer comparator + // 0xffffffff [31:0] MTIMECMP (0xffffffff) + io_rw_32 mtimecmp; + + _REG_(SIO_MTIMECMPH_OFFSET) // SIO_MTIMECMPH + // High half of RISC-V Machine-mode timer comparator + // 0xffffffff [31:0] MTIMECMPH (0xffffffff) + io_rw_32 mtimecmph; + + _REG_(SIO_TMDS_CTRL_OFFSET) // SIO_TMDS_CTRL + // Control register for TMDS encoder + // 0x10000000 [28] CLEAR_BALANCE (0) Clear the running DC balance state of the TMDS encoders + // 0x08000000 [27] PIX2_NOSHIFT (0) When encoding two pixels's worth of symbols in one cycle... + // 0x07000000 [26:24] PIX_SHIFT (0x0) Shift applied to the colour data register with each read... + // 0x00800000 [23] INTERLEAVE (0) Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE + // 0x001c0000 [20:18] L2_NBITS (0x0) Number of valid colour MSBs for lane 2 (1-8 bits,... + // 0x00038000 [17:15] L1_NBITS (0x0) Number of valid colour MSBs for lane 1 (1-8 bits,... + // 0x00007000 [14:12] L0_NBITS (0x0) Number of valid colour MSBs for lane 0 (1-8 bits,... + // 0x00000f00 [11:8] L2_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by... + // 0x000000f0 [7:4] L1_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by... + // 0x0000000f [3:0] L0_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by... + io_rw_32 tmds_ctrl; + + _REG_(SIO_TMDS_WDATA_OFFSET) // SIO_TMDS_WDATA + // Write-only access to the TMDS colour data register + // 0xffffffff [31:0] TMDS_WDATA (0x00000000) + io_wo_32 tmds_wdata; + + _REG_(SIO_TMDS_PEEK_SINGLE_OFFSET) // SIO_TMDS_PEEK_SINGLE + // Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols) + // 0xffffffff [31:0] TMDS_PEEK_SINGLE (0x00000000) + io_ro_32 tmds_peek_single; + + _REG_(SIO_TMDS_POP_SINGLE_OFFSET) // SIO_TMDS_POP_SINGLE + // Get the encoding of one pixel's worth of colour data, packed into a 32-bit value + // 0xffffffff [31:0] TMDS_POP_SINGLE (0x00000000) + io_ro_32 tmds_pop_single; + + _REG_(SIO_TMDS_PEEK_DOUBLE_L0_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L0 + // Get lane 0 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L0 (0x00000000) + io_ro_32 tmds_peek_double_l0; + + _REG_(SIO_TMDS_POP_DOUBLE_L0_OFFSET) // SIO_TMDS_POP_DOUBLE_L0 + // Get lane 0 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_POP_DOUBLE_L0 (0x00000000) + io_ro_32 tmds_pop_double_l0; + + _REG_(SIO_TMDS_PEEK_DOUBLE_L1_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L1 + // Get lane 1 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L1 (0x00000000) + io_ro_32 tmds_peek_double_l1; + + _REG_(SIO_TMDS_POP_DOUBLE_L1_OFFSET) // SIO_TMDS_POP_DOUBLE_L1 + // Get lane 1 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_POP_DOUBLE_L1 (0x00000000) + io_ro_32 tmds_pop_double_l1; + + _REG_(SIO_TMDS_PEEK_DOUBLE_L2_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L2 + // Get lane 2 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L2 (0x00000000) + io_ro_32 tmds_peek_double_l2; + + _REG_(SIO_TMDS_POP_DOUBLE_L2_OFFSET) // SIO_TMDS_POP_DOUBLE_L2 + // Get lane 2 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_POP_DOUBLE_L2 (0x00000000) + io_ro_32 tmds_pop_double_l2; +} sio_hw_t; + +#define sio_hw ((sio_hw_t *)SIO_BASE) +#define sio_ns_hw ((sio_hw_t *)SIO_NONSEC_BASE) +static_assert(sizeof (sio_hw_t) == 0x01e8, ""); + +#endif // _HARDWARE_STRUCTS_SIO_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/spi.h b/lib/pico-sdk/rp2350/hardware/structs/spi.h new file mode 100644 index 00000000..454128ea --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/spi.h @@ -0,0 +1,105 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SPI_H +#define _HARDWARE_STRUCTS_SPI_H + +/** + * \file rp2350/spi.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/spi.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_spi +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/spi.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(SPI_SSPCR0_OFFSET) // SPI_SSPCR0 + // Control register 0, SSPCR0 on page 3-4 + // 0x0000ff00 [15:8] SCR (0x00) Serial clock rate + // 0x00000080 [7] SPH (0) SSPCLKOUT phase, applicable to Motorola SPI frame format only + // 0x00000040 [6] SPO (0) SSPCLKOUT polarity, applicable to Motorola SPI frame format only + // 0x00000030 [5:4] FRF (0x0) Frame format: 00 Motorola SPI frame format + // 0x0000000f [3:0] DSS (0x0) Data Size Select: 0000 Reserved, undefined operation + io_rw_32 cr0; + + _REG_(SPI_SSPCR1_OFFSET) // SPI_SSPCR1 + // Control register 1, SSPCR1 on page 3-5 + // 0x00000008 [3] SOD (0) Slave-mode output disable + // 0x00000004 [2] MS (0) Master or slave mode select + // 0x00000002 [1] SSE (0) Synchronous serial port enable: 0 SSP operation disabled + // 0x00000001 [0] LBM (0) Loop back mode: 0 Normal serial port operation enabled + io_rw_32 cr1; + + _REG_(SPI_SSPDR_OFFSET) // SPI_SSPDR + // Data register, SSPDR on page 3-6 + // 0x0000ffff [15:0] DATA (-) Transmit/Receive FIFO: Read Receive FIFO + io_rw_32 dr; + + _REG_(SPI_SSPSR_OFFSET) // SPI_SSPSR + // Status register, SSPSR on page 3-7 + // 0x00000010 [4] BSY (0) PrimeCell SSP busy flag, RO: 0 SSP is idle + // 0x00000008 [3] RFF (0) Receive FIFO full, RO: 0 Receive FIFO is not full + // 0x00000004 [2] RNE (0) Receive FIFO not empty, RO: 0 Receive FIFO is empty + // 0x00000002 [1] TNF (1) Transmit FIFO not full, RO: 0 Transmit FIFO is full + // 0x00000001 [0] TFE (1) Transmit FIFO empty, RO: 0 Transmit FIFO is not empty + io_ro_32 sr; + + _REG_(SPI_SSPCPSR_OFFSET) // SPI_SSPCPSR + // Clock prescale register, SSPCPSR on page 3-8 + // 0x000000ff [7:0] CPSDVSR (0x00) Clock prescale divisor + io_rw_32 cpsr; + + _REG_(SPI_SSPIMSC_OFFSET) // SPI_SSPIMSC + // Interrupt mask set or clear register, SSPIMSC on page 3-9 + // 0x00000008 [3] TXIM (0) Transmit FIFO interrupt mask: 0 Transmit FIFO half empty... + // 0x00000004 [2] RXIM (0) Receive FIFO interrupt mask: 0 Receive FIFO half full or... + // 0x00000002 [1] RTIM (0) Receive timeout interrupt mask: 0 Receive FIFO not empty... + // 0x00000001 [0] RORIM (0) Receive overrun interrupt mask: 0 Receive FIFO written... + io_rw_32 imsc; + + _REG_(SPI_SSPRIS_OFFSET) // SPI_SSPRIS + // Raw interrupt status register, SSPRIS on page 3-10 + // 0x00000008 [3] TXRIS (1) Gives the raw interrupt state, prior to masking, of the... + // 0x00000004 [2] RXRIS (0) Gives the raw interrupt state, prior to masking, of the... + // 0x00000002 [1] RTRIS (0) Gives the raw interrupt state, prior to masking, of the... + // 0x00000001 [0] RORRIS (0) Gives the raw interrupt state, prior to masking, of the... + io_ro_32 ris; + + _REG_(SPI_SSPMIS_OFFSET) // SPI_SSPMIS + // Masked interrupt status register, SSPMIS on page 3-11 + // 0x00000008 [3] TXMIS (0) Gives the transmit FIFO masked interrupt state, after... + // 0x00000004 [2] RXMIS (0) Gives the receive FIFO masked interrupt state, after... + // 0x00000002 [1] RTMIS (0) Gives the receive timeout masked interrupt state, after... + // 0x00000001 [0] RORMIS (0) Gives the receive over run masked interrupt status,... + io_ro_32 mis; + + _REG_(SPI_SSPICR_OFFSET) // SPI_SSPICR + // Interrupt clear register, SSPICR on page 3-11 + // 0x00000002 [1] RTIC (0) Clears the SSPRTINTR interrupt + // 0x00000001 [0] RORIC (0) Clears the SSPRORINTR interrupt + io_rw_32 icr; + + _REG_(SPI_SSPDMACR_OFFSET) // SPI_SSPDMACR + // DMA control register, SSPDMACR on page 3-12 + // 0x00000002 [1] TXDMAE (0) Transmit DMA Enable + // 0x00000001 [0] RXDMAE (0) Receive DMA Enable + io_rw_32 dmacr; +} spi_hw_t; + +#define spi0_hw ((spi_hw_t *)SPI0_BASE) +#define spi1_hw ((spi_hw_t *)SPI1_BASE) +static_assert(sizeof (spi_hw_t) == 0x0028, ""); + +#endif // _HARDWARE_STRUCTS_SPI_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/syscfg.h b/lib/pico-sdk/rp2350/hardware/structs/syscfg.h new file mode 100644 index 00000000..8909c0db --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/syscfg.h @@ -0,0 +1,83 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SYSCFG_H +#define _HARDWARE_STRUCTS_SYSCFG_H + +/** + * \file rp2350/syscfg.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/syscfg.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_syscfg +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/syscfg.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(SYSCFG_PROC_CONFIG_OFFSET) // SYSCFG_PROC_CONFIG + // Configuration for processors + // 0x00000002 [1] PROC1_HALTED (0) Indication that proc1 has halted + // 0x00000001 [0] PROC0_HALTED (0) Indication that proc0 has halted + io_ro_32 proc_config; + + _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS + // For each bit, if 1, bypass the input synchronizer between that GPIO + + // 0xffffffff [31:0] GPIO (0x00000000) + io_rw_32 proc_in_sync_bypass; + + _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS_HI + // For each bit, if 1, bypass the input synchronizer between that GPIO + + // 0xf0000000 [31:28] QSPI_SD (0x0) + // 0x08000000 [27] QSPI_CSN (0) + // 0x04000000 [26] QSPI_SCK (0) + // 0x02000000 [25] USB_DM (0) + // 0x01000000 [24] USB_DP (0) + // 0x0000ffff [15:0] GPIO (0x0000) + io_rw_32 proc_in_sync_bypass_hi; + + _REG_(SYSCFG_DBGFORCE_OFFSET) // SYSCFG_DBGFORCE + // Directly control the chip SWD debug port + // 0x00000008 [3] ATTACH (0) Attach chip debug port to syscfg controls, and... + // 0x00000004 [2] SWCLK (1) Directly drive SWCLK, if ATTACH is set + // 0x00000002 [1] SWDI (1) Directly drive SWDIO input, if ATTACH is set + // 0x00000001 [0] SWDO (-) Observe the value of SWDIO output + io_rw_32 dbgforce; + + _REG_(SYSCFG_MEMPOWERDOWN_OFFSET) // SYSCFG_MEMPOWERDOWN + // Control PD pins to memories + // 0x00001000 [12] BOOTRAM (0) + // 0x00000800 [11] ROM (0) + // 0x00000400 [10] USB (0) + // 0x00000200 [9] SRAM9 (0) + // 0x00000100 [8] SRAM8 (0) + // 0x00000080 [7] SRAM7 (0) + // 0x00000040 [6] SRAM6 (0) + // 0x00000020 [5] SRAM5 (0) + // 0x00000010 [4] SRAM4 (0) + // 0x00000008 [3] SRAM3 (0) + // 0x00000004 [2] SRAM2 (0) + // 0x00000002 [1] SRAM1 (0) + // 0x00000001 [0] SRAM0 (0) + io_rw_32 mempowerdown; + + _REG_(SYSCFG_AUXCTRL_OFFSET) // SYSCFG_AUXCTRL + // Auxiliary system control register + // 0x000000ff [7:0] AUXCTRL (0x00) * Bits 7:2: Reserved + io_rw_32 auxctrl; +} syscfg_hw_t; + +#define syscfg_hw ((syscfg_hw_t *)SYSCFG_BASE) +static_assert(sizeof (syscfg_hw_t) == 0x0018, ""); + +#endif // _HARDWARE_STRUCTS_SYSCFG_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/sysinfo.h b/lib/pico-sdk/rp2350/hardware/structs/sysinfo.h new file mode 100644 index 00000000..688b577e --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/sysinfo.h @@ -0,0 +1,60 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SYSINFO_H +#define _HARDWARE_STRUCTS_SYSINFO_H + +/** + * \file rp2350/sysinfo.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/sysinfo.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sysinfo +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/sysinfo.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(SYSINFO_CHIP_ID_OFFSET) // SYSINFO_CHIP_ID + // JEDEC JEP-106 compliant chip identifier + // 0xf0000000 [31:28] REVISION (-) + // 0x0ffff000 [27:12] PART (-) + // 0x00000ffe [11:1] MANUFACTURER (-) + // 0x00000001 [0] STOP_BIT (1) + io_ro_32 chip_id; + + _REG_(SYSINFO_PACKAGE_SEL_OFFSET) // SYSINFO_PACKAGE_SEL + // 0x00000001 [0] PACKAGE_SEL (0) + io_ro_32 package_sel; + + _REG_(SYSINFO_PLATFORM_OFFSET) // SYSINFO_PLATFORM + // Platform register + // 0x00000010 [4] GATESIM (-) + // 0x00000008 [3] BATCHSIM (-) + // 0x00000004 [2] HDLSIM (-) + // 0x00000002 [1] ASIC (-) + // 0x00000001 [0] FPGA (-) + io_ro_32 platform; + + uint32_t _pad0[2]; + + _REG_(SYSINFO_GITREF_RP2350_OFFSET) // SYSINFO_GITREF_RP2350 + // Git hash of the chip source + // 0xffffffff [31:0] GITREF_RP2350 (-) + io_ro_32 gitref_rp2350; +} sysinfo_hw_t; + +#define sysinfo_hw ((sysinfo_hw_t *)SYSINFO_BASE) +static_assert(sizeof (sysinfo_hw_t) == 0x0018, ""); + +#endif // _HARDWARE_STRUCTS_SYSINFO_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/systick.h b/lib/pico-sdk/rp2350/hardware/structs/systick.h new file mode 100644 index 00000000..f6024b1e --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/systick.h @@ -0,0 +1,62 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SYSTICK_H +#define _HARDWARE_STRUCTS_SYSTICK_H + +/** + * \file rp2350/systick.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/m33.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m33.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV +#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" +#endif + +typedef struct { + _REG_(M33_SYST_CSR_OFFSET) // M33_SYST_CSR + // SysTick Control and Status Register + // 0x00010000 [16] COUNTFLAG (0) Returns 1 if timer counted to 0 since last time this was read + // 0x00000004 [2] CLKSOURCE (0) SysTick clock source + // 0x00000002 [1] TICKINT (0) Enables SysTick exception request: + + // 0x00000001 [0] ENABLE (0) Enable SysTick counter: + + io_rw_32 csr; + + _REG_(M33_SYST_RVR_OFFSET) // M33_SYST_RVR + // SysTick Reload Value Register + // 0x00ffffff [23:0] RELOAD (0x000000) Value to load into the SysTick Current Value Register... + io_rw_32 rvr; + + _REG_(M33_SYST_CVR_OFFSET) // M33_SYST_CVR + // SysTick Current Value Register + // 0x00ffffff [23:0] CURRENT (0x000000) Reads return the current value of the SysTick counter + io_rw_32 cvr; + + _REG_(M33_SYST_CALIB_OFFSET) // M33_SYST_CALIB + // SysTick Calibration Value Register + // 0x80000000 [31] NOREF (0) If reads as 1, the Reference clock is not provided - the... + // 0x40000000 [30] SKEW (0) If reads as 1, the calibration value for 10ms is inexact... + // 0x00ffffff [23:0] TENMS (0x000000) An optional Reload value to be used for 10ms (100Hz)... + io_ro_32 calib; +} systick_hw_t; + +#define systick_hw ((systick_hw_t *)(PPB_BASE + M33_SYST_CSR_OFFSET)) +#define systick_ns_hw ((systick_hw_t *)(PPB_NONSEC_BASE + M33_SYST_CSR_OFFSET)) +static_assert(sizeof (systick_hw_t) == 0x0010, ""); + +#endif // _HARDWARE_STRUCTS_SYSTICK_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/tbman.h b/lib/pico-sdk/rp2350/hardware/structs/tbman.h new file mode 100644 index 00000000..58d80dd8 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/tbman.h @@ -0,0 +1,39 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_TBMAN_H +#define _HARDWARE_STRUCTS_TBMAN_H + +/** + * \file rp2350/tbman.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/tbman.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_tbman +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/tbman.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(TBMAN_PLATFORM_OFFSET) // TBMAN_PLATFORM + // Indicates the type of platform in use + // 0x00000004 [2] HDLSIM (0) Indicates the platform is a simulation + // 0x00000002 [1] FPGA (0) Indicates the platform is an FPGA + // 0x00000001 [0] ASIC (1) Indicates the platform is an ASIC + io_ro_32 platform; +} tbman_hw_t; + +#define tbman_hw ((tbman_hw_t *)TBMAN_BASE) +static_assert(sizeof (tbman_hw_t) == 0x0004, ""); + +#endif // _HARDWARE_STRUCTS_TBMAN_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/ticks.h b/lib/pico-sdk/rp2350/hardware/structs/ticks.h new file mode 100644 index 00000000..b436484a --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/ticks.h @@ -0,0 +1,63 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_TICKS_H +#define _HARDWARE_STRUCTS_TICKS_H + +/** + * \file rp2350/ticks.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/ticks.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_ticks +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/ticks.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/*! \brief Tick generator numbers on RP2350 (used as typedef \ref tick_gen_num_t) + * \ingroup hardware_ticks + */ +typedef enum tick_gen_num_rp2350 { + TICK_PROC0 = 0, + TICK_PROC1 = 1, + TICK_TIMER0 = 2, + TICK_TIMER1 = 3, + TICK_WATCHDOG = 4, + TICK_RISCV = 5, + TICK_COUNT +} tick_gen_num_t; + +typedef struct { + _REG_(TICKS_PROC0_CTRL_OFFSET) // TICKS_PROC0_CTRL + // Controls the tick generator + // 0x00000002 [1] RUNNING (-) Is the tick generator running? + // 0x00000001 [0] ENABLE (0) start / stop tick generation + io_rw_32 ctrl; + + _REG_(TICKS_PROC0_CYCLES_OFFSET) // TICKS_PROC0_CYCLES + // 0x000001ff [8:0] PROC0_CYCLES (0x000) Total number of clk_tick cycles before the next tick + io_rw_32 cycles; + + _REG_(TICKS_PROC0_COUNT_OFFSET) // TICKS_PROC0_COUNT + // 0x000001ff [8:0] PROC0_COUNT (-) Count down timer: the remaining number clk_tick cycles... + io_ro_32 count; +} ticks_slice_hw_t; + +typedef struct { + ticks_slice_hw_t ticks[6]; +} ticks_hw_t; + +#define ticks_hw ((ticks_hw_t *)TICKS_BASE) +static_assert(sizeof (ticks_hw_t) == 0x0048, ""); + +#endif // _HARDWARE_STRUCTS_TICKS_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/timer.h b/lib/pico-sdk/rp2350/hardware/structs/timer.h new file mode 100644 index 00000000..978dd568 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/timer.h @@ -0,0 +1,127 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_TIMER_H +#define _HARDWARE_STRUCTS_TIMER_H + +/** + * \file rp2350/timer.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/timer.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_timer +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/timer.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(TIMER_TIMEHW_OFFSET) // TIMER_TIMEHW + // Write to bits 63:32 of time always write timelw before timehw + // 0xffffffff [31:0] TIMEHW (0x00000000) + io_wo_32 timehw; + + _REG_(TIMER_TIMELW_OFFSET) // TIMER_TIMELW + // Write to bits 31:0 of time writes do not get copied to time until timehw is written + // 0xffffffff [31:0] TIMELW (0x00000000) + io_wo_32 timelw; + + _REG_(TIMER_TIMEHR_OFFSET) // TIMER_TIMEHR + // Read from bits 63:32 of time always read timelr before timehr + // 0xffffffff [31:0] TIMEHR (0x00000000) + io_ro_32 timehr; + + _REG_(TIMER_TIMELR_OFFSET) // TIMER_TIMELR + // Read from bits 31:0 of time + // 0xffffffff [31:0] TIMELR (0x00000000) + io_ro_32 timelr; + + // (Description copied from array index 0 register TIMER_ALARM0 applies similarly to other array indexes) + _REG_(TIMER_ALARM0_OFFSET) // TIMER_ALARM0 + // Arm alarm 0, and configure the time it will fire + // 0xffffffff [31:0] ALARM0 (0x00000000) + io_rw_32 alarm[4]; + + _REG_(TIMER_ARMED_OFFSET) // TIMER_ARMED + // Indicates the armed/disarmed status of each alarm + // 0x0000000f [3:0] ARMED (0x0) + io_rw_32 armed; + + _REG_(TIMER_TIMERAWH_OFFSET) // TIMER_TIMERAWH + // Raw read from bits 63:32 of time (no side effects) + // 0xffffffff [31:0] TIMERAWH (0x00000000) + io_ro_32 timerawh; + + _REG_(TIMER_TIMERAWL_OFFSET) // TIMER_TIMERAWL + // Raw read from bits 31:0 of time (no side effects) + // 0xffffffff [31:0] TIMERAWL (0x00000000) + io_ro_32 timerawl; + + _REG_(TIMER_DBGPAUSE_OFFSET) // TIMER_DBGPAUSE + // Set bits high to enable pause when the corresponding debug ports are active + // 0x00000004 [2] DBG1 (1) Pause when processor 1 is in debug mode + // 0x00000002 [1] DBG0 (1) Pause when processor 0 is in debug mode + io_rw_32 dbgpause; + + _REG_(TIMER_PAUSE_OFFSET) // TIMER_PAUSE + // Set high to pause the timer + // 0x00000001 [0] PAUSE (0) + io_rw_32 pause; + + _REG_(TIMER_LOCKED_OFFSET) // TIMER_LOCKED + // Set locked bit to disable write access to timer Once set, cannot be cleared (without a reset) + // 0x00000001 [0] LOCKED (0) + io_rw_32 locked; + + _REG_(TIMER_SOURCE_OFFSET) // TIMER_SOURCE + // Selects the source for the timer + // 0x00000001 [0] CLK_SYS (0) + io_rw_32 source; + + _REG_(TIMER_INTR_OFFSET) // TIMER_INTR + // Raw Interrupts + // 0x00000008 [3] ALARM_3 (0) + // 0x00000004 [2] ALARM_2 (0) + // 0x00000002 [1] ALARM_1 (0) + // 0x00000001 [0] ALARM_0 (0) + io_rw_32 intr; + + _REG_(TIMER_INTE_OFFSET) // TIMER_INTE + // Interrupt Enable + // 0x00000008 [3] ALARM_3 (0) + // 0x00000004 [2] ALARM_2 (0) + // 0x00000002 [1] ALARM_1 (0) + // 0x00000001 [0] ALARM_0 (0) + io_rw_32 inte; + + _REG_(TIMER_INTF_OFFSET) // TIMER_INTF + // Interrupt Force + // 0x00000008 [3] ALARM_3 (0) + // 0x00000004 [2] ALARM_2 (0) + // 0x00000002 [1] ALARM_1 (0) + // 0x00000001 [0] ALARM_0 (0) + io_rw_32 intf; + + _REG_(TIMER_INTS_OFFSET) // TIMER_INTS + // Interrupt status after masking & forcing + // 0x00000008 [3] ALARM_3 (0) + // 0x00000004 [2] ALARM_2 (0) + // 0x00000002 [1] ALARM_1 (0) + // 0x00000001 [0] ALARM_0 (0) + io_ro_32 ints; +} timer_hw_t; + +#define timer0_hw ((timer_hw_t *)TIMER0_BASE) +#define timer1_hw ((timer_hw_t *)TIMER1_BASE) +static_assert(sizeof (timer_hw_t) == 0x004c, ""); + +#endif // _HARDWARE_STRUCTS_TIMER_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/tmds_encode.h b/lib/pico-sdk/rp2350/hardware/structs/tmds_encode.h new file mode 100644 index 00000000..c1213af1 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/tmds_encode.h @@ -0,0 +1,92 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_TMDS_ENCODE_H +#define _HARDWARE_STRUCTS_TMDS_ENCODE_H + +/** + * \file rp2350/tmds_encode.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/sio.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sio +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/sio.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(SIO_TMDS_CTRL_OFFSET) // SIO_TMDS_CTRL + // Control register for TMDS encoder + // 0x10000000 [28] CLEAR_BALANCE (0) Clear the running DC balance state of the TMDS encoders + // 0x08000000 [27] PIX2_NOSHIFT (0) When encoding two pixels's worth of symbols in one cycle... + // 0x07000000 [26:24] PIX_SHIFT (0x0) Shift applied to the colour data register with each read... + // 0x00800000 [23] INTERLEAVE (0) Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE + // 0x001c0000 [20:18] L2_NBITS (0x0) Number of valid colour MSBs for lane 2 (1-8 bits,... + // 0x00038000 [17:15] L1_NBITS (0x0) Number of valid colour MSBs for lane 1 (1-8 bits,... + // 0x00007000 [14:12] L0_NBITS (0x0) Number of valid colour MSBs for lane 0 (1-8 bits,... + // 0x00000f00 [11:8] L2_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by... + // 0x000000f0 [7:4] L1_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by... + // 0x0000000f [3:0] L0_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by... + io_rw_32 tmds_ctrl; + + _REG_(SIO_TMDS_WDATA_OFFSET) // SIO_TMDS_WDATA + // Write-only access to the TMDS colour data register + // 0xffffffff [31:0] TMDS_WDATA (0x00000000) + io_wo_32 tmds_wdata; + + _REG_(SIO_TMDS_PEEK_SINGLE_OFFSET) // SIO_TMDS_PEEK_SINGLE + // Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols) + // 0xffffffff [31:0] TMDS_PEEK_SINGLE (0x00000000) + io_ro_32 tmds_peek_single; + + _REG_(SIO_TMDS_POP_SINGLE_OFFSET) // SIO_TMDS_POP_SINGLE + // Get the encoding of one pixel's worth of colour data, packed into a 32-bit value + // 0xffffffff [31:0] TMDS_POP_SINGLE (0x00000000) + io_ro_32 tmds_pop_single; + + _REG_(SIO_TMDS_PEEK_DOUBLE_L0_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L0 + // Get lane 0 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L0 (0x00000000) + io_ro_32 tmds_peek_double_l0; + + _REG_(SIO_TMDS_POP_DOUBLE_L0_OFFSET) // SIO_TMDS_POP_DOUBLE_L0 + // Get lane 0 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_POP_DOUBLE_L0 (0x00000000) + io_ro_32 tmds_pop_double_l0; + + _REG_(SIO_TMDS_PEEK_DOUBLE_L1_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L1 + // Get lane 1 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L1 (0x00000000) + io_ro_32 tmds_peek_double_l1; + + _REG_(SIO_TMDS_POP_DOUBLE_L1_OFFSET) // SIO_TMDS_POP_DOUBLE_L1 + // Get lane 1 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_POP_DOUBLE_L1 (0x00000000) + io_ro_32 tmds_pop_double_l1; + + _REG_(SIO_TMDS_PEEK_DOUBLE_L2_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L2 + // Get lane 2 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L2 (0x00000000) + io_ro_32 tmds_peek_double_l2; + + _REG_(SIO_TMDS_POP_DOUBLE_L2_OFFSET) // SIO_TMDS_POP_DOUBLE_L2 + // Get lane 2 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_POP_DOUBLE_L2 (0x00000000) + io_ro_32 tmds_pop_double_l2; +} tmds_encode_hw_t; + +#define tmds_encode_hw ((tmds_encode_hw_t *)(SIO_BASE + SIO_TMDS_CTRL_OFFSET)) +#define tmds_encode_ns_hw ((tmds_encode_hw_t *)(SIO_NONSEC_BASE + SIO_TMDS_CTRL_OFFSET)) +static_assert(sizeof (tmds_encode_hw_t) == 0x0028, ""); + +#endif // _HARDWARE_STRUCTS_TMDS_ENCODE_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/trng.h b/lib/pico-sdk/rp2350/hardware/structs/trng.h new file mode 100644 index 00000000..5ae59296 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/trng.h @@ -0,0 +1,153 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_TRNG_H +#define _HARDWARE_STRUCTS_TRNG_H + +/** + * \file rp2350/trng.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/trng.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_trng +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/trng.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(TRNG_RNG_IMR_OFFSET) // TRNG_RNG_IMR + // Interrupt masking + // 0xfffffff0 [31:4] RESERVED (0x0000000) RESERVED + // 0x00000008 [3] VN_ERR_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated + // 0x00000004 [2] CRNGT_ERR_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated + // 0x00000002 [1] AUTOCORR_ERR_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated + // 0x00000001 [0] EHR_VALID_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated + io_rw_32 rng_imr; + + _REG_(TRNG_RNG_ISR_OFFSET) // TRNG_RNG_ISR + // RNG status register + // 0xfffffff0 [31:4] RESERVED (0x0000000) RESERVED + // 0x00000008 [3] VN_ERR (0) 1'b1 indicates Von Neuman error + // 0x00000004 [2] CRNGT_ERR (0) 1'b1 indicates CRNGT in the RNG test failed + // 0x00000002 [1] AUTOCORR_ERR (0) 1'b1 indicates Autocorrelation test failed four times in a row + // 0x00000001 [0] EHR_VALID (0) 1'b1 indicates that 192 bits have been collected in the... + io_ro_32 rng_isr; + + _REG_(TRNG_RNG_ICR_OFFSET) // TRNG_RNG_ICR + // Interrupt/status bit clear Register + // 0xfffffff0 [31:4] RESERVED (0x0000000) RESERVED + // 0x00000008 [3] VN_ERR (0) Write 1'b1 - clear corresponding bit in RNG_ISR + // 0x00000004 [2] CRNGT_ERR (0) Write 1'b1 - clear corresponding bit in RNG_ISR + // 0x00000002 [1] AUTOCORR_ERR (0) Cannot be cleared by SW! Only RNG reset clears this bit + // 0x00000001 [0] EHR_VALID (0) Write 1'b1 - clear corresponding bit in RNG_ISR + io_rw_32 rng_icr; + + _REG_(TRNG_TRNG_CONFIG_OFFSET) // TRNG_TRNG_CONFIG + // Selecting the inverter-chain length + // 0xfffffffc [31:2] RESERVED (0x00000000) RESERVED + // 0x00000003 [1:0] RND_SRC_SEL (0x0) Selects the number of inverters (out of four possible... + io_rw_32 trng_config; + + _REG_(TRNG_TRNG_VALID_OFFSET) // TRNG_TRNG_VALID + // 192 bit collection indication + // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED + // 0x00000001 [0] EHR_VALID (0) 1'b1 indicates that collection of bits in the RNG is... + io_ro_32 trng_valid; + + // (Description copied from array index 0 register TRNG_EHR_DATA0 applies similarly to other array indexes) + _REG_(TRNG_EHR_DATA0_OFFSET) // TRNG_EHR_DATA0 + // RNG collected bits + // 0xffffffff [31:0] EHR_DATA0 (0x00000000) Bits [31:0] of Entropy Holding Register (EHR) - RNG... + io_ro_32 ehr_data[6]; + + _REG_(TRNG_RND_SOURCE_ENABLE_OFFSET) // TRNG_RND_SOURCE_ENABLE + // Enable signal for the random source + // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED + // 0x00000001 [0] RND_SRC_EN (0) * 1'b1 - entropy source is enabled + io_rw_32 rnd_source_enable; + + _REG_(TRNG_SAMPLE_CNT1_OFFSET) // TRNG_SAMPLE_CNT1 + // Counts clocks between sampling of random bit + // 0xffffffff [31:0] SAMPLE_CNTR1 (0x0000ffff) Sets the number of rng_clk cycles between two... + io_rw_32 sample_cnt1; + + _REG_(TRNG_AUTOCORR_STATISTIC_OFFSET) // TRNG_AUTOCORR_STATISTIC + // Statistic about Autocorrelation test activations + // 0xffc00000 [31:22] RESERVED (0x000) RESERVED + // 0x003fc000 [21:14] AUTOCORR_FAILS (0x00) Count each time an autocorrelation test fails + // 0x00003fff [13:0] AUTOCORR_TRYS (0x0000) Count each time an autocorrelation test starts + io_rw_32 autocorr_statistic; + + _REG_(TRNG_TRNG_DEBUG_CONTROL_OFFSET) // TRNG_TRNG_DEBUG_CONTROL + // Debug register + // 0x00000008 [3] AUTO_CORRELATE_BYPASS (0) When set, the autocorrelation test in the TRNG module is bypassed + // 0x00000004 [2] TRNG_CRNGT_BYPASS (0) When set, the CRNGT test in the RNG is bypassed + // 0x00000002 [1] VNC_BYPASS (0) When set, the Von-Neuman balancer is bypassed (including... + // 0x00000001 [0] RESERVED (0) N/A + io_rw_32 trng_debug_control; + + uint32_t _pad0; + + _REG_(TRNG_TRNG_SW_RESET_OFFSET) // TRNG_TRNG_SW_RESET + // Generate internal SW reset within the RNG block + // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED + // 0x00000001 [0] TRNG_SW_RESET (0) Writing 1'b1 to this register causes an internal RNG reset + io_rw_32 trng_sw_reset; + + uint32_t _pad1[28]; + + _REG_(TRNG_RNG_DEBUG_EN_INPUT_OFFSET) // TRNG_RNG_DEBUG_EN_INPUT + // Enable the RNG debug mode + // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED + // 0x00000001 [0] RNG_DEBUG_EN (0) * 1'b1 - debug mode is enabled + io_rw_32 rng_debug_en_input; + + _REG_(TRNG_TRNG_BUSY_OFFSET) // TRNG_TRNG_BUSY + // RNG Busy indication + // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED + // 0x00000001 [0] TRNG_BUSY (0) Reflects rng_busy status + io_ro_32 trng_busy; + + _REG_(TRNG_RST_BITS_COUNTER_OFFSET) // TRNG_RST_BITS_COUNTER + // Reset the counter of collected bits in the RNG + // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED + // 0x00000001 [0] RST_BITS_COUNTER (0) Writing any value to this address will reset the bits... + io_rw_32 rst_bits_counter; + + _REG_(TRNG_RNG_VERSION_OFFSET) // TRNG_RNG_VERSION + // Displays the version settings of the TRNG + // 0xffffff00 [31:8] RESERVED (0x000000) RESERVED + // 0x00000080 [7] RNG_USE_5_SBOXES (0) * 1'b1 - 5 SBOX AES + // 0x00000040 [6] RESEEDING_EXISTS (0) * 1'b1 - Exists + // 0x00000020 [5] KAT_EXISTS (0) * 1'b1 - Exists + // 0x00000010 [4] PRNG_EXISTS (0) * 1'b1 - Exists + // 0x00000008 [3] TRNG_TESTS_BYPASS_EN (0) * 1'b1 - Exists + // 0x00000004 [2] AUTOCORR_EXISTS (0) * 1'b1 - Exists + // 0x00000002 [1] CRNGT_EXISTS (0) * 1'b1 - Exists + // 0x00000001 [0] EHR_WIDTH_192 (0) * 1'b1 - 192-bit EHR + io_ro_32 rng_version; + + uint32_t _pad2[7]; + + // (Description copied from array index 0 register TRNG_RNG_BIST_CNTR_0 applies similarly to other array indexes) + _REG_(TRNG_RNG_BIST_CNTR_0_OFFSET) // TRNG_RNG_BIST_CNTR_0 + // Collected BIST results + // 0xffc00000 [31:22] RESERVED (0x000) RESERVED + // 0x003fffff [21:0] ROSC_CNTR_VAL (0x000000) Reflects the results of RNG BIST counter + io_ro_32 rng_bist_cntr[3]; +} trng_hw_t; + +#define trng_hw ((trng_hw_t *)(TRNG_BASE + TRNG_RNG_IMR_OFFSET)) +static_assert(sizeof (trng_hw_t) == 0x00ec, ""); + +#endif // _HARDWARE_STRUCTS_TRNG_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/uart.h b/lib/pico-sdk/rp2350/hardware/structs/uart.h new file mode 100644 index 00000000..47ff324e --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/uart.h @@ -0,0 +1,182 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_UART_H +#define _HARDWARE_STRUCTS_UART_H + +/** + * \file rp2350/uart.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/uart.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_uart +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/uart.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(UART_UARTDR_OFFSET) // UART_UARTDR + // Data Register, UARTDR + // 0x00000800 [11] OE (-) Overrun error + // 0x00000400 [10] BE (-) Break error + // 0x00000200 [9] PE (-) Parity error + // 0x00000100 [8] FE (-) Framing error + // 0x000000ff [7:0] DATA (-) Receive (read) data character + io_rw_32 dr; + + _REG_(UART_UARTRSR_OFFSET) // UART_UARTRSR + // Receive Status Register/Error Clear Register, UARTRSR/UARTECR + // 0x00000008 [3] OE (0) Overrun error + // 0x00000004 [2] BE (0) Break error + // 0x00000002 [1] PE (0) Parity error + // 0x00000001 [0] FE (0) Framing error + io_rw_32 rsr; + + uint32_t _pad0[4]; + + _REG_(UART_UARTFR_OFFSET) // UART_UARTFR + // Flag Register, UARTFR + // 0x00000100 [8] RI (-) Ring indicator + // 0x00000080 [7] TXFE (1) Transmit FIFO empty + // 0x00000040 [6] RXFF (0) Receive FIFO full + // 0x00000020 [5] TXFF (0) Transmit FIFO full + // 0x00000010 [4] RXFE (1) Receive FIFO empty + // 0x00000008 [3] BUSY (0) UART busy + // 0x00000004 [2] DCD (-) Data carrier detect + // 0x00000002 [1] DSR (-) Data set ready + // 0x00000001 [0] CTS (-) Clear to send + io_ro_32 fr; + + uint32_t _pad1; + + _REG_(UART_UARTILPR_OFFSET) // UART_UARTILPR + // IrDA Low-Power Counter Register, UARTILPR + // 0x000000ff [7:0] ILPDVSR (0x00) 8-bit low-power divisor value + io_rw_32 ilpr; + + _REG_(UART_UARTIBRD_OFFSET) // UART_UARTIBRD + // Integer Baud Rate Register, UARTIBRD + // 0x0000ffff [15:0] BAUD_DIVINT (0x0000) The integer baud rate divisor + io_rw_32 ibrd; + + _REG_(UART_UARTFBRD_OFFSET) // UART_UARTFBRD + // Fractional Baud Rate Register, UARTFBRD + // 0x0000003f [5:0] BAUD_DIVFRAC (0x00) The fractional baud rate divisor + io_rw_32 fbrd; + + _REG_(UART_UARTLCR_H_OFFSET) // UART_UARTLCR_H + // Line Control Register, UARTLCR_H + // 0x00000080 [7] SPS (0) Stick parity select + // 0x00000060 [6:5] WLEN (0x0) Word length + // 0x00000010 [4] FEN (0) Enable FIFOs: 0 = FIFOs are disabled (character mode)... + // 0x00000008 [3] STP2 (0) Two stop bits select + // 0x00000004 [2] EPS (0) Even parity select + // 0x00000002 [1] PEN (0) Parity enable: 0 = parity is disabled and no parity bit... + // 0x00000001 [0] BRK (0) Send break + io_rw_32 lcr_h; + + _REG_(UART_UARTCR_OFFSET) // UART_UARTCR + // Control Register, UARTCR + // 0x00008000 [15] CTSEN (0) CTS hardware flow control enable + // 0x00004000 [14] RTSEN (0) RTS hardware flow control enable + // 0x00002000 [13] OUT2 (0) This bit is the complement of the UART Out2 (nUARTOut2)... + // 0x00001000 [12] OUT1 (0) This bit is the complement of the UART Out1 (nUARTOut1)... + // 0x00000800 [11] RTS (0) Request to send + // 0x00000400 [10] DTR (0) Data transmit ready + // 0x00000200 [9] RXE (1) Receive enable + // 0x00000100 [8] TXE (1) Transmit enable + // 0x00000080 [7] LBE (0) Loopback enable + // 0x00000004 [2] SIRLP (0) SIR low-power IrDA mode + // 0x00000002 [1] SIREN (0) SIR enable: 0 = IrDA SIR ENDEC is disabled + // 0x00000001 [0] UARTEN (0) UART enable: 0 = UART is disabled + io_rw_32 cr; + + _REG_(UART_UARTIFLS_OFFSET) // UART_UARTIFLS + // Interrupt FIFO Level Select Register, UARTIFLS + // 0x00000038 [5:3] RXIFLSEL (0x2) Receive interrupt FIFO level select + // 0x00000007 [2:0] TXIFLSEL (0x2) Transmit interrupt FIFO level select + io_rw_32 ifls; + + _REG_(UART_UARTIMSC_OFFSET) // UART_UARTIMSC + // Interrupt Mask Set/Clear Register, UARTIMSC + // 0x00000400 [10] OEIM (0) Overrun error interrupt mask + // 0x00000200 [9] BEIM (0) Break error interrupt mask + // 0x00000100 [8] PEIM (0) Parity error interrupt mask + // 0x00000080 [7] FEIM (0) Framing error interrupt mask + // 0x00000040 [6] RTIM (0) Receive timeout interrupt mask + // 0x00000020 [5] TXIM (0) Transmit interrupt mask + // 0x00000010 [4] RXIM (0) Receive interrupt mask + // 0x00000008 [3] DSRMIM (0) nUARTDSR modem interrupt mask + // 0x00000004 [2] DCDMIM (0) nUARTDCD modem interrupt mask + // 0x00000002 [1] CTSMIM (0) nUARTCTS modem interrupt mask + // 0x00000001 [0] RIMIM (0) nUARTRI modem interrupt mask + io_rw_32 imsc; + + _REG_(UART_UARTRIS_OFFSET) // UART_UARTRIS + // Raw Interrupt Status Register, UARTRIS + // 0x00000400 [10] OERIS (0) Overrun error interrupt status + // 0x00000200 [9] BERIS (0) Break error interrupt status + // 0x00000100 [8] PERIS (0) Parity error interrupt status + // 0x00000080 [7] FERIS (0) Framing error interrupt status + // 0x00000040 [6] RTRIS (0) Receive timeout interrupt status + // 0x00000020 [5] TXRIS (0) Transmit interrupt status + // 0x00000010 [4] RXRIS (0) Receive interrupt status + // 0x00000008 [3] DSRRMIS (-) nUARTDSR modem interrupt status + // 0x00000004 [2] DCDRMIS (-) nUARTDCD modem interrupt status + // 0x00000002 [1] CTSRMIS (-) nUARTCTS modem interrupt status + // 0x00000001 [0] RIRMIS (-) nUARTRI modem interrupt status + io_ro_32 ris; + + _REG_(UART_UARTMIS_OFFSET) // UART_UARTMIS + // Masked Interrupt Status Register, UARTMIS + // 0x00000400 [10] OEMIS (0) Overrun error masked interrupt status + // 0x00000200 [9] BEMIS (0) Break error masked interrupt status + // 0x00000100 [8] PEMIS (0) Parity error masked interrupt status + // 0x00000080 [7] FEMIS (0) Framing error masked interrupt status + // 0x00000040 [6] RTMIS (0) Receive timeout masked interrupt status + // 0x00000020 [5] TXMIS (0) Transmit masked interrupt status + // 0x00000010 [4] RXMIS (0) Receive masked interrupt status + // 0x00000008 [3] DSRMMIS (-) nUARTDSR modem masked interrupt status + // 0x00000004 [2] DCDMMIS (-) nUARTDCD modem masked interrupt status + // 0x00000002 [1] CTSMMIS (-) nUARTCTS modem masked interrupt status + // 0x00000001 [0] RIMMIS (-) nUARTRI modem masked interrupt status + io_ro_32 mis; + + _REG_(UART_UARTICR_OFFSET) // UART_UARTICR + // Interrupt Clear Register, UARTICR + // 0x00000400 [10] OEIC (-) Overrun error interrupt clear + // 0x00000200 [9] BEIC (-) Break error interrupt clear + // 0x00000100 [8] PEIC (-) Parity error interrupt clear + // 0x00000080 [7] FEIC (-) Framing error interrupt clear + // 0x00000040 [6] RTIC (-) Receive timeout interrupt clear + // 0x00000020 [5] TXIC (-) Transmit interrupt clear + // 0x00000010 [4] RXIC (-) Receive interrupt clear + // 0x00000008 [3] DSRMIC (-) nUARTDSR modem interrupt clear + // 0x00000004 [2] DCDMIC (-) nUARTDCD modem interrupt clear + // 0x00000002 [1] CTSMIC (-) nUARTCTS modem interrupt clear + // 0x00000001 [0] RIMIC (-) nUARTRI modem interrupt clear + io_rw_32 icr; + + _REG_(UART_UARTDMACR_OFFSET) // UART_UARTDMACR + // DMA Control Register, UARTDMACR + // 0x00000004 [2] DMAONERR (0) DMA on error + // 0x00000002 [1] TXDMAE (0) Transmit DMA enable + // 0x00000001 [0] RXDMAE (0) Receive DMA enable + io_rw_32 dmacr; +} uart_hw_t; + +#define uart0_hw ((uart_hw_t *)UART0_BASE) +#define uart1_hw ((uart_hw_t *)UART1_BASE) +static_assert(sizeof (uart_hw_t) == 0x004c, ""); + +#endif // _HARDWARE_STRUCTS_UART_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/usb.h b/lib/pico-sdk/rp2350/hardware/structs/usb.h new file mode 100644 index 00000000..1c6229bd --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/usb.h @@ -0,0 +1,602 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_USB_H +#define _HARDWARE_STRUCTS_USB_H + +/** + * \file rp2350/usb.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/usb.h" +#include "hardware/structs/usb_dpram.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_usb +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/usb.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(USB_ADDR_ENDP_OFFSET) // USB_ADDR_ENDP + // Device address and endpoint control + // 0x000f0000 [19:16] ENDPOINT (0x0) Device endpoint to send data to + // 0x0000007f [6:0] ADDRESS (0x00) In device mode, the address that the device should respond to + io_rw_32 dev_addr_ctrl; + + // (Description copied from array index 0 register USB_ADDR_ENDP1 applies similarly to other array indexes) + _REG_(USB_ADDR_ENDP1_OFFSET) // USB_ADDR_ENDP1 + // Interrupt endpoint 1 + // 0x04000000 [26] INTEP_PREAMBLE (0) Interrupt EP requires preamble (is a low speed device on... + // 0x02000000 [25] INTEP_DIR (0) Direction of the interrupt endpoint + // 0x000f0000 [19:16] ENDPOINT (0x0) Endpoint number of the interrupt endpoint + // 0x0000007f [6:0] ADDRESS (0x00) Device address + io_rw_32 int_ep_addr_ctrl[15]; + + _REG_(USB_MAIN_CTRL_OFFSET) // USB_MAIN_CTRL + // Main control register + // 0x80000000 [31] SIM_TIMING (0) Reduced timings for simulation + // 0x00000004 [2] PHY_ISO (1) Isolates USB phy after controller power-up + + // 0x00000002 [1] HOST_NDEVICE (0) Device mode = 0, Host mode = 1 + // 0x00000001 [0] CONTROLLER_EN (0) Enable controller + io_rw_32 main_ctrl; + + _REG_(USB_SOF_WR_OFFSET) // USB_SOF_WR + // Set the SOF (Start of Frame) frame number in the host controller + // 0x000007ff [10:0] COUNT (0x000) + io_wo_32 sof_wr; + + _REG_(USB_SOF_RD_OFFSET) // USB_SOF_RD + // Read the last SOF (Start of Frame) frame number seen + // 0x000007ff [10:0] COUNT (0x000) + io_ro_32 sof_rd; + + _REG_(USB_SIE_CTRL_OFFSET) // USB_SIE_CTRL + // SIE control register + // 0x80000000 [31] EP0_INT_STALL (0) Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL + // 0x40000000 [30] EP0_DOUBLE_BUF (0) Device: EP0 single buffered = 0, double buffered = 1 + // 0x20000000 [29] EP0_INT_1BUF (0) Device: Set bit in BUFF_STATUS for every buffer completed on EP0 + // 0x10000000 [28] EP0_INT_2BUF (0) Device: Set bit in BUFF_STATUS for every 2 buffers... + // 0x08000000 [27] EP0_INT_NAK (0) Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK + // 0x04000000 [26] DIRECT_EN (0) Direct bus drive enable + // 0x02000000 [25] DIRECT_DP (0) Direct control of DP + // 0x01000000 [24] DIRECT_DM (0) Direct control of DM + // 0x00080000 [19] EP0_STOP_ON_SHORT_PACKET (0) Device: Stop EP0 on a short packet + // 0x00040000 [18] TRANSCEIVER_PD (0) Power down bus transceiver + // 0x00020000 [17] RPU_OPT (0) Device: Pull-up strength (0=1K2, 1=2k3) + // 0x00010000 [16] PULLUP_EN (0) Device: Enable pull up resistor + // 0x00008000 [15] PULLDOWN_EN (1) Host: Enable pull down resistors + // 0x00002000 [13] RESET_BUS (0) Host: Reset bus + // 0x00001000 [12] RESUME (0) Device: Remote wakeup + // 0x00000800 [11] VBUS_EN (0) Host: Enable VBUS + // 0x00000400 [10] KEEP_ALIVE_EN (0) Host: Enable keep alive packet (for low speed bus) + // 0x00000200 [9] SOF_EN (0) Host: Enable SOF generation (for full speed bus) + // 0x00000100 [8] SOF_SYNC (0) Host: Delay packet(s) until after SOF + // 0x00000040 [6] PREAMBLE_EN (0) Host: Preable enable for LS device on FS hub + // 0x00000010 [4] STOP_TRANS (0) Host: Stop transaction + // 0x00000008 [3] RECEIVE_DATA (0) Host: Receive transaction (IN to host) + // 0x00000004 [2] SEND_DATA (0) Host: Send transaction (OUT from host) + // 0x00000002 [1] SEND_SETUP (0) Host: Send Setup packet + // 0x00000001 [0] START_TRANS (0) Host: Start transaction + io_rw_32 sie_ctrl; + + _REG_(USB_SIE_STATUS_OFFSET) // USB_SIE_STATUS + // SIE status register + // 0x80000000 [31] DATA_SEQ_ERROR (0) Data Sequence Error + // 0x40000000 [30] ACK_REC (0) ACK received + // 0x20000000 [29] STALL_REC (0) Host: STALL received + // 0x10000000 [28] NAK_REC (0) Host: NAK received + // 0x08000000 [27] RX_TIMEOUT (0) RX timeout is raised by both the host and device if an... + // 0x04000000 [26] RX_OVERFLOW (0) RX overflow is raised by the Serial RX engine if the... + // 0x02000000 [25] BIT_STUFF_ERROR (0) Bit Stuff Error + // 0x01000000 [24] CRC_ERROR (0) CRC Error + // 0x00800000 [23] ENDPOINT_ERROR (0) An endpoint has encountered an error + // 0x00080000 [19] BUS_RESET (0) Device: bus reset received + // 0x00040000 [18] TRANS_COMPLETE (0) Transaction complete + // 0x00020000 [17] SETUP_REC (0) Device: Setup packet received + // 0x00010000 [16] CONNECTED (0) Device: connected + // 0x00001000 [12] RX_SHORT_PACKET (0) Device or Host has received a short packet + // 0x00000800 [11] RESUME (0) Host: Device has initiated a remote resume + // 0x00000400 [10] VBUS_OVER_CURR (0) VBUS over current detected + // 0x00000300 [9:8] SPEED (0x0) Host: device speed + // 0x00000010 [4] SUSPENDED (0) Bus in suspended state + // 0x0000000c [3:2] LINE_STATE (0x0) USB bus line state + // 0x00000001 [0] VBUS_DETECTED (0) Device: VBUS Detected + io_rw_32 sie_status; + + _REG_(USB_INT_EP_CTRL_OFFSET) // USB_INT_EP_CTRL + // interrupt endpoint control register + // 0x0000fffe [15:1] INT_EP_ACTIVE (0x0000) Host: Enable interrupt endpoint 1 -> 15 + io_rw_32 int_ep_ctrl; + + _REG_(USB_BUFF_STATUS_OFFSET) // USB_BUFF_STATUS + // Buffer status register + // 0x80000000 [31] EP15_OUT (0) + // 0x40000000 [30] EP15_IN (0) + // 0x20000000 [29] EP14_OUT (0) + // 0x10000000 [28] EP14_IN (0) + // 0x08000000 [27] EP13_OUT (0) + // 0x04000000 [26] EP13_IN (0) + // 0x02000000 [25] EP12_OUT (0) + // 0x01000000 [24] EP12_IN (0) + // 0x00800000 [23] EP11_OUT (0) + // 0x00400000 [22] EP11_IN (0) + // 0x00200000 [21] EP10_OUT (0) + // 0x00100000 [20] EP10_IN (0) + // 0x00080000 [19] EP9_OUT (0) + // 0x00040000 [18] EP9_IN (0) + // 0x00020000 [17] EP8_OUT (0) + // 0x00010000 [16] EP8_IN (0) + // 0x00008000 [15] EP7_OUT (0) + // 0x00004000 [14] EP7_IN (0) + // 0x00002000 [13] EP6_OUT (0) + // 0x00001000 [12] EP6_IN (0) + // 0x00000800 [11] EP5_OUT (0) + // 0x00000400 [10] EP5_IN (0) + // 0x00000200 [9] EP4_OUT (0) + // 0x00000100 [8] EP4_IN (0) + // 0x00000080 [7] EP3_OUT (0) + // 0x00000040 [6] EP3_IN (0) + // 0x00000020 [5] EP2_OUT (0) + // 0x00000010 [4] EP2_IN (0) + // 0x00000008 [3] EP1_OUT (0) + // 0x00000004 [2] EP1_IN (0) + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) + io_rw_32 buf_status; + + _REG_(USB_BUFF_CPU_SHOULD_HANDLE_OFFSET) // USB_BUFF_CPU_SHOULD_HANDLE + // Which of the double buffers should be handled + // 0x80000000 [31] EP15_OUT (0) + // 0x40000000 [30] EP15_IN (0) + // 0x20000000 [29] EP14_OUT (0) + // 0x10000000 [28] EP14_IN (0) + // 0x08000000 [27] EP13_OUT (0) + // 0x04000000 [26] EP13_IN (0) + // 0x02000000 [25] EP12_OUT (0) + // 0x01000000 [24] EP12_IN (0) + // 0x00800000 [23] EP11_OUT (0) + // 0x00400000 [22] EP11_IN (0) + // 0x00200000 [21] EP10_OUT (0) + // 0x00100000 [20] EP10_IN (0) + // 0x00080000 [19] EP9_OUT (0) + // 0x00040000 [18] EP9_IN (0) + // 0x00020000 [17] EP8_OUT (0) + // 0x00010000 [16] EP8_IN (0) + // 0x00008000 [15] EP7_OUT (0) + // 0x00004000 [14] EP7_IN (0) + // 0x00002000 [13] EP6_OUT (0) + // 0x00001000 [12] EP6_IN (0) + // 0x00000800 [11] EP5_OUT (0) + // 0x00000400 [10] EP5_IN (0) + // 0x00000200 [9] EP4_OUT (0) + // 0x00000100 [8] EP4_IN (0) + // 0x00000080 [7] EP3_OUT (0) + // 0x00000040 [6] EP3_IN (0) + // 0x00000020 [5] EP2_OUT (0) + // 0x00000010 [4] EP2_IN (0) + // 0x00000008 [3] EP1_OUT (0) + // 0x00000004 [2] EP1_IN (0) + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) + io_ro_32 buf_cpu_should_handle; + + _REG_(USB_EP_ABORT_OFFSET) // USB_EP_ABORT + // Device only: Can be set to ignore the buffer control register for this endpoint in case you... + // 0x80000000 [31] EP15_OUT (0) + // 0x40000000 [30] EP15_IN (0) + // 0x20000000 [29] EP14_OUT (0) + // 0x10000000 [28] EP14_IN (0) + // 0x08000000 [27] EP13_OUT (0) + // 0x04000000 [26] EP13_IN (0) + // 0x02000000 [25] EP12_OUT (0) + // 0x01000000 [24] EP12_IN (0) + // 0x00800000 [23] EP11_OUT (0) + // 0x00400000 [22] EP11_IN (0) + // 0x00200000 [21] EP10_OUT (0) + // 0x00100000 [20] EP10_IN (0) + // 0x00080000 [19] EP9_OUT (0) + // 0x00040000 [18] EP9_IN (0) + // 0x00020000 [17] EP8_OUT (0) + // 0x00010000 [16] EP8_IN (0) + // 0x00008000 [15] EP7_OUT (0) + // 0x00004000 [14] EP7_IN (0) + // 0x00002000 [13] EP6_OUT (0) + // 0x00001000 [12] EP6_IN (0) + // 0x00000800 [11] EP5_OUT (0) + // 0x00000400 [10] EP5_IN (0) + // 0x00000200 [9] EP4_OUT (0) + // 0x00000100 [8] EP4_IN (0) + // 0x00000080 [7] EP3_OUT (0) + // 0x00000040 [6] EP3_IN (0) + // 0x00000020 [5] EP2_OUT (0) + // 0x00000010 [4] EP2_IN (0) + // 0x00000008 [3] EP1_OUT (0) + // 0x00000004 [2] EP1_IN (0) + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) + io_rw_32 abort; + + _REG_(USB_EP_ABORT_DONE_OFFSET) // USB_EP_ABORT_DONE + // Device only: Used in conjunction with `EP_ABORT` + // 0x80000000 [31] EP15_OUT (0) + // 0x40000000 [30] EP15_IN (0) + // 0x20000000 [29] EP14_OUT (0) + // 0x10000000 [28] EP14_IN (0) + // 0x08000000 [27] EP13_OUT (0) + // 0x04000000 [26] EP13_IN (0) + // 0x02000000 [25] EP12_OUT (0) + // 0x01000000 [24] EP12_IN (0) + // 0x00800000 [23] EP11_OUT (0) + // 0x00400000 [22] EP11_IN (0) + // 0x00200000 [21] EP10_OUT (0) + // 0x00100000 [20] EP10_IN (0) + // 0x00080000 [19] EP9_OUT (0) + // 0x00040000 [18] EP9_IN (0) + // 0x00020000 [17] EP8_OUT (0) + // 0x00010000 [16] EP8_IN (0) + // 0x00008000 [15] EP7_OUT (0) + // 0x00004000 [14] EP7_IN (0) + // 0x00002000 [13] EP6_OUT (0) + // 0x00001000 [12] EP6_IN (0) + // 0x00000800 [11] EP5_OUT (0) + // 0x00000400 [10] EP5_IN (0) + // 0x00000200 [9] EP4_OUT (0) + // 0x00000100 [8] EP4_IN (0) + // 0x00000080 [7] EP3_OUT (0) + // 0x00000040 [6] EP3_IN (0) + // 0x00000020 [5] EP2_OUT (0) + // 0x00000010 [4] EP2_IN (0) + // 0x00000008 [3] EP1_OUT (0) + // 0x00000004 [2] EP1_IN (0) + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) + io_rw_32 abort_done; + + _REG_(USB_EP_STALL_ARM_OFFSET) // USB_EP_STALL_ARM + // Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register... + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) + io_rw_32 ep_stall_arm; + + _REG_(USB_NAK_POLL_OFFSET) // USB_NAK_POLL + // Used by the host controller + // 0xf0000000 [31:28] RETRY_COUNT_HI (0x0) Bits 9:6 of nak_retry count + // 0x08000000 [27] EPX_STOPPED_ON_NAK (0) EPX polling has stopped because a nak was received + // 0x04000000 [26] STOP_EPX_ON_NAK (0) Stop polling epx when a nak is received + // 0x03ff0000 [25:16] DELAY_FS (0x010) NAK polling interval for a full speed device + // 0x0000fc00 [15:10] RETRY_COUNT_LO (0x00) Bits 5:0 of nak_retry_count + // 0x000003ff [9:0] DELAY_LS (0x010) NAK polling interval for a low speed device + io_rw_32 nak_poll; + + _REG_(USB_EP_STATUS_STALL_NAK_OFFSET) // USB_EP_STATUS_STALL_NAK + // Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set + // 0x80000000 [31] EP15_OUT (0) + // 0x40000000 [30] EP15_IN (0) + // 0x20000000 [29] EP14_OUT (0) + // 0x10000000 [28] EP14_IN (0) + // 0x08000000 [27] EP13_OUT (0) + // 0x04000000 [26] EP13_IN (0) + // 0x02000000 [25] EP12_OUT (0) + // 0x01000000 [24] EP12_IN (0) + // 0x00800000 [23] EP11_OUT (0) + // 0x00400000 [22] EP11_IN (0) + // 0x00200000 [21] EP10_OUT (0) + // 0x00100000 [20] EP10_IN (0) + // 0x00080000 [19] EP9_OUT (0) + // 0x00040000 [18] EP9_IN (0) + // 0x00020000 [17] EP8_OUT (0) + // 0x00010000 [16] EP8_IN (0) + // 0x00008000 [15] EP7_OUT (0) + // 0x00004000 [14] EP7_IN (0) + // 0x00002000 [13] EP6_OUT (0) + // 0x00001000 [12] EP6_IN (0) + // 0x00000800 [11] EP5_OUT (0) + // 0x00000400 [10] EP5_IN (0) + // 0x00000200 [9] EP4_OUT (0) + // 0x00000100 [8] EP4_IN (0) + // 0x00000080 [7] EP3_OUT (0) + // 0x00000040 [6] EP3_IN (0) + // 0x00000020 [5] EP2_OUT (0) + // 0x00000010 [4] EP2_IN (0) + // 0x00000008 [3] EP1_OUT (0) + // 0x00000004 [2] EP1_IN (0) + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) + io_rw_32 ep_nak_stall_status; + + _REG_(USB_USB_MUXING_OFFSET) // USB_USB_MUXING + // Where to connect the USB controller + // 0x80000000 [31] SWAP_DPDM (0) Swap the USB PHY DP and DM pins and all related controls... + // 0x00000010 [4] USBPHY_AS_GPIO (0) Use the usb DP and DM pins as GPIO pins instead of... + // 0x00000008 [3] SOFTCON (0) + // 0x00000004 [2] TO_DIGITAL_PAD (0) + // 0x00000002 [1] TO_EXTPHY (0) + // 0x00000001 [0] TO_PHY (1) + io_rw_32 muxing; + + _REG_(USB_USB_PWR_OFFSET) // USB_USB_PWR + // Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO + // 0x00000020 [5] OVERCURR_DETECT_EN (0) + // 0x00000010 [4] OVERCURR_DETECT (0) + // 0x00000008 [3] VBUS_DETECT_OVERRIDE_EN (0) + // 0x00000004 [2] VBUS_DETECT (0) + // 0x00000002 [1] VBUS_EN_OVERRIDE_EN (0) + // 0x00000001 [0] VBUS_EN (0) + io_rw_32 pwr; + + _REG_(USB_USBPHY_DIRECT_OFFSET) // USB_USBPHY_DIRECT + // This register allows for direct control of the USB phy + // 0x02000000 [25] RX_DM_OVERRIDE (0) Override rx_dm value into controller + // 0x01000000 [24] RX_DP_OVERRIDE (0) Override rx_dp value into controller + // 0x00800000 [23] RX_DD_OVERRIDE (0) Override rx_dd value into controller + // 0x00400000 [22] DM_OVV (0) DM over voltage + // 0x00200000 [21] DP_OVV (0) DP over voltage + // 0x00100000 [20] DM_OVCN (0) DM overcurrent + // 0x00080000 [19] DP_OVCN (0) DP overcurrent + // 0x00040000 [18] RX_DM (0) DPM pin state + // 0x00020000 [17] RX_DP (0) DPP pin state + // 0x00010000 [16] RX_DD (0) Differential RX + // 0x00008000 [15] TX_DIFFMODE (0) TX_DIFFMODE=0: Single ended mode + + // 0x00004000 [14] TX_FSSLEW (0) TX_FSSLEW=0: Low speed slew rate + + // 0x00002000 [13] TX_PD (0) TX power down override (if override enable is set) + // 0x00001000 [12] RX_PD (0) RX power down override (if override enable is set) + // 0x00000800 [11] TX_DM (0) Output data + // 0x00000400 [10] TX_DP (0) Output data + // 0x00000200 [9] TX_DM_OE (0) Output enable + // 0x00000100 [8] TX_DP_OE (0) Output enable + // 0x00000040 [6] DM_PULLDN_EN (0) DM pull down enable + // 0x00000020 [5] DM_PULLUP_EN (0) DM pull up enable + // 0x00000010 [4] DM_PULLUP_HISEL (0) Enable the second DM pull up resistor + // 0x00000004 [2] DP_PULLDN_EN (0) DP pull down enable + // 0x00000002 [1] DP_PULLUP_EN (0) DP pull up enable + // 0x00000001 [0] DP_PULLUP_HISEL (0) Enable the second DP pull up resistor + io_rw_32 phy_direct; + + _REG_(USB_USBPHY_DIRECT_OVERRIDE_OFFSET) // USB_USBPHY_DIRECT_OVERRIDE + // Override enable for each control in usbphy_direct + // 0x00040000 [18] RX_DM_OVERRIDE_EN (0) + // 0x00020000 [17] RX_DP_OVERRIDE_EN (0) + // 0x00010000 [16] RX_DD_OVERRIDE_EN (0) + // 0x00008000 [15] TX_DIFFMODE_OVERRIDE_EN (0) + // 0x00001000 [12] DM_PULLUP_OVERRIDE_EN (0) + // 0x00000800 [11] TX_FSSLEW_OVERRIDE_EN (0) + // 0x00000400 [10] TX_PD_OVERRIDE_EN (0) + // 0x00000200 [9] RX_PD_OVERRIDE_EN (0) + // 0x00000100 [8] TX_DM_OVERRIDE_EN (0) + // 0x00000080 [7] TX_DP_OVERRIDE_EN (0) + // 0x00000040 [6] TX_DM_OE_OVERRIDE_EN (0) + // 0x00000020 [5] TX_DP_OE_OVERRIDE_EN (0) + // 0x00000010 [4] DM_PULLDN_EN_OVERRIDE_EN (0) + // 0x00000008 [3] DP_PULLDN_EN_OVERRIDE_EN (0) + // 0x00000004 [2] DP_PULLUP_EN_OVERRIDE_EN (0) + // 0x00000002 [1] DM_PULLUP_HISEL_OVERRIDE_EN (0) + // 0x00000001 [0] DP_PULLUP_HISEL_OVERRIDE_EN (0) + io_rw_32 phy_direct_override; + + _REG_(USB_USBPHY_TRIM_OFFSET) // USB_USBPHY_TRIM + // Used to adjust trim values of USB phy pull down resistors + // 0x00001f00 [12:8] DM_PULLDN_TRIM (0x1f) Value to drive to USB PHY + + // 0x0000001f [4:0] DP_PULLDN_TRIM (0x1f) Value to drive to USB PHY + + io_rw_32 phy_trim; + + _REG_(USB_LINESTATE_TUNING_OFFSET) // USB_LINESTATE_TUNING + // Used for debug only + // 0x00000f00 [11:8] SPARE_FIX (0x0) + // 0x00000080 [7] DEV_LS_WAKE_FIX (1) Device - exit suspend on any non-idle signalling, not... + // 0x00000040 [6] DEV_RX_ERR_QUIESCE (1) Device - suppress repeated errors until the device FSM... + // 0x00000020 [5] SIE_RX_CHATTER_SE0_FIX (1) RX - when recovering from line chatter or bitstuff... + // 0x00000010 [4] SIE_RX_BITSTUFF_FIX (1) RX - when a bitstuff error is signalled by rx_dasm,... + // 0x00000008 [3] DEV_BUFF_CONTROL_DOUBLE_READ_FIX (1) Device - the controller FSM performs two reads of the... + // 0x00000004 [2] MULTI_HUB_FIX (0) Host - increase inter-packet and turnaround timeouts to... + // 0x00000002 [1] LINESTATE_DELAY (0) Device/Host - add an extra 1-bit debounce of linestate sampling + // 0x00000001 [0] RCV_DELAY (0) Device - register the received data to account for hub... + io_rw_32 linestate_tuning; + + _REG_(USB_INTR_OFFSET) // USB_INTR + // Raw Interrupts + // 0x00800000 [23] EPX_STOPPED_ON_NAK (0) Source: NAK_POLL + // 0x00400000 [22] DEV_SM_WATCHDOG_FIRED (0) Source: DEV_SM_WATCHDOG + // 0x00200000 [21] ENDPOINT_ERROR (0) Source: SIE_STATUS + // 0x00100000 [20] RX_SHORT_PACKET (0) Source: SIE_STATUS + // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] SETUP_REQ (0) Device + // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host + // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes + // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes + // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS + // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS + // 0x00000400 [10] STALL (0) Source: SIE_STATUS + // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS + // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS + // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS + // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS + // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS + // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS + // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host + // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i + io_ro_32 intr; + + _REG_(USB_INTE_OFFSET) // USB_INTE + // Interrupt Enable + // 0x00800000 [23] EPX_STOPPED_ON_NAK (0) Source: NAK_POLL + // 0x00400000 [22] DEV_SM_WATCHDOG_FIRED (0) Source: DEV_SM_WATCHDOG + // 0x00200000 [21] ENDPOINT_ERROR (0) Source: SIE_STATUS + // 0x00100000 [20] RX_SHORT_PACKET (0) Source: SIE_STATUS + // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] SETUP_REQ (0) Device + // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host + // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes + // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes + // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS + // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS + // 0x00000400 [10] STALL (0) Source: SIE_STATUS + // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS + // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS + // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS + // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS + // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS + // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS + // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host + // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i + io_rw_32 inte; + + _REG_(USB_INTF_OFFSET) // USB_INTF + // Interrupt Force + // 0x00800000 [23] EPX_STOPPED_ON_NAK (0) Source: NAK_POLL + // 0x00400000 [22] DEV_SM_WATCHDOG_FIRED (0) Source: DEV_SM_WATCHDOG + // 0x00200000 [21] ENDPOINT_ERROR (0) Source: SIE_STATUS + // 0x00100000 [20] RX_SHORT_PACKET (0) Source: SIE_STATUS + // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] SETUP_REQ (0) Device + // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host + // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes + // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes + // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS + // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS + // 0x00000400 [10] STALL (0) Source: SIE_STATUS + // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS + // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS + // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS + // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS + // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS + // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS + // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host + // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i + io_rw_32 intf; + + _REG_(USB_INTS_OFFSET) // USB_INTS + // Interrupt status after masking & forcing + // 0x00800000 [23] EPX_STOPPED_ON_NAK (0) Source: NAK_POLL + // 0x00400000 [22] DEV_SM_WATCHDOG_FIRED (0) Source: DEV_SM_WATCHDOG + // 0x00200000 [21] ENDPOINT_ERROR (0) Source: SIE_STATUS + // 0x00100000 [20] RX_SHORT_PACKET (0) Source: SIE_STATUS + // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] SETUP_REQ (0) Device + // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host + // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes + // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes + // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS + // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS + // 0x00000400 [10] STALL (0) Source: SIE_STATUS + // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS + // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS + // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS + // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS + // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS + // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS + // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host + // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i + io_ro_32 ints; + + uint32_t _pad0[25]; + + _REG_(USB_SOF_TIMESTAMP_RAW_OFFSET) // USB_SOF_TIMESTAMP_RAW + // Device only + // 0x001fffff [20:0] SOF_TIMESTAMP_RAW (0x000000) + io_ro_32 sof_timestamp_raw; + + _REG_(USB_SOF_TIMESTAMP_LAST_OFFSET) // USB_SOF_TIMESTAMP_LAST + // Device only + // 0x001fffff [20:0] SOF_TIMESTAMP_LAST (0x000000) + io_ro_32 sof_timestamp_last; + + _REG_(USB_SM_STATE_OFFSET) // USB_SM_STATE + // 0x00000f00 [11:8] RX_DASM (0x0) + // 0x000000e0 [7:5] BC_STATE (0x0) + // 0x0000001f [4:0] STATE (0x00) + io_ro_32 sm_state; + + _REG_(USB_EP_TX_ERROR_OFFSET) // USB_EP_TX_ERROR + // TX error count for each endpoint + // 0xc0000000 [31:30] EP15 (0x0) + // 0x30000000 [29:28] EP14 (0x0) + // 0x0c000000 [27:26] EP13 (0x0) + // 0x03000000 [25:24] EP12 (0x0) + // 0x00c00000 [23:22] EP11 (0x0) + // 0x00300000 [21:20] EP10 (0x0) + // 0x000c0000 [19:18] EP9 (0x0) + // 0x00030000 [17:16] EP8 (0x0) + // 0x0000c000 [15:14] EP7 (0x0) + // 0x00003000 [13:12] EP6 (0x0) + // 0x00000c00 [11:10] EP5 (0x0) + // 0x00000300 [9:8] EP4 (0x0) + // 0x000000c0 [7:6] EP3 (0x0) + // 0x00000030 [5:4] EP2 (0x0) + // 0x0000000c [3:2] EP1 (0x0) + // 0x00000003 [1:0] EP0 (0x0) + io_rw_32 ep_tx_error; + + _REG_(USB_EP_RX_ERROR_OFFSET) // USB_EP_RX_ERROR + // RX error count for each endpoint + // 0x80000000 [31] EP15_SEQ (0) + // 0x40000000 [30] EP15_TRANSACTION (0) + // 0x20000000 [29] EP14_SEQ (0) + // 0x10000000 [28] EP14_TRANSACTION (0) + // 0x08000000 [27] EP13_SEQ (0) + // 0x04000000 [26] EP13_TRANSACTION (0) + // 0x02000000 [25] EP12_SEQ (0) + // 0x01000000 [24] EP12_TRANSACTION (0) + // 0x00800000 [23] EP11_SEQ (0) + // 0x00400000 [22] EP11_TRANSACTION (0) + // 0x00200000 [21] EP10_SEQ (0) + // 0x00100000 [20] EP10_TRANSACTION (0) + // 0x00080000 [19] EP9_SEQ (0) + // 0x00040000 [18] EP9_TRANSACTION (0) + // 0x00020000 [17] EP8_SEQ (0) + // 0x00010000 [16] EP8_TRANSACTION (0) + // 0x00008000 [15] EP7_SEQ (0) + // 0x00004000 [14] EP7_TRANSACTION (0) + // 0x00002000 [13] EP6_SEQ (0) + // 0x00001000 [12] EP6_TRANSACTION (0) + // 0x00000800 [11] EP5_SEQ (0) + // 0x00000400 [10] EP5_TRANSACTION (0) + // 0x00000200 [9] EP4_SEQ (0) + // 0x00000100 [8] EP4_TRANSACTION (0) + // 0x00000080 [7] EP3_SEQ (0) + // 0x00000040 [6] EP3_TRANSACTION (0) + // 0x00000020 [5] EP2_SEQ (0) + // 0x00000010 [4] EP2_TRANSACTION (0) + // 0x00000008 [3] EP1_SEQ (0) + // 0x00000004 [2] EP1_TRANSACTION (0) + // 0x00000002 [1] EP0_SEQ (0) + // 0x00000001 [0] EP0_TRANSACTION (0) + io_rw_32 ep_rx_error; + + _REG_(USB_DEV_SM_WATCHDOG_OFFSET) // USB_DEV_SM_WATCHDOG + // Watchdog that forces the device state machine to idle and raises an interrupt if the device... + // 0x00100000 [20] FIRED (0) + // 0x00080000 [19] RESET (0) Set to 1 to forcibly reset the device state machine on... + // 0x00040000 [18] ENABLE (0) + // 0x0003ffff [17:0] LIMIT (0x00000) + io_rw_32 dev_sm_watchdog; +} usb_hw_t; + +#define usb_hw ((usb_hw_t *)USBCTRL_REGS_BASE) +static_assert(sizeof (usb_hw_t) == 0x0118, ""); + +#endif // _HARDWARE_STRUCTS_USB_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/usb_dpram.h b/lib/pico-sdk/rp2350/hardware/structs/usb_dpram.h new file mode 100644 index 00000000..aaa4ec58 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/usb_dpram.h @@ -0,0 +1,128 @@ +/** + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_USB_DPRAM_H +#define _HARDWARE_STRUCTS_USB_DPRAM_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/usb.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_usb +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/usb.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + + +// 0-15 +#define USB_NUM_ENDPOINTS 16 + +// allow user to restrict number of endpoints available to save RAN +#ifndef USB_MAX_ENDPOINTS +#define USB_MAX_ENDPOINTS USB_NUM_ENDPOINTS +#endif + +// 1-15 +#define USB_HOST_INTERRUPT_ENDPOINTS (USB_NUM_ENDPOINTS - 1) + +// Endpoint buffer control bits +#define USB_BUF_CTRL_FULL 0x00008000u +#define USB_BUF_CTRL_LAST 0x00004000u +#define USB_BUF_CTRL_DATA0_PID 0x00000000u +#define USB_BUF_CTRL_DATA1_PID 0x00002000u +#define USB_BUF_CTRL_SEL 0x00001000u +#define USB_BUF_CTRL_STALL 0x00000800u +#define USB_BUF_CTRL_AVAIL 0x00000400u +#define USB_BUF_CTRL_LEN_MASK 0x000003FFu +#define USB_BUF_CTRL_LEN_LSB 0 + +// ep_inout_ctrl bits +#define EP_CTRL_ENABLE_BITS (1u << 31u) +#define EP_CTRL_DOUBLE_BUFFERED_BITS (1u << 30) +#define EP_CTRL_INTERRUPT_PER_BUFFER (1u << 29) +#define EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER (1u << 28) +#define EP_CTRL_INTERRUPT_ON_NAK (1u << 16) +#define EP_CTRL_INTERRUPT_ON_STALL (1u << 17) +#define EP_CTRL_BUFFER_TYPE_LSB 26u +#define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16u + +#define USB_DPRAM_SIZE 4096u + +// PICO_CONFIG: USB_DPRAM_MAX, Set amount of USB RAM used by USB system, min=0, max=4096, default=4096, group=hardware_usb +// Allow user to claim some of the USB RAM for themselves +#ifndef USB_DPRAM_MAX +#define USB_DPRAM_MAX USB_DPRAM_SIZE +#endif + +// Define maximum packet sizes +#define USB_MAX_ISO_PACKET_SIZE 1023 +#define USB_MAX_PACKET_SIZE 64 + +typedef struct { + // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses + volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets + + // Starts at ep1 + struct usb_device_dpram_ep_ctrl { + io_rw_32 in; + io_rw_32 out; + } ep_ctrl[USB_NUM_ENDPOINTS - 1]; + + // Starts at ep0 + struct usb_device_dpram_ep_buf_ctrl { + io_rw_32 in; + io_rw_32 out; + } ep_buf_ctrl[USB_NUM_ENDPOINTS]; + + // EP0 buffers are fixed. Assumes single buffered mode for EP0 + uint8_t ep0_buf_a[0x40]; + uint8_t ep0_buf_b[0x40]; + + // Rest of DPRAM can be carved up as needed + uint8_t epx_data[USB_DPRAM_MAX - 0x180]; +} usb_device_dpram_t; + +static_assert(sizeof(usb_device_dpram_t) == USB_DPRAM_MAX, ""); +static_assert(offsetof(usb_device_dpram_t, epx_data) == 0x180, ""); + +typedef struct { + // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses + volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets + + // Interrupt endpoint control 1 -> 15 + struct usb_host_dpram_ep_ctrl { + io_rw_32 ctrl; + io_rw_32 spare; + } int_ep_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; + + io_rw_32 epx_buf_ctrl; + io_rw_32 _spare0; + + // Interrupt endpoint buffer control + struct usb_host_dpram_ep_buf_ctrl { + io_rw_32 ctrl; + io_rw_32 spare; + } int_ep_buffer_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; + + io_rw_32 epx_ctrl; + + uint8_t _spare1[124]; + + // Should start at 0x180 + uint8_t epx_data[USB_DPRAM_MAX - 0x180]; +} usb_host_dpram_t; + +static_assert(sizeof(usb_host_dpram_t) == USB_DPRAM_MAX, ""); +static_assert(offsetof(usb_host_dpram_t, epx_data) == 0x180, ""); + +#define usb_dpram ((usb_device_dpram_t *)USBCTRL_DPRAM_BASE) +#define usbh_dpram ((usb_host_dpram_t *)USBCTRL_DPRAM_BASE) + +static_assert( USB_HOST_INTERRUPT_ENDPOINTS == 15, ""); + +#endif // _HARDWARE_STRUCTS_USB_DPRAM_H
\ No newline at end of file diff --git a/lib/pico-sdk/rp2350/hardware/structs/watchdog.h b/lib/pico-sdk/rp2350/hardware/structs/watchdog.h new file mode 100644 index 00000000..19c7bfae --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/watchdog.h @@ -0,0 +1,59 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_WATCHDOG_H +#define _HARDWARE_STRUCTS_WATCHDOG_H + +/** + * \file rp2350/watchdog.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/watchdog.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_watchdog +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/watchdog.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(WATCHDOG_CTRL_OFFSET) // WATCHDOG_CTRL + // Watchdog control + + // 0x80000000 [31] TRIGGER (0) Trigger a watchdog reset + // 0x40000000 [30] ENABLE (0) When not enabled the watchdog timer is paused + // 0x04000000 [26] PAUSE_DBG1 (1) Pause the watchdog timer when processor 1 is in debug mode + // 0x02000000 [25] PAUSE_DBG0 (1) Pause the watchdog timer when processor 0 is in debug mode + // 0x01000000 [24] PAUSE_JTAG (1) Pause the watchdog timer when JTAG is accessing the bus fabric + // 0x00ffffff [23:0] TIME (0x000000) Indicates the time in usec before a watchdog reset will... + io_rw_32 ctrl; + + _REG_(WATCHDOG_LOAD_OFFSET) // WATCHDOG_LOAD + // Load the watchdog timer + // 0x00ffffff [23:0] LOAD (0x000000) + io_wo_32 load; + + _REG_(WATCHDOG_REASON_OFFSET) // WATCHDOG_REASON + // Logs the reason for the last reset + // 0x00000002 [1] FORCE (0) + // 0x00000001 [0] TIMER (0) + io_ro_32 reason; + + // (Description copied from array index 0 register WATCHDOG_SCRATCH0 applies similarly to other array indexes) + _REG_(WATCHDOG_SCRATCH0_OFFSET) // WATCHDOG_SCRATCH0 + // Scratch register + // 0xffffffff [31:0] SCRATCH0 (0x00000000) + io_rw_32 scratch[8]; +} watchdog_hw_t; + +#define watchdog_hw ((watchdog_hw_t *)WATCHDOG_BASE) +static_assert(sizeof (watchdog_hw_t) == 0x002c, ""); + +#endif // _HARDWARE_STRUCTS_WATCHDOG_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/xip.h b/lib/pico-sdk/rp2350/hardware/structs/xip.h new file mode 100644 index 00000000..ee5cb236 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/xip.h @@ -0,0 +1,79 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_XIP_H +#define _HARDWARE_STRUCTS_XIP_H + +/** + * \file rp2350/xip.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/xip.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_xip +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/xip.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(XIP_CTRL_OFFSET) // XIP_CTRL + // Cache control register + // 0x00000800 [11] WRITABLE_M1 (0) If 1, enable writes to XIP memory window 1 (addresses... + // 0x00000400 [10] WRITABLE_M0 (0) If 1, enable writes to XIP memory window 0 (addresses... + // 0x00000200 [9] SPLIT_WAYS (0) When 1, route all cached+Secure accesses to way 0 of the... + // 0x00000100 [8] MAINT_NONSEC (0) When 0, Non-secure accesses to the cache maintenance... + // 0x00000080 [7] NO_UNTRANSLATED_NONSEC (1) When 1, Non-secure accesses to the uncached,... + // 0x00000040 [6] NO_UNTRANSLATED_SEC (0) When 1, Secure accesses to the uncached, untranslated... + // 0x00000020 [5] NO_UNCACHED_NONSEC (0) When 1, Non-secure accesses to the uncached window... + // 0x00000010 [4] NO_UNCACHED_SEC (0) When 1, Secure accesses to the uncached window... + // 0x00000008 [3] POWER_DOWN (0) When 1, the cache memories are powered down + // 0x00000002 [1] EN_NONSECURE (1) When 1, enable the cache for Non-secure accesses + // 0x00000001 [0] EN_SECURE (1) When 1, enable the cache for Secure accesses + io_rw_32 ctrl; + + uint32_t _pad0; + + _REG_(XIP_STAT_OFFSET) // XIP_STAT + // 0x00000004 [2] FIFO_FULL (0) When 1, indicates the XIP streaming FIFO is completely full + // 0x00000002 [1] FIFO_EMPTY (1) When 1, indicates the XIP streaming FIFO is completely empty + io_ro_32 stat; + + _REG_(XIP_CTR_HIT_OFFSET) // XIP_CTR_HIT + // Cache Hit counter + // 0xffffffff [31:0] CTR_HIT (0x00000000) A 32 bit saturating counter that increments upon each... + io_rw_32 ctr_hit; + + _REG_(XIP_CTR_ACC_OFFSET) // XIP_CTR_ACC + // Cache Access counter + // 0xffffffff [31:0] CTR_ACC (0x00000000) A 32 bit saturating counter that increments upon each... + io_rw_32 ctr_acc; + + _REG_(XIP_STREAM_ADDR_OFFSET) // XIP_STREAM_ADDR + // FIFO stream address + // 0xfffffffc [31:2] STREAM_ADDR (0x00000000) The address of the next word to be streamed from flash... + io_rw_32 stream_addr; + + _REG_(XIP_STREAM_CTR_OFFSET) // XIP_STREAM_CTR + // FIFO stream control + // 0x003fffff [21:0] STREAM_CTR (0x000000) Write a nonzero value to start a streaming read + io_rw_32 stream_ctr; + + _REG_(XIP_STREAM_FIFO_OFFSET) // XIP_STREAM_FIFO + // FIFO stream data + // 0xffffffff [31:0] STREAM_FIFO (0x00000000) Streamed data is buffered here, for retrieval by the system DMA + io_ro_32 stream_fifo; +} xip_ctrl_hw_t; + +#define xip_ctrl_hw ((xip_ctrl_hw_t *)XIP_CTRL_BASE) +static_assert(sizeof (xip_ctrl_hw_t) == 0x0020, ""); + +#endif // _HARDWARE_STRUCTS_XIP_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/xip_aux.h b/lib/pico-sdk/rp2350/hardware/structs/xip_aux.h new file mode 100644 index 00000000..1e1caf8c --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/xip_aux.h @@ -0,0 +1,51 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_XIP_AUX_H +#define _HARDWARE_STRUCTS_XIP_AUX_H + +/** + * \file rp2350/xip_aux.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/xip_aux.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_xip_aux +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/xip_aux.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(XIP_AUX_STREAM_OFFSET) // XIP_AUX_STREAM + // Read the XIP stream FIFO (fast bus access to XIP_CTRL_STREAM_FIFO) + // 0xffffffff [31:0] STREAM (0x00000000) + io_ro_32 stream; + + _REG_(XIP_AUX_QMI_DIRECT_TX_OFFSET) // XIP_AUX_QMI_DIRECT_TX + // Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX) + // 0x00100000 [20] NOPUSH (0) Inhibit the RX FIFO push that would correspond to this... + // 0x00080000 [19] OE (0) Output enable (active-high) + // 0x00040000 [18] DWIDTH (0) Data width + // 0x00030000 [17:16] IWIDTH (0x0) Configure whether this FIFO record is transferred with... + // 0x0000ffff [15:0] DATA (0x0000) Data pushed here will be clocked out falling edges of... + io_wo_32 qmi_direct_tx; + + _REG_(XIP_AUX_QMI_DIRECT_RX_OFFSET) // XIP_AUX_QMI_DIRECT_RX + // Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX) + // 0x0000ffff [15:0] QMI_DIRECT_RX (0x0000) With each byte clocked out on the serial interface, one... + io_ro_32 qmi_direct_rx; +} xip_aux_hw_t; + +#define xip_aux_hw ((xip_aux_hw_t *)XIP_AUX_BASE) +static_assert(sizeof (xip_aux_hw_t) == 0x000c, ""); + +#endif // _HARDWARE_STRUCTS_XIP_AUX_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/xip_ctrl.h b/lib/pico-sdk/rp2350/hardware/structs/xip_ctrl.h new file mode 100644 index 00000000..c31569b6 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/xip_ctrl.h @@ -0,0 +1,11 @@ +/** + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// Support old header for compatibility (and if included, support old variable name) +#include "hardware/structs/xip.h" +#define XIP_STAT_FIFO_FULL XIP_STAT_FIFO_FULL_BITS +#define XIP_STAT_FIFO_EMPTY XIP_STAT_FIFO_EMPTY_BITS +#define XIP_STAT_FLUSH_RDY XIP_STAT_FLUSH_READY_BITS diff --git a/lib/pico-sdk/rp2350/hardware/structs/xosc.h b/lib/pico-sdk/rp2350/hardware/structs/xosc.h new file mode 100644 index 00000000..dca0c05e --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/xosc.h @@ -0,0 +1,64 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_XOSC_H +#define _HARDWARE_STRUCTS_XOSC_H + +/** + * \file rp2350/xosc.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/xosc.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_xosc +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/xosc.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/// \tag::xosc_hw[] +typedef struct { + _REG_(XOSC_CTRL_OFFSET) // XOSC_CTRL + // Crystal Oscillator Control + // 0x00fff000 [23:12] ENABLE (-) On power-up this field is initialised to DISABLE and the... + // 0x00000fff [11:0] FREQ_RANGE (-) The 12-bit code is intended to give some protection... + io_rw_32 ctrl; + + _REG_(XOSC_STATUS_OFFSET) // XOSC_STATUS + // Crystal Oscillator Status + // 0x80000000 [31] STABLE (0) Oscillator is running and stable + // 0x01000000 [24] BADWRITE (0) An invalid value has been written to CTRL_ENABLE or... + // 0x00001000 [12] ENABLED (-) Oscillator is enabled but not necessarily running and... + // 0x00000003 [1:0] FREQ_RANGE (-) The current frequency range setting + io_rw_32 status; + + _REG_(XOSC_DORMANT_OFFSET) // XOSC_DORMANT + // Crystal Oscillator pause control + // 0xffffffff [31:0] DORMANT (-) This is used to save power by pausing the XOSC + + io_rw_32 dormant; + + _REG_(XOSC_STARTUP_OFFSET) // XOSC_STARTUP + // Controls the startup delay + // 0x00100000 [20] X4 (-) Multiplies the startup_delay by 4, just in case + // 0x00003fff [13:0] DELAY (-) in multiples of 256*xtal_period + io_rw_32 startup; + + _REG_(XOSC_COUNT_OFFSET) // XOSC_COUNT + // A down counter running at the XOSC frequency which counts to zero and stops. + // 0x0000ffff [15:0] COUNT (0x0000) + io_rw_32 count; +} xosc_hw_t; +/// \end::xosc_hw[] + +#define xosc_hw ((xosc_hw_t *)XOSC_BASE) +static_assert(sizeof (xosc_hw_t) == 0x0014, ""); + +#endif // _HARDWARE_STRUCTS_XOSC_H + |