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* stm32: Allow 32KiB bootloader to be specified for all STM32F4 buildsKevin O'Connor2022-03-141-1/+1
| | | | | | Reported by @GerogeFu. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Clarify CCIPR2 setting in stm32g0.cKevin O'Connor2022-03-111-1/+1
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Simplify CCIPR2 register assignment on stm32g0Kevin O'Connor2022-03-091-5/+2
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: USB clock source from PLLQCLK on stm32g0 (#5341)BIGTREETECH2022-03-091-6/+4
| | | Signed-off-by: Alan.Ma from BigTreeTech <tech@biqu3d.com>
* lpc176x: Fix serial ordering of initializationKevin O'Connor2022-03-011-1/+1
| | | | | | | The serial device needs to be enabled before setting the DLAB bit. This prevented UART3 from working. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Clear SPE flag on a change to SPI CR1 registerKevin O'Connor2022-02-101-0/+6
| | | | | | | | | The stm32 specs indicate that the SPE bit must be cleared before changing the CPHA or CPOL bits. Reported by @cbc02009 and @bigtreetech. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Wait for transmission to complete before returning from spi_transfer()Kevin O'Connor2022-02-101-2/+5
| | | | | | | | | | | | | It's possible for the SCLK pin to still be updating even after the last byte of data has been read from the receive pin. (In particular in spi mode 0 and 1.) Exiting early from spi_transfer() in this case could result in the CS pin being raised before the final updates to SCLK pin. Add an additional wait at the end of spi_transfer() to avoid this issue. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Fix ADC on stm32h7 (#5239)adelyser2022-02-061-1/+3
| | | | | | Don't reset the ADC peripheral if the clock is already enabled. Fixes #5236 Signed-off-by: Aaron DeLyser <bluwolf@gmail.com>
* flash_usb: use sudo for rp2040 flashingLasse Dalegaard2022-01-311-1/+1
| | | | | | | | | | | The rp2040 can be flashed without sudo when using udev rules to give the user permission, but in a standard configuration sudo is required. Here we make it possible for flash_usb to use sudo for the rp2040 target, and make it the default when using `make flash` for the rp2040. As for other targets, one can set `NOSUDO=1` to not call through sudo. Signed-off-by: Lasse Dalegaard <dalegaard@gmail.com>
* stm32: Add remap CAN to PD0/PD1 for stm32f103 (#5173)Sergey15602022-01-262-1/+4
| | | Signed-off-by: Sergey Terentiev <sergey@terentiev.me>
* rp2040: implement I2CLasse Dalegaard2022-01-124-0/+227
| | | | | | | This implements I2C for the rp2040 target. All output groupings of both I2C blocks are available for use. Signed-off-by: Lasse Dalegaard <dalegaard@gmail.com>
* stm32: Update Kconfig as CANBUS isn't available on stm32f401Kevin O'Connor2022-01-071-8/+15
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* rp2040: add make flash supportLasse Dalegaard2022-01-061-6/+7
| | | | | | | | | | | | | | | | This adds `make flash` support for the rp2040 target. Flashing is performed using a custom `rp2040_flash` tool that uses the PICOBOOT protocol. Root is not required. The user specifies the serial device of the rp2040 they wish to flash as the device. This device is reset into bootsel mode and `rp2040_flash` is invoked on the original USB device path. If the device is already in bootloader mode, the user can specify 'first' as `FLASH_DEVICE` which will simply invoke `rp2040_flash` with no bus/address options. Signed-off-by: Lasse Dalegaard <dalegaard@gmail.com>
* stm32: Unify enable_pclock() codeKevin O'Connor2021-12-308-238/+125
| | | | | | | | | Unify the handling of the enable_pclock() and is_enabled_pclock() code across all stm32 chips. All chips will now perform a peripheral reset on enable_pclock() (this is a change for stm32f0 and stm32h7). The enable_pclock() code will now also disable irqs during the enable. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Fix the GPIO register for stm32h7 (#5077)adelyser2021-12-291-3/+3
| | | Signed-off-by: Aaron DeLyser <bluwolf@gmail.com>
* stm32: Fix ADC on stm32f042Kevin O'Connor2021-12-241-0/+1
| | | | | | It seems the stm32f042 chip needs a small delay during ADC enable. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Enable SPI support on stm32g0Kevin O'Connor2021-12-232-4/+8
| | | | | Signed-off-by: Alan.Ma from BigTreeTech <tech@biqu3d.com> Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Enable ADC support on stm32g0Kevin O'Connor2021-12-233-12/+51
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Rework register access on stm32f0_adc.cKevin O'Connor2021-12-231-34/+25
| | | | | | | | | | | Avoid read-modify-write operations where possible. The register values are in a known state so prefer absolute writes. Improve handling of race conditions with hardware updates. Remove the adc reference from "struct gpio_adc" as it is a constant. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Minor whitespace changes to stm32f0_adc.cKevin O'Connor2021-12-231-12/+8
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Enable I2C on stm32g0Kevin O'Connor2021-12-232-1/+2
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Add support for USB on stm32g0Kevin O'Connor2021-12-232-21/+70
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Rework USB transfer memory layout in usbfs.cKevin O'Connor2021-12-231-46/+55
| | | | | | | | | Use a fixed layout for the USB transfer memory and remove the ep_mem struct definition. This is in preparation for stm32g0 support. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Fix buffer size calculation in usbfs.cKevin O'Connor2021-12-231-1/+1
| | | | | | When the buffers are over 32 bytes, a block count of 1 starts at 0. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Simplify irq declaration in usbfs.cKevin O'Connor2021-12-231-11/+11
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Initial support for stm32g0Kevin O'Connor2021-12-236-8/+253
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Enable optimized gpio_clock_enable() function on stm32h7Kevin O'Connor2021-12-231-1/+3
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Reorganize stm32h7.c into major code blocksKevin O'Connor2021-12-231-10/+21
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Remove USB boot stubs from stm32h7.cKevin O'Connor2021-12-231-8/+0
| | | | | | | The USB dfu bootloader wasn't enabled on stm32h7, so remove the copy-and-paste code stubs for it. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Fix DFU entry point on stm32f072Kevin O'Connor2021-12-231-0/+2
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Reorganize usb bootloader code in stm32f0.cKevin O'Connor2021-12-231-38/+65
| | | | | | Reorganize stm32f0.c into major code blocks. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Reorganize usb bootloader code in stm32f4.cKevin O'Connor2021-12-231-30/+63
| | | | | | Reorganize stm32f4.c into major code blocks. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Reorganize code in stm32f1.cKevin O'Connor2021-12-231-47/+82
| | | | | | Reorganize stm32f1.c into major code blocks. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Add new gpioperiph.c file for gpio_peripheral() codeKevin O'Connor2021-12-235-83/+45
| | | | | | | | The gpio_peripheral() code is the same in stm32f0.c, stm32f4.c, and stm32h7.c. Move that function to a new gpioperiph.c file to avoid code duplication. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Add option to disable SWD on GigaDevice STM32F103 clonesKevin O'Connor2021-11-252-2/+17
| | | | | | Tested by @FotoFieber. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Add USBOTG support to stm32h7adelyser2021-11-213-23/+81
| | | | | Signed-off-by: Aaron DeLyser <bluwolf@gmail.com> Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Enable SPI on stm32h7Kevin O'Connor2021-11-201-1/+1
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Add stm32h7 SPI support (#4850)adelyser2021-11-203-3/+159
| | | Signed-off-by: Aaron DeLyser <bluwolf@gmail.com>
* stm32: Add STM32H743 supportadelyser2021-11-201-3/+17
| | | | | Signed-off-by: Aaron DeLyser <bluwolf@gmail.com> Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Limit stm32h7 chips to 400MhzKevin O'Connor2021-11-201-1/+1
| | | | | | | | Don't go above 400Mhz as otherwise it causes 32bit rollover issues. (Parts of the code expect a rollover will not occur faster than 10 seconds.) Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* atsam: Add get_pclock_frequency() helper functionKevin O'Connor2021-11-207-12/+22
| | | | | | Add get_pclock_frequency() and use it to calculate peripheral clocks. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* atsam: Fix I2C bitrateAlex Maclean2021-11-201-2/+2
| | | | | | | Multiplying the desired bitrate by 4 results in half the desired period and thus twice the desired bitrate. Signed-off-by: Alex Maclean <monkeh@monkeh.net>
* atsam: Don't enable USB FS clock on SAM3Alex Maclean2021-11-201-2/+0
| | | | | | | This clock is only needed for low-power operation mode, and wasn't correctly configured anyway (should be 48MHz). Signed-off-by: Alex Maclean <monkeh@monkeh.net>
* atsam: Don't bother disabling DMA for UARTAlex Maclean2021-11-201-1/+0
| | | | | | PDC is not enabled by default so no need to disable it Signed-off-by: Alex Maclean <monkeh@monkeh.net>
* atsam: Don't set unused bits in UARTAlex Maclean2021-11-201-2/+1
| | | | | | | The CHRL and NBSTOP bits are not present in the UART peripheral, only the USART. Signed-off-by: Alex Maclean <monkeh@monkeh.net>
* stm32: Add UART4 to stm32h7 (#4848)adelyser2021-11-191-2/+13
| | | Signed-off-by: Aaron DeLyser <bluwolf@gmail.com>
* sched: Move last_insert check for improved gcc code layoutKevin O'Connor2021-11-091-2/+2
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32f4: reset peripherals in enable_pcclock()Eric Callahan2021-11-081-0/+7
| | | | | | | Reset peripherals to after enabling to clear stale registers set by the bootloader. Signed-off-by: Eric Callahan <arksine.code@gmail.com>
* stm32f4: reset peripheral clocks on initEric Callahan2021-11-081-0/+6
| | | | Signed-off-by: Eric Callahan <arksine.code@gmail.com>
* mcu: Make a minor change to the protocol to require mcu updateKevin O'Connor2021-11-061-2/+2
| | | | | | | | Commit 9ecddd1b fixed a serious error (introduced in 7d95a004). Force a protocol version change so users are aware of the need to update the mcu code. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
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