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| author | BIGTREETECH <38851044+bigtreetech@users.noreply.github.com> | 2022-03-10 02:11:04 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-03-09 13:11:04 -0500 |
| commit | d75154d695efb1338cbfff061d226c4f384d127b (patch) | |
| tree | 1431e1cd8a430f9ded602a0cf5524a07f0a350c7 /src | |
| parent | c721c20c97c32c33872007f28e4a13afc6a5b352 (diff) | |
| download | kutter-d75154d695efb1338cbfff061d226c4f384d127b.tar.gz kutter-d75154d695efb1338cbfff061d226c4f384d127b.tar.xz kutter-d75154d695efb1338cbfff061d226c4f384d127b.zip | |
stm32: USB clock source from PLLQCLK on stm32g0 (#5341)
Signed-off-by: Alan.Ma from BigTreeTech <tech@biqu3d.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/stm32/stm32g0.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/src/stm32/stm32g0.c b/src/stm32/stm32g0.c index 3d3cca69..ee0230f4 100644 --- a/src/stm32/stm32g0.c +++ b/src/stm32/stm32g0.c @@ -81,7 +81,8 @@ clock_setup(void) } pllcfgr |= (pll_freq/pll_base) << RCC_PLLCFGR_PLLN_Pos; pllcfgr |= (pll_freq/CONFIG_CLOCK_FREQ - 1) << RCC_PLLCFGR_PLLR_Pos; - RCC->PLLCFGR = pllcfgr | RCC_PLLCFGR_PLLREN; + pllcfgr |= (pll_freq/FREQ_USB - 1) << RCC_PLLCFGR_PLLQ_Pos; + RCC->PLLCFGR = pllcfgr | RCC_PLLCFGR_PLLREN | RCC_PLLCFGR_PLLQEN; RCC->CR |= RCC_CR_PLLON; // Wait for PLL lock @@ -95,11 +96,8 @@ clock_setup(void) // Enable USB clock if (CONFIG_USBSERIAL) { - RCC->CR |= RCC_CR_HSI48ON; - while (!(RCC->CR & RCC_CR_HSI48RDY)) - ; - enable_pclock(CRS_BASE); - CRS->CR |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN; + // PLLQCLK + RCC->CCIPR2 |= RCC_CCIPR2_USBSEL_1; } } |