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| author | Kevin O'Connor <kevin@koconnor.net> | 2025-05-31 17:00:18 -0400 |
|---|---|---|
| committer | Kevin O'Connor <kevin@koconnor.net> | 2025-06-02 13:15:53 -0400 |
| commit | 105ce35e1ba813b7ebe1be2a87fd852a5f7b66f5 (patch) | |
| tree | 0c0c55df7baba74b5eaf4f400744cc4e2e9a93dc /src/stm32/stm32f4.c | |
| parent | c0ca4c5cc7379046221a250ce9c90f514e85ca7e (diff) | |
| download | kutter-105ce35e1ba813b7ebe1be2a87fd852a5f7b66f5.tar.gz kutter-105ce35e1ba813b7ebe1be2a87fd852a5f7b66f5.tar.xz kutter-105ce35e1ba813b7ebe1be2a87fd852a5f7b66f5.zip | |
stm32: Add comments on PLL frequency requirements to clock setup code
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src/stm32/stm32f4.c')
| -rw-r--r-- | src/stm32/stm32f4.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/stm32/stm32f4.c b/src/stm32/stm32f4.c index fd3eb0ba..e5beabee 100644 --- a/src/stm32/stm32f4.c +++ b/src/stm32/stm32f4.c @@ -57,6 +57,11 @@ gpio_clock_enable(GPIO_TypeDef *regs) RCC->AHB1ENR; } +// PLL (f207) input: 0.95 to 2.1Mhz, vco: 192 to 432Mhz, output: 24 to 120Mhz +// PLL (f401) input: 0.95 to 2.1Mhz, vco: 192 to 432Mhz, output: 24 to 84Mhz +// PLL (f405/7) input: 0.95 to 2.1Mhz, vco: 100 to 432Mhz, output: 24 to 168Mhz +// PLL (f446) input: 0.95 to 2.1Mhz, vco: 100 to 432Mhz, output: 12.5 to 180Mhz + #if !CONFIG_STM32_CLOCK_REF_INTERNAL DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PH0,PH1"); #endif |