9 files changed, 22 insertions, 0 deletions
diff --git a/src/rp2040/main.c b/src/rp2040/main.c
index 607498d1..97fa5eb8 100644
--- a/src/rp2040/main.c
+++ b/src/rp2040/main.c
@@ -97,6 +97,8 @@ get_pclock_frequency(uint32_t reset_bit)
     return FREQ_SYS;
 }
 
+// PLL (rp2xxx) input: 5 to 100Mhz, vco: 750 to 1600Mhz
+
 static void
 xosc_setup(void)
 {
diff --git a/src/stm32/stm32f0.c b/src/stm32/stm32f0.c
index d7af831e..b0691c64 100644
--- a/src/stm32/stm32f0.c
+++ b/src/stm32/stm32f0.c
@@ -52,6 +52,8 @@ gpio_clock_enable(GPIO_TypeDef *regs)
     RCC->AHBENR;
 }
 
+// PLL (f0) input: 1 to 24Mhz, output: 16 to 48Mhz
+
 #if !CONFIG_STM32_CLOCK_REF_INTERNAL
 DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PF0,PF1");
 #endif
diff --git a/src/stm32/stm32f1.c b/src/stm32/stm32f1.c
index 9d3c3b97..0e4cb782 100644
--- a/src/stm32/stm32f1.c
+++ b/src/stm32/stm32f1.c
@@ -51,6 +51,8 @@ gpio_clock_enable(GPIO_TypeDef *regs)
     RCC->APB2ENR;
 }
 
+// PLL (f103) input: 1 to 25Mhz, output: 16 to 72Mhz
+
 // Main clock setup called at chip startup
 static void
 clock_setup(void)
diff --git a/src/stm32/stm32f4.c b/src/stm32/stm32f4.c
index fd3eb0ba..e5beabee 100644
--- a/src/stm32/stm32f4.c
+++ b/src/stm32/stm32f4.c
@@ -57,6 +57,11 @@ gpio_clock_enable(GPIO_TypeDef *regs)
     RCC->AHB1ENR;
 }
 
+// PLL (f207) input: 0.95 to 2.1Mhz, vco: 192 to 432Mhz, output: 24 to 120Mhz
+// PLL (f401) input: 0.95 to 2.1Mhz, vco: 192 to 432Mhz, output: 24 to 84Mhz
+// PLL (f405/7) input: 0.95 to 2.1Mhz, vco: 100 to 432Mhz, output: 24 to 168Mhz
+// PLL (f446) input: 0.95 to 2.1Mhz, vco: 100 to 432Mhz, output: 12.5 to 180Mhz
+
 #if !CONFIG_STM32_CLOCK_REF_INTERNAL
 DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PH0,PH1");
 #endif
diff --git a/src/stm32/stm32f7.c b/src/stm32/stm32f7.c
index f6f27618..c86bca3d 100644
--- a/src/stm32/stm32f7.c
+++ b/src/stm32/stm32f7.c
@@ -57,6 +57,8 @@ gpio_clock_enable(GPIO_TypeDef *regs)
     RCC->AHB1ENR;
 }
 
+// PLL (f765) input: 0.95 to 2.1Mhz, vco: 100 to 432Mhz, output: 24 to 216Mhz
+
 #if !CONFIG_STM32_CLOCK_REF_INTERNAL
 DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PH0,PH1");
 #endif
diff --git a/src/stm32/stm32g0.c b/src/stm32/stm32g0.c
index 819a5edd..d02d5728 100644
--- a/src/stm32/stm32g0.c
+++ b/src/stm32/stm32g0.c
@@ -97,6 +97,8 @@ gpio_clock_enable(GPIO_TypeDef *regs)
     RCC->IOPENR;
 }
 
+// PLL (g0) input: 2.66 to 16Mhz, vco: 96 to 344Mhz, output: 12 to 64Mhz
+
 #if !CONFIG_STM32_CLOCK_REF_INTERNAL
 DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PF0,PF1");
 #endif
diff --git a/src/stm32/stm32g4.c b/src/stm32/stm32g4.c
index 02c9656f..3301071e 100644
--- a/src/stm32/stm32g4.c
+++ b/src/stm32/stm32g4.c
@@ -76,6 +76,8 @@ gpio_clock_enable(GPIO_TypeDef *regs)
     RCC->AHB2ENR;
 }
 
+// PLL (g4) input: 2.66 to 16Mhz, vco: 96 to 344Mhz, output: 2.06 to 170Mhz
+
 #if !CONFIG_STM32_CLOCK_REF_INTERNAL
 DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PF0,PF1");
 #endif
diff --git a/src/stm32/stm32h7.c b/src/stm32/stm32h7.c
index f65eeed7..c6da0eac 100644
--- a/src/stm32/stm32h7.c
+++ b/src/stm32/stm32h7.c
@@ -82,6 +82,9 @@ gpio_clock_enable(GPIO_TypeDef *regs)
     RCC->AHB4ENR;
 }
 
+// PLL1 (h723) input: 2 to 16Mhz, vco: 192 to 836Mhz, output: 1.5 to 550Mhz
+// PLL1 (h743v) input: 2 to 16Mhz, vco: 192 to 960Mhz, output: 1.5 to 480Mhz
+
 #if !CONFIG_STM32_CLOCK_REF_INTERNAL
 DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PH0,PH1");
 #endif
diff --git a/src/stm32/stm32l4.c b/src/stm32/stm32l4.c
index ae099d6b..3100a741 100644
--- a/src/stm32/stm32l4.c
+++ b/src/stm32/stm32l4.c
@@ -68,6 +68,8 @@ gpio_clock_enable(GPIO_TypeDef *regs)
     RCC->AHB2ENR;
 }
 
+// PLL (L412) input: 4 to 16Mhz, vco: 96 to 344Mhz, output: 12 to 80Mhz
+
 #if !CONFIG_STM32_CLOCK_REF_INTERNAL
 DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PC14,PC15");
 #endif