From 105ce35e1ba813b7ebe1be2a87fd852a5f7b66f5 Mon Sep 17 00:00:00 2001 From: Kevin O'Connor Date: Sat, 31 May 2025 17:00:18 -0400 Subject: stm32: Add comments on PLL frequency requirements to clock setup code Signed-off-by: Kevin O'Connor --- src/stm32/stm32f4.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/stm32/stm32f4.c') diff --git a/src/stm32/stm32f4.c b/src/stm32/stm32f4.c index fd3eb0ba..e5beabee 100644 --- a/src/stm32/stm32f4.c +++ b/src/stm32/stm32f4.c @@ -57,6 +57,11 @@ gpio_clock_enable(GPIO_TypeDef *regs) RCC->AHB1ENR; } +// PLL (f207) input: 0.95 to 2.1Mhz, vco: 192 to 432Mhz, output: 24 to 120Mhz +// PLL (f401) input: 0.95 to 2.1Mhz, vco: 192 to 432Mhz, output: 24 to 84Mhz +// PLL (f405/7) input: 0.95 to 2.1Mhz, vco: 100 to 432Mhz, output: 24 to 168Mhz +// PLL (f446) input: 0.95 to 2.1Mhz, vco: 100 to 432Mhz, output: 12.5 to 180Mhz + #if !CONFIG_STM32_CLOCK_REF_INTERNAL DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PH0,PH1"); #endif -- cgit v1.2.3-70-g09d2