diff options
| -rw-r--r-- | reg/gpio.h | 130 | ||||
| -rw-r--r-- | reg/port.h | 91 |
2 files changed, 131 insertions, 90 deletions
@@ -4,68 +4,90 @@ #include <reg/regdefs.h> // Port Data Output Register -#define GPIOA_PDOR REG_32(0x400FF000) -// Port Set Output Register -#define GPIOA_PSOR REG_32(0x400FF004) -// Port Clear Output Register -#define GPIOA_PCOR REG_32(0x400FF008) -// Port Toggle Output Register -#define GPIOA_PTOR REG_32(0x400FF00C) -// Port Data Input Register -#define GPIOA_PDIR REG_32(0x400FF010) -// Port Data Direction Register -#define GPIOA_PDDR REG_32(0x400FF014) +#define GPIO_PDOR(base) REG_32((base) + 0x00) +enum { + PDOR_PDO = 0, // Port Data Output +#define PDOR_PDO_M REG_32_M(PDOR_PDO, 32) +}; -// Port Data Output Register -#define GPIOB_PDOR REG_32(0x400FF040) // Port Set Output Register -#define GPIOB_PSOR REG_32(0x400FF044) -// Port Clear Output Register -#define GPIOB_PCOR REG_32(0x400FF048) -// Port Toggle Output Register -#define GPIOB_PTOR REG_32(0x400FF04C) -// Port Data Input Register -#define GPIOB_PDIR REG_32(0x400FF050) -// Port Data Direction Register -#define GPIOB_PDDR REG_32(0x400FF054) +#define GPIO_PSOR(base) REG_32((base) + 0x04) +enum { + PSOR_PTSO = 0, // Port Set Output +#define PSOR_PTSO_M REG_32_M(PSOR_PTSO, 32) +}; -// Port Data Output Register -#define GPIOC_PDOR REG_32(0x400FF080) -// Port Set Output Register -#define GPIOC_PSOR REG_32(0x400FF084) // Port Clear Output Register -#define GPIOC_PCOR REG_32(0x400FF088) -// Port Toggle Output Register -#define GPIOC_PTOR REG_32(0x400FF08C) -// Port Data Input Register -#define GPIOC_PDIR REG_32(0x400FF090) -// Port Data Direction Register -#define GPIOC_PDDR REG_32(0x400FF094) +#define GPIO_PCOR(base) REG_32((base) + 0x08) +enum { + PCOR_PTCO = 0, // Port Clear Output +#define PCOR_PTCO_M REG_32_M(PCOR_PTCO, 32) +}; -// Port Data Output Register -#define GPIOD_PDOR REG_32(0x400FF0C0) -// Port Set Output Register -#define GPIOD_PSOR REG_32(0x400FF0C4) -// Port Clear Output Register -#define GPIOD_PCOR REG_32(0x400FF0C8) // Port Toggle Output Register -#define GPIOD_PTOR REG_32(0x400FF0CC) -// Port Data Input Register -#define GPIOD_PDIR REG_32(0x400FF0D0) -// Port Data Direction Register -#define GPIOD_PDDR REG_32(0x400FF0D4) +#define GPIO_PTOR(base) REG_32((base) + 0x0C) +enum { + PTOR_PTTO = 0, // Port Toggle Output +#define PTOR_PTTO_M REG_32_M(PTOR_PTTO, 32) +}; -// Port Data Output Register -#define GPIOE_PDOR REG_32(0x400FF100) -// Port Set Output Register -#define GPIOE_PSOR REG_32(0x400FF104) -// Port Clear Output Register -#define GPIOE_PCOR REG_32(0x400FF108) -// Port Toggle Output Register -#define GPIOE_PTOR REG_32(0x400FF10C) // Port Data Input Register -#define GPIOE_PDIR REG_32(0x400FF110) +#define GPIO_PDIR(base) REG_32((base) + 0x10) +enum { + PDIR_PDI = 0, // Port Data Input +#define PDIR_PDI_M REG_32_M(PDIR_PDI, 32) +}; + // Port Data Direction Register -#define GPIOE_PDDR REG_32(0x400FF114) +#define GPIO_PDDR(base) REG_32((base) + 0x14) +enum { + PDDR_PDD = 0, // Port Data Direction +#define PDDR_PDD_M REG_32_M(PDDR_PDD, 32) +}; + +#define GPIOA_BASE 0x400FF000 + +#define GPIOA_PDOR GPIO_PDOR(GPIOA_BASE) +#define GPIOA_PSOR GPIO_PSOR(GPIOA_BASE) +#define GPIOA_PCOR GPIO_PCOR(GPIOA_BASE) +#define GPIOA_PTOR GPIO_PTOR(GPIOA_BASE) +#define GPIOA_PDIR GPIO_PDIR(GPIOA_BASE) +#define GPIOA_PDDR GPIO_PDDR(GPIOA_BASE) + +#define GPIOB_BASE 0x400FF040 + +#define GPIOB_PDOR GPIO_PDOR(GPIOB_BASE) +#define GPIOB_PSOR GPIO_PSOR(GPIOB_BASE) +#define GPIOB_PCOR GPIO_PCOR(GPIOB_BASE) +#define GPIOB_PTOR GPIO_PTOR(GPIOB_BASE) +#define GPIOB_PDIR GPIO_PDIR(GPIOB_BASE) +#define GPIOB_PDDR GPIO_PDDR(GPIOB_BASE) + +#define GPIOC_BASE 0x400FF080 + +#define GPIOC_PDOR GPIO_PDOR(GPIOC_BASE) +#define GPIOC_PSOR GPIO_PSOR(GPIOC_BASE) +#define GPIOC_PCOR GPIO_PCOR(GPIOC_BASE) +#define GPIOC_PTOR GPIO_PTOR(GPIOC_BASE) +#define GPIOC_PDIR GPIO_PDIR(GPIOC_BASE) +#define GPIOC_PDDR GPIO_PDDR(GPIOC_BASE) + +#define GPIOD_BASE 0x400FF0C0 + +#define GPIOD_PDOR GPIO_PDOR(GPIOD_BASE) +#define GPIOD_PSOR GPIO_PSOR(GPIOD_BASE) +#define GPIOD_PCOR GPIO_PCOR(GPIOD_BASE) +#define GPIOD_PTOR GPIO_PTOR(GPIOD_BASE) +#define GPIOD_PDIR GPIO_PDIR(GPIOD_BASE) +#define GPIOD_PDDR GPIO_PDDR(GPIOD_BASE) + +#define GPIOE_BASE 0x400FF100 + +#define GPIOE_PDOR GPIO_PDOR(GPIOE_BASE) +#define GPIOE_PSOR GPIO_PSOR(GPIOE_BASE) +#define GPIOE_PCOR GPIO_PCOR(GPIOE_BASE) +#define GPIOE_PTOR GPIO_PTOR(GPIOE_BASE) +#define GPIOE_PDIR GPIO_PDIR(GPIOE_BASE) +#define GPIOE_PDDR GPIO_PDDR(GPIOE_BASE) #endif /* MK20DX256_REG_GPIO_H */ @@ -5,15 +5,7 @@ #include <reg/regdefs.h> // Pin Control Register n -#define PORTA_PCR(n) REG_32(0x40049000 + 4 * (n)) -// Pin Control Register n -#define PORTB_PCR(n) REG_32(0x4004A000 + 4 * (n)) -// Pin Control Register n -#define PORTC_PCR(n) REG_32(0x4004B000 + 4 * (n)) -// Pin Control Register n -#define PORTD_PCR(n) REG_32(0x4004C000 + 4 * (n)) -// Pin Control Register n -#define PORTE_PCR(n) REG_32(0x4004D000 + 4 * (n)) +#define PORT_PCR(base, n) REG_32((base) + 0x00 + 4 * (n)) enum { PCR_ISF = 24, // Interrupt Status Flag PCR_IRQC = 16, // Interrupt Configuration @@ -30,36 +22,63 @@ enum { }; // Global Pin Control Low Register -#define PORTA_GPCLR REG_32(0x40049080) -// Global Pin Control Low Register -#define PORTB_GPCLR REG_32(0x4004A080) -// Global Pin Control Low Register -#define PORTC_GPCLR REG_32(0x4004B080) -// Global Pin Control Low Register -#define PORTD_GPCLR REG_32(0x4004C080) -// Global Pin Control Low Register -#define PORTE_GPCLR REG_32(0x4004D080) +#define PORT_GPCLR(base) REG_32((base) + 0x80) +enum { + GPCLR_GPWE = 16, // Global Pin Write Enable +#define GPCLR_GPWE_M REG_32_M(GPCLR_GPWE, 16) + GPCLR_GPWD = 0, // Global Pin Write Data +#define GPCLR_GPWD_M REG_32_M(GPCLR_GPWD, 16) +}; // Global Pin Control High Register -#define PORTA_GPCHR REG_32(0x40049084) -// Global Pin Control High Register -#define PORTB_GPCHR REG_32(0x4004A084) -// Global Pin Control High Register -#define PORTC_GPCHR REG_32(0x4004B084) -// Global Pin Control High Register -#define PORTD_GPCHR REG_32(0x4004C084) -// Global Pin Control High Register -#define PORTE_GPCHR REG_32(0x4004D084) +#define PORT_GPCHR(base) REG_32((base) + 0x84) +enum { + GPCHR_GPWE = 16, // Global Pin Write Enable +#define GPCHR_GPWE_M REG_32_M(GPCHR_GPWE, 16) + GPCHR_GPWD = 0, // Global Pin Write Data +#define GPCHR_GPWD_M REG_32_M(GPCHR_GPWD, 16) +}; // Interrupt Status Flag Register -#define PORTA_ISFR REG_32(0x400490A0) -// Interrupt Status Flag Register -#define PORTB_ISFR REG_32(0x4004A0A0) -// Interrupt Status Flag Register -#define PORTC_ISFR REG_32(0x4004B0A0) -// Interrupt Status Flag Register -#define PORTD_ISFR REG_32(0x4004C0A0) -// Interrupt Status Flag Register -#define PORTE_ISFR REG_32(0x4004D0A0) +#define PORT_ISFR(base) REG_32((base) + 0xa0) +enum { + ISFR_ISF = 0, // Interrupt Status Flag +#define ISFR_ISF_M REG_32_M(ISFR_ISF, 32); +}; + +#define PORTA_BASE 0x40049000 + +#define PORTA_GPCHR PORT_GPCHR(PORTA_BASE) +#define PORTA_GPCLR PORT_GPCLR(PORTA_BASE) +#define PORTA_ISFR PORT_ISFR(PORTA_BASE) +#define PORTA_PCR(n) PORT_PCR(n, PORTA_BASE) + +#define PORTB_BASE 0x4004A000 + +#define PORTB_GPCHR PORT_GPCHR(PORTB_BASE) +#define PORTB_GPCLR PORT_GPCLR(PORTB_BASE) +#define PORTB_ISFR PORT_ISFR(PORTB_BASE) +#define PORTB_PCR(n) PORT_PCR(n, PORTB_BASE) + +#define PORTC_BASE 0x4004B000 + +#define PORTC_GPCHR PORT_GPCHR(PORTC_BASE) +#define PORTC_GPCLR PORT_GPCLR(PORTC_BASE) +#define PORTC_ISFR PORT_ISFR(PORTC_BASE) +#define PORTC_PCR(n) PORT_PCR(n, PORTC_BASE) + +#define PORTD_BASE 0x4004C000 + +#define PORTD_GPCHR PORT_GPCHR(PORTD_BASE) +#define PORTD_GPCLR PORT_GPCLR(PORTD_BASE) +#define PORTD_ISFR PORT_ISFR(PORTD_BASE) +#define PORTD_PCR(n) PORT_PCR(n, PORTD_BASE) + +#define PORTE_BASE 0x4004D000 + +#define PORTE_GPCHR PORT_GPCHR(PORTE_BASE) +#define PORTE_GPCLR PORT_GPCLR(PORTE_BASE) +#define PORTE_ISFR PORT_ISFR(PORTE_BASE) +#define PORTE_PCR(n) PORT_PCR(n, PORTE_BASE) #endif /* MK20DX256_REG_PORT_H */ |