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/* Port control and interrupts (PORT) (Chapter 11) */
#ifndef MK20DX256_REG_PORT_H
#define MK20DX256_REG_PORT_H
#include <reg/regdefs.h>
// Pin Control Register n
#define PORT_PCR(base, n) REG_32((base) + 0x00 + 4 * (n))
enum {
PCR_ISF = 24, // Interrupt Status Flag
PCR_IRQC = 16, // Interrupt Configuration
PCR_IRQC_M = REG_32_M(PCR_IRQC, 4),
PCR_LK = 15, // Lock Register
PCR_MUX = 8, // Pin Mux Control
PCR_MUX_M = REG_32_M(PCR_MUX, 3),
PCR_DSE = 6, // Drive Strength Enable
PCR_ODE = 5, // Open Drain Enable
PCR_PFE = 4, // Passive Filter Enable
PCR_SRE = 2, // Slew Rate Enable
PCR_PE = 1, // Pull Enable
PCR_PS = 0, // Pull Select
};
// Global Pin Control Low Register
#define PORT_GPCLR(base) REG_32((base) + 0x80)
enum {
GPCLR_GPWE = 16, // Global Pin Write Enable
#define GPCLR_GPWE_M REG_32_M(GPCLR_GPWE, 16)
GPCLR_GPWD = 0, // Global Pin Write Data
#define GPCLR_GPWD_M REG_32_M(GPCLR_GPWD, 16)
};
// Global Pin Control High Register
#define PORT_GPCHR(base) REG_32((base) + 0x84)
enum {
GPCHR_GPWE = 16, // Global Pin Write Enable
#define GPCHR_GPWE_M REG_32_M(GPCHR_GPWE, 16)
GPCHR_GPWD = 0, // Global Pin Write Data
#define GPCHR_GPWD_M REG_32_M(GPCHR_GPWD, 16)
};
// Interrupt Status Flag Register
#define PORT_ISFR(base) REG_32((base) + 0xa0)
enum {
ISFR_ISF = 0, // Interrupt Status Flag
#define ISFR_ISF_M REG_32_M(ISFR_ISF, 32);
};
#define PORTA_BASE 0x40049000
#define PORTA_GPCHR PORT_GPCHR(PORTA_BASE)
#define PORTA_GPCLR PORT_GPCLR(PORTA_BASE)
#define PORTA_ISFR PORT_ISFR(PORTA_BASE)
#define PORTA_PCR(n) PORT_PCR(n, PORTA_BASE)
#define PORTB_BASE 0x4004A000
#define PORTB_GPCHR PORT_GPCHR(PORTB_BASE)
#define PORTB_GPCLR PORT_GPCLR(PORTB_BASE)
#define PORTB_ISFR PORT_ISFR(PORTB_BASE)
#define PORTB_PCR(n) PORT_PCR(n, PORTB_BASE)
#define PORTC_BASE 0x4004B000
#define PORTC_GPCHR PORT_GPCHR(PORTC_BASE)
#define PORTC_GPCLR PORT_GPCLR(PORTC_BASE)
#define PORTC_ISFR PORT_ISFR(PORTC_BASE)
#define PORTC_PCR(n) PORT_PCR(n, PORTC_BASE)
#define PORTD_BASE 0x4004C000
#define PORTD_GPCHR PORT_GPCHR(PORTD_BASE)
#define PORTD_GPCLR PORT_GPCLR(PORTD_BASE)
#define PORTD_ISFR PORT_ISFR(PORTD_BASE)
#define PORTD_PCR(n) PORT_PCR(n, PORTD_BASE)
#define PORTE_BASE 0x4004D000
#define PORTE_GPCHR PORT_GPCHR(PORTE_BASE)
#define PORTE_GPCLR PORT_GPCLR(PORTE_BASE)
#define PORTE_ISFR PORT_ISFR(PORTE_BASE)
#define PORTE_PCR(n) PORT_PCR(n, PORTE_BASE)
#endif /* MK20DX256_REG_PORT_H */
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