blob: 76d84c5f765fdab57adc93eacf28b5ba2e61e7c4 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
|
#ifndef MK20DX256_REG_GPIO_H
#define MK20DX256_REG_GPIO_H
#include <reg/regdefs.h>
// Port Data Output Register
#define GPIOA_PDOR REG_32(0x400FF000)
// Port Set Output Register
#define GPIOA_PSOR REG_32(0x400FF004)
// Port Clear Output Register
#define GPIOA_PCOR REG_32(0x400FF008)
// Port Toggle Output Register
#define GPIOA_PTOR REG_32(0x400FF00C)
// Port Data Input Register
#define GPIOA_PDIR REG_32(0x400FF010)
// Port Data Direction Register
#define GPIOA_PDDR REG_32(0x400FF014)
// Port Data Output Register
#define GPIOB_PDOR REG_32(0x400FF040)
// Port Set Output Register
#define GPIOB_PSOR REG_32(0x400FF044)
// Port Clear Output Register
#define GPIOB_PCOR REG_32(0x400FF048)
// Port Toggle Output Register
#define GPIOB_PTOR REG_32(0x400FF04C)
// Port Data Input Register
#define GPIOB_PDIR REG_32(0x400FF050)
// Port Data Direction Register
#define GPIOB_PDDR REG_32(0x400FF054)
// Port Data Output Register
#define GPIOC_PDOR REG_32(0x400FF080)
// Port Set Output Register
#define GPIOC_PSOR REG_32(0x400FF084)
// Port Clear Output Register
#define GPIOC_PCOR REG_32(0x400FF088)
// Port Toggle Output Register
#define GPIOC_PTOR REG_32(0x400FF08C)
// Port Data Input Register
#define GPIOC_PDIR REG_32(0x400FF090)
// Port Data Direction Register
#define GPIOC_PDDR REG_32(0x400FF094)
// Port Data Output Register
#define GPIOD_PDOR REG_32(0x400FF0C0)
// Port Set Output Register
#define GPIOD_PSOR REG_32(0x400FF0C4)
// Port Clear Output Register
#define GPIOD_PCOR REG_32(0x400FF0C8)
// Port Toggle Output Register
#define GPIOD_PTOR REG_32(0x400FF0CC)
// Port Data Input Register
#define GPIOD_PDIR REG_32(0x400FF0D0)
// Port Data Direction Register
#define GPIOD_PDDR REG_32(0x400FF0D4)
// Port Data Output Register
#define GPIOE_PDOR REG_32(0x400FF100)
// Port Set Output Register
#define GPIOE_PSOR REG_32(0x400FF104)
// Port Clear Output Register
#define GPIOE_PCOR REG_32(0x400FF108)
// Port Toggle Output Register
#define GPIOE_PTOR REG_32(0x400FF10C)
// Port Data Input Register
#define GPIOE_PDIR REG_32(0x400FF110)
// Port Data Direction Register
#define GPIOE_PDDR REG_32(0x400FF114)
#endif /* MK20DX256_REG_GPIO_H */
|
