cleanup

9 files changed, 654 insertions, 433 deletions

diff --git a/reg/gpio.h b/reg/gpio.h
index d4c8574..76d84c5 100644
--- a/reg/gpio.h
+++ b/reg/gpio.h
@@ -3,39 +3,69 @@
 
 #include <reg/regdefs.h>
 
-#define GPIOA_PDOR REG_32(0x400FF000) /* Port Data Output Register */
-#define GPIOA_PSOR REG_32(0x400FF004) /* Port Set Output Register */
-#define GPIOA_PCOR REG_32(0x400FF008) /* Port Clear Output Register */
-#define GPIOA_PTOR REG_32(0x400FF00C) /* Port Toggle Output Register */
-#define GPIOA_PDIR REG_32(0x400FF010) /* Port Data Input Register */
-#define GPIOA_PDDR REG_32(0x400FF014) /* Port Data Direction Register */
+// Port Data Output Register
+#define GPIOA_PDOR REG_32(0x400FF000)
+// Port Set Output Register
+#define GPIOA_PSOR REG_32(0x400FF004)
+// Port Clear Output Register
+#define GPIOA_PCOR REG_32(0x400FF008)
+// Port Toggle Output Register
+#define GPIOA_PTOR REG_32(0x400FF00C)
+// Port Data Input Register
+#define GPIOA_PDIR REG_32(0x400FF010)
+// Port Data Direction Register
+#define GPIOA_PDDR REG_32(0x400FF014)
 
-#define GPIOB_PDOR REG_32(0x400FF040) /* Port Data Output Register */
-#define GPIOB_PSOR REG_32(0x400FF044) /* Port Set Output Register */
-#define GPIOB_PCOR REG_32(0x400FF048) /* Port Clear Output Register */
-#define GPIOB_PTOR REG_32(0x400FF04C) /* Port Toggle Output Register */
-#define GPIOB_PDIR REG_32(0x400FF050) /* Port Data Input Register */
-#define GPIOB_PDDR REG_32(0x400FF054) /* Port Data Direction Register */
+// Port Data Output Register
+#define GPIOB_PDOR REG_32(0x400FF040)
+// Port Set Output Register
+#define GPIOB_PSOR REG_32(0x400FF044)
+// Port Clear Output Register
+#define GPIOB_PCOR REG_32(0x400FF048)
+// Port Toggle Output Register
+#define GPIOB_PTOR REG_32(0x400FF04C)
+// Port Data Input Register
+#define GPIOB_PDIR REG_32(0x400FF050)
+// Port Data Direction Register
+#define GPIOB_PDDR REG_32(0x400FF054)
 
-#define GPIOC_PDOR REG_32(0x400FF080) /* Port Data Output Register */
-#define GPIOC_PSOR REG_32(0x400FF084) /* Port Set Output Register */
-#define GPIOC_PCOR REG_32(0x400FF088) /* Port Clear Output Register */
-#define GPIOC_PTOR REG_32(0x400FF08C) /* Port Toggle Output Register */
-#define GPIOC_PDIR REG_32(0x400FF090) /* Port Data Input Register */
-#define GPIOC_PDDR REG_32(0x400FF094) /* Port Data Direction Register */
+// Port Data Output Register
+#define GPIOC_PDOR REG_32(0x400FF080)
+// Port Set Output Register
+#define GPIOC_PSOR REG_32(0x400FF084)
+// Port Clear Output Register
+#define GPIOC_PCOR REG_32(0x400FF088)
+// Port Toggle Output Register
+#define GPIOC_PTOR REG_32(0x400FF08C)
+// Port Data Input Register
+#define GPIOC_PDIR REG_32(0x400FF090)
+// Port Data Direction Register
+#define GPIOC_PDDR REG_32(0x400FF094)
 
-#define GPIOD_PDOR REG_32(0x400FF0C0) /* Port Data Output Register */
-#define GPIOD_PSOR REG_32(0x400FF0C4) /* Port Set Output Register */
-#define GPIOD_PCOR REG_32(0x400FF0C8) /* Port Clear Output Register */
-#define GPIOD_PTOR REG_32(0x400FF0CC) /* Port Toggle Output Register */
-#define GPIOD_PDIR REG_32(0x400FF0D0) /* Port Data Input Register */
-#define GPIOD_PDDR REG_32(0x400FF0D4) /* Port Data Direction Register */
+// Port Data Output Register
+#define GPIOD_PDOR REG_32(0x400FF0C0)
+// Port Set Output Register
+#define GPIOD_PSOR REG_32(0x400FF0C4)
+// Port Clear Output Register
+#define GPIOD_PCOR REG_32(0x400FF0C8)
+// Port Toggle Output Register
+#define GPIOD_PTOR REG_32(0x400FF0CC)
+// Port Data Input Register
+#define GPIOD_PDIR REG_32(0x400FF0D0)
+// Port Data Direction Register
+#define GPIOD_PDDR REG_32(0x400FF0D4)
 
-#define GPIOE_PDOR REG_32(0x400FF100) /* Port Data Output Register */
-#define GPIOE_PSOR REG_32(0x400FF104) /* Port Set Output Register */
-#define GPIOE_PCOR REG_32(0x400FF108) /* Port Clear Output Register */
-#define GPIOE_PTOR REG_32(0x400FF10C) /* Port Toggle Output Register */
-#define GPIOE_PDIR REG_32(0x400FF110) /* Port Data Input Register */
-#define GPIOE_PDDR REG_32(0x400FF114) /* Port Data Direction Register */
+// Port Data Output Register
+#define GPIOE_PDOR REG_32(0x400FF100)
+// Port Set Output Register
+#define GPIOE_PSOR REG_32(0x400FF104)
+// Port Clear Output Register
+#define GPIOE_PCOR REG_32(0x400FF108)
+// Port Toggle Output Register
+#define GPIOE_PTOR REG_32(0x400FF10C)
+// Port Data Input Register
+#define GPIOE_PDIR REG_32(0x400FF110)
+// Port Data Direction Register
+#define GPIOE_PDDR REG_32(0x400FF114)
 
 #endif /* MK20DX256_REG_GPIO_H */
diff --git a/reg/mcg.h b/reg/mcg.h
index 5972439..1acae9e 100644
--- a/reg/mcg.h
+++ b/reg/mcg.h
@@ -3,54 +3,76 @@
 
 #include <reg/regdefs.h>
 
-#define MCG_C1 REG_8(0x40064000) /* MCG Control 1 Register */
-#define C1_CLKS 6 /* Clock Source Select */
-#define C1_CLKS_M REG_8_M(C1_CLKS, 2)
-#define C1_FRDIV 3 /* FLL External Reference Divider */
-#define C1_FRDIV_M REG_8_M(C1_FRDIV, 3)
-#define C1_IREFS 2 /* Internal Reference Select */
-#define C1_IRCLKEN 1 /* Internal Reference Clock Enable */
-#define C1_IREFSTEN 0 /* Internal Reference Stop Enable */
-
-#define MCG_C2 REG_8(0x40064001) /* MCG Control 2 Register */
-#define C2_LOCRE0 7 /* Loss of Clock Reset Enable */
-#define C2_RANGE0 4 /* Frequency Range Select */
-#define C2_RANGE0_M REG_8_M(C2_RANGE0, 2)
-#define C2_HGO0 3 /* High Gain Oscillator Select */
-#define C2_EREFS0 2 /* External Reference Select */
-#define C2_LP 1 /* Low Power Select */
-#define C2_IRCS 0 /* Internal Reference Clock Select */
-
-#define MCG_C3 REG_8(0x40064002) /* MCG Control 3 Register */
-#define MCG_C4 REG_8(0x40064003) /* MCG Control 4 Register */
-
-#define MCG_C5 REG_8(0x40064004) /* MCG Control 5 Register */
-#define C5_PLLCLKEN0 6 /* PLL Clock Enable */
-#define C5_PLLSTEN0 5 /* PLL Stop Enable */
-#define C5_PRDIV0 0 /* PLL External Reference Divider */
-#define C5_PRDIV0_M REG_8_M(C5_PRDIV0, 5)
-
-#define MCG_C6 REG_8(0x40064005) /* MCG Control 6 Register */
-#define C6_LOLIE0 7 /* Loss of Lock Interrrupt Enable */
-#define C6_PLLS 6 /* PLL Select */
-#define C6_CME0 5 /* Clock Monitor Enable */
-#define C6_VDIV0 0 /* VCO 0 Divider */
-#define C6_VDIV0_M REG_8_M(C6_VDIV0, 5)
-
-#define MCG_S REG_8(0x40064006) /* MCG Status Register */
-#define S_LOLS0 7 /* Loss of Lock Status */
-#define S_LOCK0 6 /* Lock Status */
-#define S_PLLST 5 /* PLL Select Status */
-#define S_IREFST 4 /* Internal Reference Status */
-#define S_CLKST 2 /* Clock Mode Status */
-#define S_CLKST_M REG_8_M(S_CLKST, 2)
-#define S_OSCINIT0 1 /* OSC Initialization */
-#define S_IRCST 0 /* Internal Reference Clock Status */
-
-#define MCG_SC REG_8(0x40064008) /* MCG Status and Control Register */
-#define MCG_ATCVH REG_8(0x4006400A) /* MCG Auto Trim Compare Value High Register */
-#define MCG_ATCVL REG_8(0x4006400B) /* MCG Auto Trim Compare Value Low Register */
-#define MCG_C7 REG_8(0x4006400C) /* MCG Control 7 Register */
-#define MCG_C8 REG_8(0x4006400D) /* MCG Control 8 Register */
+// MCG Control 1 Register
+#define MCG_C1 REG_8(0x40064000)
+enum {
+	C1_CLKS = 6, // Clock Source Select
+	C1_CLKS_M = REG_8_M(C1_CLKS, 2),
+	C1_FRDIV = 3, // FLL External Reference Divider
+	C1_FRDIV_M = REG_8_M(C1_FRDIV, 3),
+	C1_IREFS = 2, // Internal Reference Select
+	C1_IRCLKEN = 1, // Internal Reference Clock Enable
+	C1_IREFSTEN = 0, // Internal Reference Stop Enable
+};
+
+// MCG Control 2 Register
+#define MCG_C2 REG_8(0x40064001)
+enum {
+	C2_LOCRE0 = 7, // Loss of Clock Reset Enable
+	C2_RANGE0 = 4, // Frequency Range Select
+	C2_RANGE0_M = REG_8_M(C2_RANGE0, 2),
+	C2_HGO0 = 3, // High Gain Oscillator Select
+	C2_EREFS0 = 2, // External Reference Select
+	C2_LP = 1, // Low Power Select
+	C2_IRCS = 0, // Internal Reference Clock Select
+};
+
+// MCG Control 3 Register
+#define MCG_C3 REG_8(0x40064002)
+// MCG Control 4 Register
+#define MCG_C4 REG_8(0x40064003)
+
+// MCG Control 5 Register
+#define MCG_C5 REG_8(0x40064004)
+enum {
+	C5_PLLCLKEN0 = 6, // PLL Clock Enable
+	C5_PLLSTEN0 = 5, // PLL Stop Enable
+	C5_PRDIV0 = 0, // PLL External Reference Divider
+	C5_PRDIV0_M = REG_8_M(C5_PRDIV0, 5),
+};
+
+// MCG Control 6 Register
+#define MCG_C6 REG_8(0x40064005)
+enum {
+	C6_LOLIE0 = 7, // Loss of Lock Interrrupt Enable
+	C6_PLLS = 6, // PLL Select
+	C6_CME0 = 5, // Clock Monitor Enable
+	C6_VDIV0 = 0, // VCO 0 Divider
+	C6_VDIV0_M = REG_8_M(C6_VDIV0, 5),
+};
+
+// MCG Status Register
+#define MCG_S REG_8(0x40064006)
+enum {
+	S_LOLS0 = 7, // Loss of Lock Status
+	S_LOCK0 = 6, // Lock Status
+	S_PLLST = 5, // PLL Select Status
+	S_IREFST = 4, // Internal Reference Status
+	S_CLKST = 2, // Clock Mode Status
+	S_CLKST_M = REG_8_M(S_CLKST, 2),
+	S_OSCINIT0 = 1, // OSC Initialization
+	S_IRCST = 0, // Internal Reference Clock Status
+};
+
+// MCG Status and Control Register
+#define MCG_SC REG_8(0x40064008)
+// MCG Auto Trim Compare Value High Register
+#define MCG_ATCVH REG_8(0x4006400A)
+// MCG Auto Trim Compare Value Low Register
+#define MCG_ATCVL REG_8(0x4006400B)
+// MCG Control 7 Register
+#define MCG_C7 REG_8(0x4006400C)
+// MCG Control 8 Register
+#define MCG_C8 REG_8(0x4006400D)
 
 #endif /* MK20DX256_REG_MCG_H */
diff --git a/reg/pit.h b/reg/pit.h
index db155dc..04a9759 100644
--- a/reg/pit.h
+++ b/reg/pit.h
@@ -5,27 +5,37 @@
 
 // PIT Module Control Register
 #define PIT_MCR REG_32(0x40037000)
-#define MCR_MDIS 1 // Module Disable
-#define MCR_FRZ 0 // Freeze
+enum {
+	MCR_MDIS = 1, // Module Disable
+	MCR_FRZ = 0, // Freeze
+};
 
 // Timer Load Value Register
 #define PIT_LDVAL(n) REG_32(0x40037100 + 16 * (n))
-#define LDVAL_TSV 0 // Timer Start Value
-#define LDVAL_TSV_M REG_32_M(CVAL_TVL, 32)
+enum {
+	LDVAL_TSV = 0, // Timer Start Value
+	LDVAL_TSV_M = REG_32_M(CVAL_TVL, 32),
+};
 
 // Current Timer Value Register
 #define PIT_CVAL(n) REG_32(0x40037104 + 16 * (n))
-#define CVAL_TVL 0 // Current Timer Value
-#define CVAL_TVL_M REG_32_M(CVAL_TVL, 32)
+enum {
+	CVAL_TVL = 0, // Current Timer Value
+	CVAL_TVL_M = REG_32_M(CVAL_TVL, 32),
+};
 
 // Timer Control Register
 #define PIT_TCTRL(n) REG_32(0x40037108 + 16 * (n))
-#define TCTRL_CHN 2 // Chain Mode
-#define TCTRL_TIE 1 // Timer Interrupt Enable
-#define TCTRL_TEN 0 // Timer Enable
+enum {
+	TCTRL_CHN = 2, // Chain Mode
+	TCTRL_TIE = 1, // Timer Interrupt Enable
+	TCTRL_TEN = 0, // Timer Enable
+};
 
 // Timer Flag Register
 #define PIT_TFLG(n) REG_32(0x4003710C + 16 * (n))
-#define TFLG_TIF 0 // Timer Interrupt Flag
+enum {
+	TFLG_TIF = 0, // Timer Interrupt Flag
+};
 
 #endif /* MK20DX256_REG_PIT_H */
diff --git a/reg/pmc.h b/reg/pmc.h
index cb045ea..befbb50 100644
--- a/reg/pmc.h
+++ b/reg/pmc.h
@@ -3,25 +3,34 @@
 
 #include <reg/regdefs.h>
 
-#define PMC_LVDSC1 REG_8(0x4007D000) /* Low Voltage Detect Status And Control 1 register */
-#define LVDSC1_LVDF 7 /* Low-Voltage Detect Flag */
-#define LVDSC1_LVDACK 6 /* Low-Voltage Detect Acknowledge */
-#define LVDSC1_LVDIE 5 /* Low-Voltage Detect Interrupt Enable */
-#define LVDSC1_LVDRE 4 /* Low-Voltage Detect Reset Enable */
-#define LVDSC1_LVDV 0 /* Low-Voltage Detect Voltage Select */
-#define LVDSC1_LVDV_M REG_8_M(LVDSC1_LVDV, 2)
+// Low Voltage Detect Status And Control 1 register
+#define PMC_LVDSC1 REG_8(0x4007D000)
+enum {
+	LVDSC1_LVDF = 7, // Low-Voltage Detect Flag
+	LVDSC1_LVDACK = 6, // Low-Voltage Detect Acknowledge
+	LVDSC1_LVDIE = 5, // Low-Voltage Detect Interrupt Enable
+	LVDSC1_LVDRE = 4, // Low-Voltage Detect Reset Enable
+	LVDSC1_LVDV = 0, // Low-Voltage Detect Voltage Select
+	LVDSC1_LVDV_M = REG_8_M(LVDSC1_LVDV, 2),
+};
 
-#define PMC_LVDSC2 REG_8(0x4007D001) /* Low Voltage Detect Status And Control 2 register */
-#define LVDSC2_LVWF 7 /* Low-Voltage Warning Flag */
-#define LVDSC2_LVWACK 6 /* Low-Voltage Warning Acknowledge */
-#define LVDSC2_LVWIE 5 /* Low-Voltage Warning Interrupt Enable */
-#define LVDSC2_LVWV 0 /* Low-Voltage Warning Voltage Select */
-#define LVDSC2_LVWV_M REG_8_M(LVDSC2_LVWV, 2)
+// Low Voltage Detect Status And Control 2 register
+#define PMC_LVDSC2 REG_8(0x4007D001)
+enum {
+	LVDSC2_LVWF = 7, // Low-Voltage Warning Flag
+	LVDSC2_LVWACK = 6, // Low-Voltage Warning Acknowledge
+	LVDSC2_LVWIE = 5, // Low-Voltage Warning Interrupt Enable
+	LVDSC2_LVWV = 0, // Low-Voltage Warning Voltage Select
+	LVDSC2_LVWV_M = REG_8_M(LVDSC2_LVWV, 2),
+};
 
-#define PMC_REGSC REG_8(0x4007D002) /* Regulator Status And Control register */
-#define REGSC_BGEN 4 /* Bandgap Enable In VLPx Operation */
-#define REGSC_ACKISO 3 /* Acknowledge Isolation */
-#define REGSC_REGONS 2 /* Regulator In Run Regulation Status */
-#define REGSC_BGBE 1 /* Bandgap Buffer Enable */
+// Regulator Status And Control register
+#define PMC_REGSC REG_8(0x4007D002)
+enum {
+	REGSC_BGEN = 4, // Bandgap Enable In VLPx Operation
+	REGSC_ACKISO = 3, // Acknowledge Isolation
+	REGSC_REGONS = 2, // Regulator In Run Regulation Status
+	REGSC_BGBE = 1, // Bandgap Buffer Enable
+};
 
 #endif /* MK20DX256_REG_PMC_H */
diff --git a/reg/port.h b/reg/port.h
index 55e30bc..704eaaf 100644
--- a/reg/port.h
+++ b/reg/port.h
@@ -3,40 +3,62 @@
 
 #include <reg/regdefs.h>
 
-#define PORTA_PCR(n) REG_32(0x40049000 + 4 * (n)) /* Pin Control Register n */
-#define PORTB_PCR(n) REG_32(0x4004A000 + 4 * (n)) /* Pin Control Register n */
-#define PORTC_PCR(n) REG_32(0x4004B000 + 4 * (n)) /* Pin Control Register n */
-#define PORTD_PCR(n) REG_32(0x4004C000 + 4 * (n)) /* Pin Control Register n */
-#define PORTE_PCR(n) REG_32(0x4004D000 + 4 * (n)) /* Pin Control Register n */
-#define PCR_ISF 24 /* Interrupt Status Flag */
-#define PCR_IRQC 16 /* Interrupt Configuration */
-#define PCR_IRQC_M (uint32_t)(BITS(4) << PCR_IRQC)
-#define PCR_LK 15 /* Lock Register */
-#define PCR_MUX 8 /* Pin Mux Control */
-#define PCR_MUX_M (uint32_t)(BITS(3) << PCR_MUX)
-#define PCR_DSE 6 /* Drive Strength Enable */
-#define PCR_ODE 5 /* Open Drain Enable */
-#define PCR_PFE 4 /* Passive Filter Enable */
-#define PCR_SRE 2 /* Slew Rate Enable */
-#define PCR_PE 1 /* Pull Enable */
-#define PCR_PS 0 /* Pull Select */
+// Pin Control Register n
+#define PORTA_PCR(n) REG_32(0x40049000 + 4 * (n))
+// Pin Control Register n
+#define PORTB_PCR(n) REG_32(0x4004A000 + 4 * (n))
+// Pin Control Register n
+#define PORTC_PCR(n) REG_32(0x4004B000 + 4 * (n))
+// Pin Control Register n
+#define PORTD_PCR(n) REG_32(0x4004C000 + 4 * (n))
+// Pin Control Register n
+#define PORTE_PCR(n) REG_32(0x4004D000 + 4 * (n))
+enum {
+	PCR_ISF = 24, // Interrupt Status Flag
+	PCR_IRQC = 16, // Interrupt Configuration
+	PCR_IRQC_M = REG_32_M(PCR_IRQC, 4),
+	PCR_LK = 15, // Lock Register
+	PCR_MUX = 8, // Pin Mux Control
+	PCR_MUX_M = REG_32_M(PCR_MUX, 3),
+	PCR_DSE = 6, // Drive Strength Enable
+	PCR_ODE = 5, // Open Drain Enable
+	PCR_PFE = 4, // Passive Filter Enable
+	PCR_SRE = 2, // Slew Rate Enable
+	PCR_PE = 1, // Pull Enable
+	PCR_PS = 0, // Pull Select
+};
 
-#define PORTA_GPCLR REG_32(0x40049080) /* Global Pin Control Low Register */
-#define PORTB_GPCLR REG_32(0x4004A080) /* Global Pin Control Low Register */
-#define PORTC_GPCLR REG_32(0x4004B080) /* Global Pin Control Low Register */
-#define PORTD_GPCLR REG_32(0x4004C080) /* Global Pin Control Low Register */
-#define PORTE_GPCLR REG_32(0x4004D080) /* Global Pin Control Low Register */
+// Global Pin Control Low Register
+#define PORTA_GPCLR REG_32(0x40049080)
+// Global Pin Control Low Register
+#define PORTB_GPCLR REG_32(0x4004A080)
+// Global Pin Control Low Register
+#define PORTC_GPCLR REG_32(0x4004B080)
+// Global Pin Control Low Register
+#define PORTD_GPCLR REG_32(0x4004C080)
+// Global Pin Control Low Register
+#define PORTE_GPCLR REG_32(0x4004D080)
 
-#define PORTA_GPCHR REG_32(0x40049084) /* Global Pin Control High Register */
-#define PORTB_GPCHR REG_32(0x4004A084) /* Global Pin Control High Register */
-#define PORTC_GPCHR REG_32(0x4004B084) /* Global Pin Control High Register */
-#define PORTD_GPCHR REG_32(0x4004C084) /* Global Pin Control High Register */
-#define PORTE_GPCHR REG_32(0x4004D084) /* Global Pin Control High Register */
+// Global Pin Control High Register
+#define PORTA_GPCHR REG_32(0x40049084)
+// Global Pin Control High Register
+#define PORTB_GPCHR REG_32(0x4004A084)
+// Global Pin Control High Register
+#define PORTC_GPCHR REG_32(0x4004B084)
+// Global Pin Control High Register
+#define PORTD_GPCHR REG_32(0x4004C084)
+// Global Pin Control High Register
+#define PORTE_GPCHR REG_32(0x4004D084)
 
-#define PORTA_ISFR REG_32(0x400490A0) /* Interrupt Status Flag Register */
-#define PORTB_ISFR REG_32(0x4004A0A0) /* Interrupt Status Flag Register */
-#define PORTC_ISFR REG_32(0x4004B0A0) /* Interrupt Status Flag Register */
-#define PORTD_ISFR REG_32(0x4004C0A0) /* Interrupt Status Flag Register */
-#define PORTE_ISFR REG_32(0x4004D0A0) /* Interrupt Status Flag Register */
+// Interrupt Status Flag Register
+#define PORTA_ISFR REG_32(0x400490A0)
+// Interrupt Status Flag Register
+#define PORTB_ISFR REG_32(0x4004A0A0)
+// Interrupt Status Flag Register
+#define PORTC_ISFR REG_32(0x4004B0A0)
+// Interrupt Status Flag Register
+#define PORTD_ISFR REG_32(0x4004C0A0)
+// Interrupt Status Flag Register
+#define PORTE_ISFR REG_32(0x4004D0A0)
 
 #endif /* MK20DX256_REG_PORT_H */
diff --git a/reg/sim.h b/reg/sim.h
index a9559b1..9a10eaf 100644
--- a/reg/sim.h
+++ b/reg/sim.h
@@ -9,27 +9,31 @@
 
 // System Options Register 2
 #define SIM_SOPT2 REG_32(0x40048004)
-#define SOPT2_USBSRC 18 // USB clock source select
-#define SOPT2_PLLFLLSEL 16 // PLL/FLL clock select
-#define SOPT2_TRACECLKSEL 12 // Debug trace clock select
-#define SOPT2_PTD7PAD 11 // PTD7 pad drive strength
-#define SOPT2_CLKOUTSEL 5 // CLKOUT select
-#define SOPT2_CLKOUTSEL_M REG_32_M(SOPT2_CLKOUTSEL, 3)
-#define SOPT2_RTCCLKOUTSEL 4 // RTC clock out select
+enum {
+	SOPT2_USBSRC = 18, // USB clock source select
+	SOPT2_PLLFLLSEL = 16, // PLL/FLL clock select
+	SOPT2_TRACECLKSEL = 12, // Debug trace clock select
+	SOPT2_PTD7PAD = 11, // PTD7 pad drive strength
+	SOPT2_CLKOUTSEL = 5, // CLKOUT select
+	SOPT2_CLKOUTSEL_M = REG_32_M(SOPT2_CLKOUTSEL, 3),
+	SOPT2_RTCCLKOUTSEL = 4, // RTC clock out select
+};
 
 // System Options Register 4
 #define SIM_SOPT4 REG_32(0x4004800C)
 
 // System Options Register 5
 #define SIM_SOPT5 REG_32(0x40048010)
-#define SOPT5_UART1RXSRC 6 // UART 1 receive data source select
-#define SOPT5_UART1RXSRC_M REG_32_M(SOPT5_UART1RXSRC, 2)
-#define SOPT5_UART1TXSRC 4 // UART 1 transmit data source select
-#define SOPT5_UART1TXSRC_M REG_32_M(SOPT5_UART1TXSRC, 2)
-#define SOPT5_UART0RXSRC 2 // UART 0 receive data source select
-#define SOPT5_UART0RXSRC_M REG_32_M(SOPT5_UART0RXSRC, 2)
-#define SOPT5_UART0TXSRC 0 // UART 0 transmit data source select
-#define SOPT5_UART0TXSRC_M REG_32_M(SOPT5_UART0TXSRC, 2)
+enum {
+	SOPT5_UART1RXSRC = 6, // UART 1 receive data source select
+	SOPT5_UART1RXSRC_M = REG_32_M(SOPT5_UART1RXSRC, 2),
+	SOPT5_UART1TXSRC = 4, // UART 1 transmit data source select
+	SOPT5_UART1TXSRC_M = REG_32_M(SOPT5_UART1TXSRC, 2),
+	SOPT5_UART0RXSRC = 2, // UART 0 receive data source select
+	SOPT5_UART0RXSRC_M = REG_32_M(SOPT5_UART0RXSRC, 2),
+	SOPT5_UART0TXSRC = 0, // UART 0 transmit data source select
+	SOPT5_UART0TXSRC_M = REG_32_M(SOPT5_UART0TXSRC, 2),
+};
 
 // System Options Register 7
 #define SIM_SOPT7 REG_32(0x40048018)
@@ -48,26 +52,30 @@
 
 // System Clock Gating Control Register 4
 #define SIM_SCGC4 REG_32(0x40048034)
-#define SCGC4_VREF 20 // VREF Clock Gate Control
-#define SCGC4_CMP 19 // Comparator Clock Gate Control
-#define SCGC4_USBOTG 18 // USB Clock Gate Control
-#define SCGC4_UART2 12 // UART2 Clock Gate Control
-#define SCGC4_UART1 11 // UART1 Clock Gate Control
-#define SCGC4_UART0 10 // UART0 Clock Gate Control
-#define SCGC4_I2C1 7 // I2C1 Clock Gate Control
-#define SCGC4_I2C0 6 // I2C0 Clock Gate Control
-#define SCGC4_CMT 2 // CMT Clock Gate Control
-#define SCGC4_EWM 1 // EWM Clock Gate Control
+enum {
+	SCGC4_VREF = 20, // VREF Clock Gate Control
+	SCGC4_CMP = 19, // Comparator Clock Gate Control
+	SCGC4_USBOTG = 18, // USB Clock Gate Control
+	SCGC4_UART2 = 12, // UART2 Clock Gate Control
+	SCGC4_UART1 = 11, // UART1 Clock Gate Control
+	SCGC4_UART0 = 10, // UART0 Clock Gate Control
+	SCGC4_I2C1 = 7, // I2C1 Clock Gate Control
+	SCGC4_I2C0 = 6, // I2C0 Clock Gate Control
+	SCGC4_CMT = 2, // CMT Clock Gate Control
+	SCGC4_EWM = 1, // EWM Clock Gate Control
+};
 
 // System Clock Gating Control Register 5
 #define SIM_SCGC5 REG_32(0x40048038)
-#define SCGC5_PORTE 13 // Port E Clock Gate Control
-#define SCGC5_PORTD 12 // Port D Clock Gate Control
-#define SCGC5_PORTC 11 // Port C Clock Gate Control
-#define SCGC5_PORTB 10 // Port B Clock Gate Control
-#define SCGC5_PORTA 9 // Port A Clock Gate Control
-#define SCGC5_TSI 5 // TSI Clock Gate Control
-#define SCGC5_LPTIMER 0 // Low Power Timer Access Control
+enum {
+	SCGC5_PORTE = 13, // Port E Clock Gate Control
+	SCGC5_PORTD = 12, // Port D Clock Gate Control
+	SCGC5_PORTC = 11, // Port C Clock Gate Control
+	SCGC5_PORTB = 10, // Port B Clock Gate Control
+	SCGC5_PORTA = 9, // Port A Clock Gate Control
+	SCGC5_TSI = 5, // TSI Clock Gate Control
+	SCGC5_LPTIMER = 0, // Low Power Timer Access Control
+};
 
 // System Clock Gating Control Register 6
 #define SIM_SCGC6 REG_32(0x4004803C)
@@ -77,18 +85,22 @@
 
 // System Clock Divider Register 1
 #define SIM_CLKDIV1 REG_32(0x40048044)
-#define CLKDIV1_OUTDIV1 28 // Clock 1 output divider value
-#define CLKDIV1_OUTDIV1_M REG_32_M(CLKDIV1_OUTDIV1, 4)
-#define CLKDIV1_OUTDIV2 24 // Clock 2 output divider value
-#define CLKDIV1_OUTDIV2_M REG_32_M(CLKDIV1_OUTDIV2, 4)
-#define CLKDIV1_OUTDIV4 16 // Clock 4 output divider value
-#define CLKDIV1_OUTDIV4_M REG_32_M(CLKDIV1_OUTDIV4, 4)
+enum {
+	CLKDIV1_OUTDIV1 = 28, // Clock 1 output divider value
+	CLKDIV1_OUTDIV1_M = REG_32_M(CLKDIV1_OUTDIV1, 4),
+	CLKDIV1_OUTDIV2 = 24, // Clock 2 output divider value
+	CLKDIV1_OUTDIV2_M = REG_32_M(CLKDIV1_OUTDIV2, 4),
+	CLKDIV1_OUTDIV4 = 16, // Clock 4 output divider value
+	CLKDIV1_OUTDIV4_M = REG_32_M(CLKDIV1_OUTDIV4, 4),
+};
 
 // System Clock Divider Register 2
 #define SIM_CLKDIV2 REG_32(0x40048048)
-#define CLKDIV2_USBDIV 1 // USB clock divider divisor
-#define CLKDIV2_USBDIV_M REG_32_M(CLKDIV2_USBDIV, 3)
-#define CLKDIV2_USBFRAC 0 // USB clock divider fraction
+enum {
+	CLKDIV2_USBDIV = 1, // USB clock divider divisor
+	CLKDIV2_USBDIV_M = REG_32_M(CLKDIV2_USBDIV, 3),
+	CLKDIV2_USBFRAC = 0, // USB clock divider fraction
+};
 
 // Flash Configuration Register 1
 #define SIM_FCFG1 REG_32(0x4004804C)
diff --git a/reg/uart.h b/reg/uart.h
index 3b2ee12..0ec2105 100644
--- a/reg/uart.h
+++ b/reg/uart.h
@@ -26,161 +26,205 @@
 
 // UART Baud Rate Registers: High
 #define UART_BDH(base) REG_8((base) + 0x0)
-#define BDH_LBKDIE 7 // LIN Break Detect Interrupt Enable
-#define BDH_RXEDGIE 6 // RxD Input Active Edge Interrupt Enable
-#define BDH_SBR 0 // UART Baud Rate Bits
-#define BDH_SBR_M REG_8_M(BDH_SBR, 4)
+enum {
+	BDH_LBKDIE = 7, // LIN Break Detect Interrupt Enable
+	BDH_RXEDGIE = 6, // RxD Input Active Edge Interrupt Enable
+	BDH_SBR = 0, // UART Baud Rate Bits
+	BDH_SBR_M = REG_8_M(BDH_SBR, 4),
+};
 
 // UART Baud Rate Registers: Low
 #define UART_BDL(base) REG_8((base) + 0x1)
-#define BDL_SBR 0 // UART Baud Rate Bits
-#define BDL_SBR_M REG_8_M(BDL_SBR, 8)
+enum {
+	BDL_SBR = 0, // UART Baud Rate Bits
+	BDL_SBR_M = REG_8_M(BDL_SBR, 8),
+};
 
 // UART Control Register 1
 #define UART_C1(base) REG_8((base) + 0x2)
-#define C1_LOOPS 7 // Loop Mode Select
-#define C1_UARTSWAI 6 // UART Stops in Wait Mode
-#define C1_RSRC 5 // Receiver Source Select
-#define C1_M 4 // 9-bit or 8-bit Mode Select
-#define C1_WAKE 3 // Receiver Wakeup Method Select
-#define C1_ILT 2 // Idle Line Type Select
-#define C1_PE 1 // Parity Enable
-#define C1_PT 0 // Parity Type
+enum {
+	C1_LOOPS = 7, // Loop Mode Select
+	C1_UARTSWAI = 6, // UART Stops in Wait Mode
+	C1_RSRC = 5, // Receiver Source Select
+	C1_M = 4, // 9-bit or 8-bit Mode Select
+	C1_WAKE = 3, // Receiver Wakeup Method Select
+	C1_ILT = 2, // Idle Line Type Select
+	C1_PE = 1, // Parity Enable
+	C1_PT = 0, // Parity Type
+};
 
 // UART Control Register 2
 #define UART_C2(base) REG_8((base) + 0x3)
-#define C2_TIE 7 // Transmitter Interrupt or DMA Transfer Enable.
-#define C2_TCIE 6 // Transmission Complete Interrupt Enable
-#define C2_RIE 5 // Receiver Full Interrupt or DMA Transfer Enable
-#define C2_ILIE 4 // Idle Line Interrupt Enable
-#define C2_TE 3 // Transmitter Enable
-#define C2_RE 2 // Receiver Enable
-#define C2_RWU 1 // Receiver Wakeup Control
-#define C2_SBK 0 // Send Break
+enum {
+	C2_TIE = 7, // Transmitter Interrupt or DMA Transfer Enable.
+	C2_TCIE = 6, // Transmission Complete Interrupt Enable
+	C2_RIE = 5, // Receiver Full Interrupt or DMA Transfer Enable
+	C2_ILIE = 4, // Idle Line Interrupt Enable
+	C2_TE = 3, // Transmitter Enable
+	C2_RE = 2, // Receiver Enable
+	C2_RWU = 1, // Receiver Wakeup Control
+	C2_SBK = 0, // Send Break
+};
 
 // UART Status Register 1
 #define UART_S1(base) REG_8((base) + 0x4)
-#define S1_TDRE 7 // Transmit Data Register Empty Flag
-#define S1_TC 6 // Transmit Complete Flag
-#define S1_RDRF 5 // Receive Data Register Full Flag
-#define S1_IDLE 4 // Idle Line Flag
-#define S1_OR 3 // Receiver Overrun Flag
-#define S1_NF 2 // Noise Flag
-#define S1_FE 1 // Framing Error Flag
-#define S1_PF 0 // Parity Error Flag
+enum {
+	S1_TDRE = 7, // Transmit Data Register Empty Flag
+	S1_TC = 6, // Transmit Complete Flag
+	S1_RDRF = 5, // Receive Data Register Full Flag
+	S1_IDLE = 4, // Idle Line Flag
+	S1_OR = 3, // Receiver Overrun Flag
+	S1_NF = 2, // Noise Flag
+	S1_FE = 1, // Framing Error Flag
+	S1_PF = 0, // Parity Error Flag
+};
 
 // UART Status Register 2
 #define UART_S2(base) REG_8((base) + 0x5)
-#define S2_LBKDIF 7 // LIN Break Detect Interrupt Flag
-#define S2_RXEDGIF 6 // RxD Pin Active Edge Interrupt Flag
-#define S2_MSBF 5 // Most Significant Bit First
-#define S2_RXINV 4 // Receive Data Inversion
-#define S2_RWUID 3 // Receive Wakeup Idle Detect
-#define S2_BRK13 2 // Break Transmit Character Length
-#define S2_LBKDE 1 // LIN Break Detection Enable
-#define S2_RAF 0 // Receiver Active Flag
+enum {
+	S2_LBKDIF = 7, // LIN Break Detect Interrupt Flag
+	S2_RXEDGIF = 6, // RxD Pin Active Edge Interrupt Flag
+	S2_MSBF = 5, // Most Significant Bit First
+	S2_RXINV = 4, // Receive Data Inversion
+	S2_RWUID = 3, // Receive Wakeup Idle Detect
+	S2_BRK13 = 2, // Break Transmit Character Length
+	S2_LBKDE = 1, // LIN Break Detection Enable
+	S2_RAF = 0, // Receiver Active Flag
+};
 
 // UART Control Register 3
 #define UART_C3(base) REG_8((base) + 0x6)
-#define C3_R8 7 // Received Bit 8
-#define C3_T8 6 // Transmit Bit 8
-#define C3_TXDIR 5 // Transmitter Pin Data Direction in Single-Wire mode
-#define C3_TXINV 4 // Transmit Data Inversion.
-#define C3_ORIE 3 // Overrun Error Interrupt Enable
-#define C3_NEIE 2 // Noise Error Interrupt Enable
-#define C3_FEIE 1 // Framing Error Interrupt Enable
-#define C3_PEIE 0 // Parity Error Interrupt Enable
+enum {
+	C3_R8 = 7, // Received Bit 8
+	C3_T8 = 6, // Transmit Bit 8
+	C3_TXDIR = 5, // Transmitter Pin Data Direction in Single-Wire mode
+	C3_TXINV = 4, // Transmit Data Inversion.
+	C3_ORIE = 3, // Overrun Error Interrupt Enable
+	C3_NEIE = 2, // Noise Error Interrupt Enable
+	C3_FEIE = 1, // Framing Error Interrupt Enable
+	C3_PEIE = 0, // Parity Error Interrupt Enable
+};
 
 // UART Data Register
 #define UART_D(base) REG_8((base) + 0x7)
-#define D_RT 0
-#define D_RT_M REG_8_M(D_RT, 8)
+enum {
+	D_RT = 0,
+	D_RT_M = REG_8_M(D_RT, 8),
+};
 
 // UART Match Address Registers 1
 #define UART_MA1(base) REG_8((base) + 0x8)
-#define MA1_MA 0 // Match Address
-#define MA1_MA_M REG_8_M(MA1_M, 8)
+enum {
+	MA1_MA = 0, // Match Address
+	MA1_MA_M = REG_8_M(MA1_M, 8),
+};
 
 // UART Match Address Registers 2
 #define UART_MA2(base) REG_8((base) + 0x9)
-#define MA2_MA 0 // Match Address
-#define MA2_MA_M REG_8_M(MA2_M, 8)
+enum {
+	MA2_MA = 0, // Match Address
+	MA2_MA_M = REG_8_M(MA2_M, 8),
+};
 
 // UART Control Register 4
 #define UART_C4(base) REG_8((base) + 0xA)
-#define C4_MAEN1 7 // Match Address Mode Enable 1
-#define C4_MAEN2 6 // Match Address Mode Enable 2
-#define C4_M10 5 // 10-bit Mode Select
-#define C4_BRFA 0 // Baud Rate Fine Adjust
-#define C4_BRFA_M REG_8_M(C4_BRFA, 5)
+enum {
+	C4_MAEN1 = 7, // Match Address Mode Enable 1
+	C4_MAEN2 = 6, // Match Address Mode Enable 2
+	C4_M10 = 5, // 10-bit Mode Select
+	C4_BRFA = 0, // Baud Rate Fine Adjust
+	C4_BRFA_M = REG_8_M(C4_BRFA, 5),
+};
 
 // UART Control Register 5
 #define UART_C5(base) REG_8((base) + 0xB)
-#define C5_TDMAS 7 // Transmitter DMA Select
-#define C5_RDMAS 5 // Receiver Full DMA Select
+enum {
+	C5_TDMAS = 7, // Transmitter DMA Select
+	C5_RDMAS = 5, // Receiver Full DMA Select
+};
 
 // UART Extended Data Register
 #define UART_ED(base) REG_8((base) + 0xC)
-#define ED_NOISY 7 // Dataword contained in D and C3[R8] received with noise.
-#define ED_PARITYE 6 // Dataword contained in D and C3[R8] received with a parity error.
+enum {
+	ED_NOISY = 7, // Dataword contained in D and C3[R8] received with noise.
+	ED_PARITYE = 6, // Dataword contained in D and C3[R8] received with a parity error.
+};
 
 // UART Modem Register
 #define UART_MODEM(base) REG_8((base) + 0xD)
-#define MODEM_RXRTSE 3 // Receiver request-to-send enable
-#define MODEM_TXRTSPOL 2 // Transmitter request-to-send polarity
-#define MODEM_TXRTSE 1 // Transmitter request-to-send enable
-#define MODEM_TXCTSE 0 // Transmitter clear-to-send enable
+enum {
+	MODEM_RXRTSE = 3, // Receiver request-to-send enable
+	MODEM_TXRTSPOL = 2, // Transmitter request-to-send polarity
+	MODEM_TXRTSE = 1, // Transmitter request-to-send enable
+	MODEM_TXCTSE = 0, // Transmitter clear-to-send enable
+};
 
 // UART Infrared Register
 #define UART_IR(base) REG_8((base) + 0xE)
-#define IR_IREN 2 // Infrared enable
-#define IR_TNP 0 // Transmitter narrow pulse
-#define IR_TNP_M REG_8_M(IR_TNP, 2)
+enum {
+	IR_IREN = 2, // Infrared enable
+	IR_TNP = 0, // Transmitter narrow pulse
+	IR_TNP_M = REG_8_M(IR_TNP, 2),
+};
 
 // UART FIFO Parameters
 #define UART_PFIFO(base) REG_8((base) + 0x10)
-#define PFIFO_TXFE 7 // Transmit FIFO Enable
-#define PFIFO_TXFIFOSIZE 4 // Transmit FIFO, Buffer Depth
-#define PFIFO_TXFIFOSIZE_M REG_8_M(PFIFO_TXFIFOSIZE, 3)
-#define PFIFO_RXFE 3 // Receive FIFO Enable
-#define PFIFO_RXFIFOSIZE 0 // Receive FIFO, Buffer Depth
-#define PFIFO_RXFIFOSIZE_M REG_8_M(PFIFO_RXFIFOSIZE, 3)
+enum {
+	PFIFO_TXFE = 7, // Transmit FIFO Enable
+	PFIFO_TXFIFOSIZE = 4, // Transmit FIFO, Buffer Depth
+	PFIFO_TXFIFOSIZE_M = REG_8_M(PFIFO_TXFIFOSIZE, 3),
+	PFIFO_RXFE = 3, // Receive FIFO Enable
+	PFIFO_RXFIFOSIZE = 0, // Receive FIFO, Buffer Depth
+	PFIFO_RXFIFOSIZE_M = REG_8_M(PFIFO_RXFIFOSIZE, 3),
+};
 
 // UART FIFO Control Register
 #define UART_CFIFO(base) REG_8((base) + 0x11)
-#define CFIFO_TXFLUSH 7 // Transmit FIFO/Buffer Flush
-#define CFIFO_RXFLUSH 6 // Receive FIFO/Buffer Flush
-#define CFIFO_RXOFE 2 // Receive FIFO Overflow Interrupt Enable
-#define CFIFO_TXOFE 1 // Transmit FIFO Overflow Interrupt Enable
-#define CFIFO_RXUFE 0 // Receive FIFO Underflow Interrupt Enable
+enum {
+	CFIFO_TXFLUSH = 7, // Transmit FIFO/Buffer Flush
+	CFIFO_RXFLUSH = 6, // Receive FIFO/Buffer Flush
+	CFIFO_RXOFE = 2, // Receive FIFO Overflow Interrupt Enable
+	CFIFO_TXOFE = 1, // Transmit FIFO Overflow Interrupt Enable
+	CFIFO_RXUFE = 0, // Receive FIFO Underflow Interrupt Enable
+};
 
 // UART FIFO Status Register
 #define UART_SFIFO(base) REG_8((base) + 0x12)
-#define SFIFO_TXEMPT 7 // Transmit Buffer/FIFO Empty
-#define SFIFO_RXEMPT 6 // Receive Buffer/FIFO Empty
-#define SFIFO_RXOF 2 // Receiver Buffer Overflow Flag
-#define SFIFO_TXOF 1 // Transmitter Buffer Overflow Flag
-#define SFIFO_RXUF 0 // Receiver Buffer Underflow Flag
+enum {
+	SFIFO_TXEMPT = 7, // Transmit Buffer/FIFO Empty
+	SFIFO_RXEMPT = 6, // Receive Buffer/FIFO Empty
+	SFIFO_RXOF = 2, // Receiver Buffer Overflow Flag
+	SFIFO_TXOF = 1, // Transmitter Buffer Overflow Flag
+	SFIFO_RXUF = 0, // Receiver Buffer Underflow Flag
+};
 
 // UART FIFO Transmit Watermark
 #define UART_TWFIFO(base) REG_8((base) + 0x13)
-#define TWFIFO_TXWATER 0 // Transmit Watermark
-#define TWFIFO_TXWATER_M REG_8_M(TWFIFO_TXWATER, 8)
+enum {
+	TWFIFO_TXWATER = 0, // Transmit Watermark
+	TWFIFO_TXWATER_M = REG_8_M(TWFIFO_TXWATER, 8),
+};
 
 // UART FIFO Transmit Count
 #define UART_TCFIFO(base) REG_8((base) + 0x14)
-#define TCFIFO_TXCOUNT 0 // Transmit Counter
-#define TCFIFO_TXCOUNT_M REG_8_M(TCFIFO_TXCOUNT, 8)
+enum {
+	TCFIFO_TXCOUNT = 0, // Transmit Counter
+	TCFIFO_TXCOUNT_M = REG_8_M(TCFIFO_TXCOUNT, 8),
+};
 
 // UART FIFO Receive Watermark
 #define UART_RWFIFO(base) REG_8((base) + 0x15)
-#define RWFIFO_RXWATER 0 // Receive Watermark
-#define RWFIFO_RXWATER_M REG_8_M(RWFIFO_RXWATER, 8)
+enum {
+	RWFIFO_RXWATER = 0, // Receive Watermark
+	RWFIFO_RXWATER_M = REG_8_M(RWFIFO_RXWATER, 8),
+};
 
 // UART FIFO Receive Count
 #define UART_RCFIFO(base) REG_8((base) + 0x16)
-#define RCFIFO_RXCOUNT 0
-#define RCFIFO_RXCOUNT_M REG_8_M(RCFIFO_RXCOUNT, 8)
+enum {
+	RCFIFO_RXCOUNT = 0,
+	RCFIFO_RXCOUNT_M = REG_8_M(RCFIFO_RXCOUNT, 8),
+};
 
 // UART 0 Only
 
diff --git a/reg/usbotg.h b/reg/usbotg.h
index a806cbf..0028d1d 100644
--- a/reg/usbotg.h
+++ b/reg/usbotg.h
@@ -5,198 +5,253 @@
 
 // Peripheral ID register
 #define USB0_PERID REG_8(0x40072000)
-#define PERID_ID 0 // Peripheral Identification
-#define PERID_ID_M REG_8_M(PERID_ID, 6)
+enum {
+	PERID_ID = 0, // Peripheral Identification
+	PERID_ID_M = REG_8_M(PERID_ID, 6),
+};
 
 // Peripheral ID Complement register
 #define USB0_IDCOMP REG_8(0x40072004)
-#define IDCOMP_NID 0 // Ones complement of peripheral identification bits.
-#define IDCOMP_NID_M REG_8_M(IDCOMP_NID, 6)
+enum {
+	IDCOMP_NID = 0, // Ones complement of peripheral identification bits.
+	IDCOMP_NID_M = REG_8_M(IDCOMP_NID, 6),
+};
 
 // Peripheral Revision register
 #define USB0_REV REG_8(0x40072008)
-#define REV_REV 0 // Revision
-#define REV_REV_M REG_8_M(REV_REV, 8)
+enum {
+	REV_REV = 0, // Revision
+	REV_REV_M = REG_8_M(REV_REV, 8),
+};
 
 // Peripheral Additional Info register
 #define USB0_ADDINFO REG_8(0x4007200C)
-#define ADDINFO_IRQNUM 3 // Assigned Interrupt Request Number.
-#define ADDINFO_IRQNUM_M REG_8_M(ADDINFO_IRQNUM, 5)
-#define ADDINFO_IEHOST 0 // Set if SIE is in host mode.
+enum {
+	ADDINFO_IRQNUM = 3, // Assigned Interrupt Request Number.
+	ADDINFO_IRQNUM_M = REG_8_M(ADDINFO_IRQNUM, 5),
+	ADDINFO_IEHOST = 0, // Set if SIE is in host mode.
+};
 
 // OTG Interrupt Status register
 #define USB0_OTGISTAT REG_8(0x40072010)
-#define OTGISTAT_IDCHG 7 // Set on change in the ID Signal from the USB connector.
-#define OTGISTAT_ONEMSEC 6 // Set on 1 ms timer expire.
-#define OTGISTAT_LINE_STATE_CHG 5 // Set when USB line state changes.
-#define OTGISTAT_SESSVLDCHG 3
-#define OTGISTAT_B_SESS_CHG 2
-#define OTGISTAT_AVBUSCHG 0
+enum {
+	OTGISTAT_IDCHG = 7, // Set on change in the ID Signal from the USB connector.
+	OTGISTAT_ONEMSEC = 6, // Set on 1 ms timer expire.
+	OTGISTAT_LINE_STATE_CHG = 5, // Set when USB line state changes.
+	OTGISTAT_SESSVLDCHG = 3,
+	OTGISTAT_B_SESS_CHG = 2,
+	OTGISTAT_AVBUSCHG = 0,
+};
 
 // OTG Interrupt Control Register
 #define USB0_OTGICR REG_8(0x40072014)
-#define OTGICR_IDEN 7 // ID Interrupt Enable
-#define OTGICR_ONEMSECEN 6 // One Millisecond Interrupt Enable
-#define OTGICR_LINESTATEEN 5 // Line State Change Interrupt Enable
-#define OTGICR_SESSVLDEN 3 // Session Valid Interrupt Enable
-#define OTGICR_BSESSEN 2 // B Session END Interrupt Enable
-#define OTGICR_AVBUSEN 0 // A VBUS Valid Interrupt Enable
+enum {
+	OTGICR_IDEN = 7, // ID Interrupt Enable
+	OTGICR_ONEMSECEN = 6, // One Millisecond Interrupt Enable
+	OTGICR_LINESTATEEN = 5, // Line State Change Interrupt Enable
+	OTGICR_SESSVLDEN = 3, // Session Valid Interrupt Enable
+	OTGICR_BSESSEN = 2, // B Session END Interrupt Enable
+	OTGICR_AVBUSEN = 0, // A VBUS Valid Interrupt Enable
+};
 
 // OTG Status register
 #define USB0_OTGSTAT REG_8(0x40072018)
-#define OTGSTAT_ID 7
-#define OTGSTAT_ONEMSECEN 6
-#define OTGSTAT_LINESTATESTABLE 5
-#define OTGSTAT_SESS_VLD 3
-#define OTGSTAT_BSESSEND 2
-#define OTGSTAT_AVBUSVLD 0
+enum {
+	OTGSTAT_ID = 7,
+	OTGSTAT_ONEMSECEN = 6,
+	OTGSTAT_LINESTATESTABLE = 5,
+	OTGSTAT_SESS_VLD = 3,
+	OTGSTAT_BSESSEND = 2,
+	OTGSTAT_AVBUSVLD = 0,
+};
 
 // OTG Control register
 #define USB0_OTGCTL REG_8(0x4007201C)
-#define OTGCTL_DPHIGH 7 // D+ Data Line pullup resistor enable
-#define OTGCTL_DPLOW 5 // D+ Data Line pull-down resistor enable
-#define OTGCTL_DMLOW 4 // D– Data Line pull-down resistor enable
-#define OTGCTL_OTGEN 2 // On-The-Go pullup/pulldown resistor enable
+enum {
+	OTGCTL_DPHIGH = 7, // D+ Data Line pullup resistor enable
+	OTGCTL_DPLOW = 5, // D+ Data Line pull-down resistor enable
+	OTGCTL_DMLOW = 4, // D– Data Line pull-down resistor enable
+	OTGCTL_OTGEN = 2, // On-The-Go pullup/pulldown resistor enable
+};
 
 // Interrupt Status register
 #define USB0_ISTAT REG_8(0x40072080)
-#define ISTAT_STALL 7 // Stall Interrupt
-#define ISTAT_ATTACH 6 // Attach Interrupt
-#define ISTAT_RESUME 5
-#define ISTAT_SLEEP 4
-#define ISTAT_TOKDNE 3
-#define ISTAT_SOFTOK 2
-#define ISTAT_ERROR 1
-#define ISTAT_USBRST 0
+enum {
+	ISTAT_STALL = 7, // Stall Interrupt
+	ISTAT_ATTACH = 6, // Attach Interrupt
+	ISTAT_RESUME = 5,
+	ISTAT_SLEEP = 4,
+	ISTAT_TOKDNE = 3,
+	ISTAT_SOFTOK = 2,
+	ISTAT_ERROR = 1,
+	ISTAT_USBRST = 0,
+};
 
 // Interrupt Enable register
 #define USB0_INTEN REG_8(0x40072084)
-#define INTEN_STALLEN 7 // STALL Interrupt Enable
-#define INTEN_ATTACHEN 6 // ATTACH Interrupt Enable
-#define INTEN_RESUMEEN 5 // RESUME Interrupt Enable
-#define INTEN_SLEEPEN 4 // SLEEP Interrupt Enable
-#define INTEN_TOKDNEEN 3 // TOKDNE Interrupt Enable
-#define INTEN_SOFTOKEN 2 // SOFTOK Interrupt Enable
-#define INTEN_ERROREN 1 // ERROR Interrupt Enable
-#define INTEN_USBRSTEN 0 // USBRST Interrupt Enable
+enum {
+	INTEN_STALLEN = 7, // STALL Interrupt Enable
+	INTEN_ATTACHEN = 6, // ATTACH Interrupt Enable
+	INTEN_RESUMEEN = 5, // RESUME Interrupt Enable
+	INTEN_SLEEPEN = 4, // SLEEP Interrupt Enable
+	INTEN_TOKDNEEN = 3, // TOKDNE Interrupt Enable
+	INTEN_SOFTOKEN = 2, // SOFTOK Interrupt Enable
+	INTEN_ERROREN = 1, // ERROR Interrupt Enable
+	INTEN_USBRSTEN = 0, // USBRST Interrupt Enable
+};
 
 // Error Interrupt Status register
 #define USB0_ERRSTAT REG_8(0x40072088)
-#define ERRSTAT_BTSERR 7
-#define ERRSTAT_DMAERR 5
-#define ERRSTAT_BTOERR 4
-#define ERRSTAT_DFN8 3
-#define ERRSTAT_CRC16 2
-#define ERRSTAT_CRC5EOF 1
-#define ERRSTAT_PIDERR 0
+enum {
+	ERRSTAT_BTSERR = 7,
+	ERRSTAT_DMAERR = 5,
+	ERRSTAT_BTOERR = 4,
+	ERRSTAT_DFN8 = 3,
+	ERRSTAT_CRC16 = 2,
+	ERRSTAT_CRC5EOF = 1,
+	ERRSTAT_PIDERR = 0,
+};
 
 // Error Interrupt Enable register
 #define USB0_ERREN REG_8(0x4007208C)
-#define ERREN_BTSERREN 7 // BTSERR Interrupt Enable
-#define ERREN_DMAERREN 5 // DMAERR Interrupt Enable
-#define ERREN_BTOERREN 4 // BTOERR Interrupt Enable
-#define ERREN_DFN8EN 3 // DFN8 Interrupt Enable
-#define ERREN_CRC16EN 2 // CRC16 Interrupt Enable
-#define ERREN_CRC5EOFEN 1 // CRC5EOF Interrupt Enable
-#define ERREN_PIDERREN 0 // PIDERR Interrupt Enable
+enum {
+	ERREN_BTSERREN = 7, // BTSERR Interrupt Enable
+	ERREN_DMAERREN = 5, // DMAERR Interrupt Enable
+	ERREN_BTOERREN = 4, // BTOERR Interrupt Enable
+	ERREN_DFN8EN = 3, // DFN8 Interrupt Enable
+	ERREN_CRC16EN = 2, // CRC16 Interrupt Enable
+	ERREN_CRC5EOFEN = 1, // CRC5EOF Interrupt Enable
+	ERREN_PIDERREN = 0, // PIDERR Interrupt Enable
+};
 
 // Status register
 #define USB0_STAT REG_8(0x40072090)
-#define STAT_ENDP 4
-#define STAT_ENDP_M REG_8_M(STAT_ENDP, 4)
-#define STAT_TX 3 // Transmit Indicator
-#define STAT_ODD 2
+enum {
+	STAT_ENDP = 4,
+	STAT_ENDP_M = REG_8_M(STAT_ENDP, 4),
+	STAT_TX = 3, // Transmit Indicator
+	STAT_ODD = 2,
+};
 
 // Control register
 #define USB0_CTL REG_8(0x40072094)
-#define CTL_JSTATE 7 // Live USB differential receiver JSTATE signal
-#define CTL_SE0 6 // Live USB Single Ended Zero signal
-#define CTL_TXSUSPENDTOKENBUSY 5 
-#define CTL_RESET 4
-#define CTL_HOSTMODEEN 3
-#define CTL_RESUME 2
-#define CTL_ODDRST 1
-#define CTL_USBENSOFEN 0 // USB Enable
+enum {
+	CTL_JSTATE = 7, // Live USB differential receiver JSTATE signal
+	CTL_SE0 = 6, // Live USB Single Ended Zero signal
+	CTL_TXSUSPENDTOKENBUSY = 5,
+	CTL_RESET = 4,
+	CTL_HOSTMODEEN = 3,
+	CTL_RESUME = 2,
+	CTL_ODDRST = 1,
+	CTL_USBENSOFEN = 0, // USB Enable
+};
 
 // Address register
 #define USB0_ADDR REG_8(0x40072098)
-#define ADDR_LSEN 7
-#define ADDR_ADDR 0
-#define ADDR_ADDR_M REG_8_M(ADDR_ADDR, 7)
+enum {
+	ADDR_LSEN = 7,
+	ADDR_ADDR = 0,
+	ADDR_ADDR_M = REG_8_M(ADDR_ADDR, 7),
 
 // BDT Page Register 1
 #define USB0_BDTPAGE1 REG_8(0x4007209C)
-#define BDTPAGE1_BDTBA 1
-#define BDTPAGE1_BDTBA_M REG_8_M(BDTPAGE1_BDTBA, 7)
+enum {
+	BDTPAGE1_BDTBA = 1,
+	BDTPAGE1_BDTBA_M = REG_8_M(BDTPAGE1_BDTBA, 7),
+};
 
 // Frame Number Register Low
 #define USB0_FRMNUML REG_8(0x400720A0)
-#define FRMNUML_FRM 0
-#define FRMNUML_FRM_M REG_8_M(FRMNUML_FRM, 8)
+enum {
+	FRMNUML_FRM = 0,
+	FRMNUML_FRM_M = REG_8_M(FRMNUML_FRM, 8),
+};
 
 // Frame Number Register High
 #define USB0_FRMNUMH REG_8(0x400720A4)
-#define FRMNUMH_FRM 0
-#define FRMNUMH_FRM_M REG_8_M(FRMNUMH_FRM_M, 3)
+enum {
+	FRMNUMH_FRM = 0,
+	FRMNUMH_FRM_M = REG_8_M(FRMNUMH_FRM_M, 3),
+};
 
 // Token register
 #define USB0_TOKEN REG_8(0x400720A8)
-#define TOKEN_TOKENPID 4
-#define TOKEN_TOKENPID_M REG_8_M(TOKEN_TOKENPID, 4)
-#define TOKEN_TOKENENDPT 0
-#define TOKEN_TOKENENDPT_M REG_8_M(TOKEN_TOKENENDPT, 4)
+enum {
+	TOKEN_TOKENPID = 4,
+	TOKEN_TOKENPID_M = REG_8_M(TOKEN_TOKENPID, 4),
+	TOKEN_TOKENENDPT = 0,
+	TOKEN_TOKENENDPT_M = REG_8_M(TOKEN_TOKENENDPT, 4),
+};
 
 // SOF Threshold Register
 #define USB0_SOFTHLD REG_8(0x400720AC)
-#define SOFTHLD_CNT 0
-#define SOFTHLD_CNT_M REG_8_M(SOFTHLD_CNT, 8)
+enum {
+	SOFTHLD_CNT = 0,
+	SOFTHLD_CNT_M = REG_8_M(SOFTHLD_CNT, 8),
+};
 
 // BDT Page Register 2
 #define USB0_BDTPAGE2 REG_8(0x400720B0)
-#define BDTPAGE2_BDTBA 0
-#define BDTPAGE2_BDTBA_M REG_8_M(BDTPAGE2_BDTBA, 8)
+enum {
+	BDTPAGE2_BDTBA = 0,
+	BDTPAGE2_BDTBA_M = REG_8_M(BDTPAGE2_BDTBA, 8),
+};
 
 // BDT Page Register 3
 #define USB0_BDTPAGE3 REG_8(0x400720B4)
-#define BDTPAGE3_BDTBA 0
-#define BDTPAGE3_BDTBA_M REG_8_M(BDTPAGE3_BDTBA, 8)
+enum {
+	BDTPAGE3_BDTBA = 0,
+	BDTPAGE3_BDTBA_M = REG_8_M(BDTPAGE3_BDTBA, 8),
+};
 
 // Endpoint Control register
 #define USB0_ENDPT(n) REG_8(0x400720C0 + 4 * (n))
-#define ENDPT_HOSTWOHUB 7
-#define ENDPT_RETRYDIS 6
-#define ENDPT_EPCTLDIS 4
-#define ENDPT_EPRXEN 3
-#define ENDPT_EPTXEN 2
-#define ENDPT_EPSTALL 1
-#define ENDPT_EPHSHK 0
+enum {
+	ENDPT_HOSTWOHUB = 7,
+	ENDPT_RETRYDIS = 6,
+	ENDPT_EPCTLDIS = 4,
+	ENDPT_EPRXEN = 3,
+	ENDPT_EPTXEN = 2,
+	ENDPT_EPSTALL = 1,
+	ENDPT_EPHSHK = 0,
+};
 
 // USB Control register
 #define USB0_USBCTRL REG_8(0x40072100)
-#define USBCTRL_SUSP 7 // Places the USB transceiver into the suspend state.
-#define USBCTRL_PDE 6 // Enables the weak pulldowns on the USB transceiver.
+enum {
+	USBCTRL_SUSP = 7, // Places the USB transceiver into the suspend state.
+	USBCTRL_PDE = 6, // Enables the weak pulldowns on the USB transceiver.
+};
 
 // USB OTG Observe register
 #define USB0_OBSERVE REG_8(0x40072104)
-#define OBSERVE_DPPU 7 // Provides observability of the D+ Pullup
-#define OBSERVE_DPPD 6 // Provides observability of the D+ Pulldown
-#define OBSERVE_DMPD 4 // Provides observability of the D- Pulldown
+enum {
+	OBSERVE_DPPU = 7, // Provides observability of the D+ Pullup
+	OBSERVE_DPPD = 6, // Provides observability of the D+ Pulldown
+	OBSERVE_DMPD = 4, // Provides observability of the D- Pulldown
+};
 
 // USB OTG Control register
 #define USB0_CONTROL REG_8(0x40072108)
-#define CONTROL_DPPULLUPNONOTG 4 // DP Pullup in non-OTG device mode state
+enum {
+	CONTROL_DPPULLUPNONOTG = 4, // DP Pullup in non-OTG device mode state
+};
 
 // USB Transceiver Control Register 0
 #define USB0_USBTRC0 REG_8(0x4007210C)
-#define USBTRC0_USBRESET 7 // USB Reset
-#define USBTRC0_USBRESMEN 5 // Asynchronous Resume Interrupt Enable
-#define USBTRC0_SYNC_DET 1 // Synchronous USB Interrupt Detect
-#define USBTRC0_USB_RESUME_INT 0 // USB Asynchronous Interrupt
+enum {
+	USBTRC0_USBRESET = 7, // USB Reset
+	USBTRC0_USBRESMEN = 5, // Asynchronous Resume Interrupt Enable
+	USBTRC0_SYNC_DET = 1, // Synchronous USB Interrupt Detect
+	USBTRC0_USB_RESUME_INT = 0, // USB Asynchronous Interrupt
+};
 
 // Frame Adjust Register
 #define USB0_USBFRMADJUST REG_8(0x40072114)
-#define USBFRMADJUST_ADJ 0
-#define USBFRMADJUST_ADJ_M REG_8_M(USBFRMADJUST_ADJ, 8)
+enum {
+	USBFRMADJUST_ADJ = 0,
+	USBFRMADJUST_ADJ_M = REG_8_M(USBFRMADJUST_ADJ, 8),
+};
 
 // TODO: Move elsewhere
 __attribute__ ((packed))
@@ -204,30 +259,31 @@ struct usb0_bd {
 	uint32_t desc;
 	void *addr;
 };
-//#define USB0_BD(desc, addr) (struct usb0_bd){(desc), (addr)}
 #define USB0_BD_INIT(size, data01) ((size) << BD_BC | BV(BD_OWN) | \
 				    ((data01) & 1) << BD_DATA01 | BV(BD_DTS))
-#define BD_BC 16 // Byte Count
-#define BD_BC_M REG_32_M(BD_BC, 10)
-#define BD_OWN 7
-#define BD_DATA01 6
-#define BD_KEEP 5
-#define BD_NINC 4
-#define BD_DTS 3
-#define BD_BDT_STALL 2
-#define BD_TOK_PID 2
-#define BD_TOK_PID_M REG_32_M(BD_TOK_PID, 4)
-
-#define BD_TOK_PID_OUT 0x1
-#define BD_TOK_PID_IN 0x9
-#define BD_TOK_PID_SETUP 0xd
-
-#define BD_TOK_PID_DATA0 0x3
-#define BD_TOK_PID_DATA1 0xb
-#define BD_TOK_PID_ACK 0x2
-#define BD_TOK_PID_STALL 0xe
-#define BD_TOK_PID_NAK 0xa
-#define BD_TOK_PID_TIMEOUT 0x0
-#define BD_TOK_PID_ERROR 0xf
+enum {
+	BD_BC = 16, // Byte Count
+	BD_BC_M = REG_32_M(BD_BC, 10),
+	BD_OWN = 7,
+	BD_DATA01 = 6,
+	BD_KEEP = 5,
+	BD_NINC = 4,
+	BD_DTS = 3,
+	BD_BDT_STALL = 2,
+	BD_TOK_PID = 2,
+	BD_TOK_PID_M = REG_32_M(BD_TOK_PID, 4),
+
+	BD_TOK_PID_OUT = 0x1,
+	BD_TOK_PID_IN = 0x9,
+	BD_TOK_PID_SETUP = 0xd,
+
+	BD_TOK_PID_DATA0 = 0x3,
+	BD_TOK_PID_DATA1 = 0xb,
+	BD_TOK_PID_ACK = 0x2,
+	BD_TOK_PID_STALL = 0xe,
+	BD_TOK_PID_NAK = 0xa,
+	BD_TOK_PID_TIMEOUT = 0x0,
+	BD_TOK_PID_ERROR = 0xf,
+};
 
 #endif /* MK20DX256_REG_USBOTG_H */
diff --git a/reg/wdog.h b/reg/wdog.h
index 5d9d5eb..e4db084 100644
--- a/reg/wdog.h
+++ b/reg/wdog.h
@@ -3,35 +3,51 @@
 
 #include <reg/regdefs.h>
 
-#define WDOG_STCTRLH REG_16(0x40052000) /* Watchdog Status and Control Register High */
-#define STCTRLH_DISTESTWDOG 14 /* Functional test mode disable */
-#define STCTRLH_BYTESEL 12 /* Byte test mode byte selector */
-#define STCTRLH_BYTESEL_M REG_16_M(STCTRLH_BYTESEL, 2)
-#define STCTRLH_TESTSEL 11 /* Functional test mode test selector */
-#define STCTRLH_TESTWDOG 10 /* Functional test mode enable */
-#define STCTRLH_WAITEN 7 /* Wait mode WDOG enable */
-#define STCTRLH_STOPEN 6 /* Stop mode WDOG enable */
-#define STCTRLH_DBGEN 5 /* Debug mode WDOG enable */
-#define STCTRLH_ALLOWUPDATE 4 /* Allow further updates to write-once registers */
-#define STCTRLH_WINEN 3 /* Windowing mode enable */
-#define STCTRLH_IRQRSTEN 2 /* Debug breadcrumbs feature enable */
-#define STCTRLH_CLKSRC 1 /* Clock source selector */
-#define STCTRLH_WDOGEN 0 /* WDOG enable */
+// Watchdog Status and Control Register High
+#define WDOG_STCTRLH REG_16(0x40052000)
+enum {
+	STCTRLH_DISTESTWDOG = 14, // Functional test mode disable
+	STCTRLH_BYTESEL = 12, // Byte test mode byte selector
+	STCTRLH_BYTESEL_M = REG_16_M(STCTRLH_BYTESEL, 2),
+	STCTRLH_TESTSEL = 11, // Functional test mode test selector
+	STCTRLH_TESTWDOG = 10, // Functional test mode enable
+	STCTRLH_WAITEN = 7, // Wait mode WDOG enable
+	STCTRLH_STOPEN = 6, // Stop mode WDOG enable
+	STCTRLH_DBGEN = 5, // Debug mode WDOG enable
+	STCTRLH_ALLOWUPDATE = 4, // Allow further updates to write-once registers
+	STCTRLH_WINEN = 3, // Windowing mode enable
+	STCTRLH_IRQRSTEN = 2, // Debug breadcrumbs feature enable
+	STCTRLH_CLKSRC = 1, // Clock source selector
+	STCTRLH_WDOGEN = 0, // WDOG enable
+};
 
-#define WDOG_STCTRLL REG_16(0x40052002) /* Watchdog Status and Control Register Low */
-#define WDOG_TOVALH REG_16(0x40052004) /* Watchdog Time-out Value Register High */
-#define WDOG_TOVALL REG_16(0x40052006) /* Watchdog Time-out Value Register Low */
-#define WDOG_WINH REG_16(0x40052008) /* Watchdog Window Register High */
-#define WDOG_WINL REG_16(0x4005200A) /* Watchdog Window Register Low */
-#define WDOG_REFRESH REG_16(0x4005200C) /* Watchdog Refresh register */
+// Watchdog Status and Control Register Low
+#define WDOG_STCTRLL REG_16(0x40052002)
+// Watchdog Time-out Value Register High
+#define WDOG_TOVALH REG_16(0x40052004)
+// Watchdog Time-out Value Register Low
+#define WDOG_TOVALL REG_16(0x40052006)
+// Watchdog Window Register High
+#define WDOG_WINH REG_16(0x40052008)
+// Watchdog Window Register Low
+#define WDOG_WINL REG_16(0x4005200A)
+// Watchdog Refresh register
+#define WDOG_REFRESH REG_16(0x4005200C)
 
-#define WDOG_UNLOCK REG_16(0x4005200E) /* Watchdog Unlock Register */
-#define WDOG_UNLOCK_S1 0xC520 /* Unlock Sequence 1/2 */
-#define WDOG_UNLOCK_S2 0xD928 /* Unlock Sequence 2/2 */
+// Watchdog Unlock Register
+#define WDOG_UNLOCK REG_16(0x4005200E)
+enum {
+	WDOG_UNLOCK_S1 = 0xC520, // Unlock Sequence 1/2
+	WDOG_UNLOCK_S2 = 0xD928, // Unlock Sequence 2/2
+};
 
-#define WDOG_TMROUTH REG_16(0x40052010) /* Watchdog Timer Output Register High */
-#define WDOG_TMROUTL REG_16(0x40052012) /* Watchdog Timer Output Register Low */
-#define WDOG_RSTCNT REG_16(0x40052014) /* Watchdog Reset Count register */
-#define WDOG_PRESC REG_16(0x40052016) /* Watchdog Prescaler register */
+// Watchdog Timer Output Register High
+#define WDOG_TMROUTH REG_16(0x40052010)
+// Watchdog Timer Output Register Low
+#define WDOG_TMROUTL REG_16(0x40052012)
+// Watchdog Reset Count register
+#define WDOG_RSTCNT REG_16(0x40052014)
+// Watchdog Prescaler register
+#define WDOG_PRESC REG_16(0x40052016)
 
 #endif /* MK20DX256_REG_WDOG_H */