diff options
Diffstat (limited to 'reg/usbotg.h')
| -rw-r--r-- | reg/usbotg.h | 324 |
1 files changed, 190 insertions, 134 deletions
diff --git a/reg/usbotg.h b/reg/usbotg.h index a806cbf..0028d1d 100644 --- a/reg/usbotg.h +++ b/reg/usbotg.h @@ -5,198 +5,253 @@ // Peripheral ID register #define USB0_PERID REG_8(0x40072000) -#define PERID_ID 0 // Peripheral Identification -#define PERID_ID_M REG_8_M(PERID_ID, 6) +enum { + PERID_ID = 0, // Peripheral Identification + PERID_ID_M = REG_8_M(PERID_ID, 6), +}; // Peripheral ID Complement register #define USB0_IDCOMP REG_8(0x40072004) -#define IDCOMP_NID 0 // Ones complement of peripheral identification bits. -#define IDCOMP_NID_M REG_8_M(IDCOMP_NID, 6) +enum { + IDCOMP_NID = 0, // Ones complement of peripheral identification bits. + IDCOMP_NID_M = REG_8_M(IDCOMP_NID, 6), +}; // Peripheral Revision register #define USB0_REV REG_8(0x40072008) -#define REV_REV 0 // Revision -#define REV_REV_M REG_8_M(REV_REV, 8) +enum { + REV_REV = 0, // Revision + REV_REV_M = REG_8_M(REV_REV, 8), +}; // Peripheral Additional Info register #define USB0_ADDINFO REG_8(0x4007200C) -#define ADDINFO_IRQNUM 3 // Assigned Interrupt Request Number. -#define ADDINFO_IRQNUM_M REG_8_M(ADDINFO_IRQNUM, 5) -#define ADDINFO_IEHOST 0 // Set if SIE is in host mode. +enum { + ADDINFO_IRQNUM = 3, // Assigned Interrupt Request Number. + ADDINFO_IRQNUM_M = REG_8_M(ADDINFO_IRQNUM, 5), + ADDINFO_IEHOST = 0, // Set if SIE is in host mode. +}; // OTG Interrupt Status register #define USB0_OTGISTAT REG_8(0x40072010) -#define OTGISTAT_IDCHG 7 // Set on change in the ID Signal from the USB connector. -#define OTGISTAT_ONEMSEC 6 // Set on 1 ms timer expire. -#define OTGISTAT_LINE_STATE_CHG 5 // Set when USB line state changes. -#define OTGISTAT_SESSVLDCHG 3 -#define OTGISTAT_B_SESS_CHG 2 -#define OTGISTAT_AVBUSCHG 0 +enum { + OTGISTAT_IDCHG = 7, // Set on change in the ID Signal from the USB connector. + OTGISTAT_ONEMSEC = 6, // Set on 1 ms timer expire. + OTGISTAT_LINE_STATE_CHG = 5, // Set when USB line state changes. + OTGISTAT_SESSVLDCHG = 3, + OTGISTAT_B_SESS_CHG = 2, + OTGISTAT_AVBUSCHG = 0, +}; // OTG Interrupt Control Register #define USB0_OTGICR REG_8(0x40072014) -#define OTGICR_IDEN 7 // ID Interrupt Enable -#define OTGICR_ONEMSECEN 6 // One Millisecond Interrupt Enable -#define OTGICR_LINESTATEEN 5 // Line State Change Interrupt Enable -#define OTGICR_SESSVLDEN 3 // Session Valid Interrupt Enable -#define OTGICR_BSESSEN 2 // B Session END Interrupt Enable -#define OTGICR_AVBUSEN 0 // A VBUS Valid Interrupt Enable +enum { + OTGICR_IDEN = 7, // ID Interrupt Enable + OTGICR_ONEMSECEN = 6, // One Millisecond Interrupt Enable + OTGICR_LINESTATEEN = 5, // Line State Change Interrupt Enable + OTGICR_SESSVLDEN = 3, // Session Valid Interrupt Enable + OTGICR_BSESSEN = 2, // B Session END Interrupt Enable + OTGICR_AVBUSEN = 0, // A VBUS Valid Interrupt Enable +}; // OTG Status register #define USB0_OTGSTAT REG_8(0x40072018) -#define OTGSTAT_ID 7 -#define OTGSTAT_ONEMSECEN 6 -#define OTGSTAT_LINESTATESTABLE 5 -#define OTGSTAT_SESS_VLD 3 -#define OTGSTAT_BSESSEND 2 -#define OTGSTAT_AVBUSVLD 0 +enum { + OTGSTAT_ID = 7, + OTGSTAT_ONEMSECEN = 6, + OTGSTAT_LINESTATESTABLE = 5, + OTGSTAT_SESS_VLD = 3, + OTGSTAT_BSESSEND = 2, + OTGSTAT_AVBUSVLD = 0, +}; // OTG Control register #define USB0_OTGCTL REG_8(0x4007201C) -#define OTGCTL_DPHIGH 7 // D+ Data Line pullup resistor enable -#define OTGCTL_DPLOW 5 // D+ Data Line pull-down resistor enable -#define OTGCTL_DMLOW 4 // D– Data Line pull-down resistor enable -#define OTGCTL_OTGEN 2 // On-The-Go pullup/pulldown resistor enable +enum { + OTGCTL_DPHIGH = 7, // D+ Data Line pullup resistor enable + OTGCTL_DPLOW = 5, // D+ Data Line pull-down resistor enable + OTGCTL_DMLOW = 4, // D– Data Line pull-down resistor enable + OTGCTL_OTGEN = 2, // On-The-Go pullup/pulldown resistor enable +}; // Interrupt Status register #define USB0_ISTAT REG_8(0x40072080) -#define ISTAT_STALL 7 // Stall Interrupt -#define ISTAT_ATTACH 6 // Attach Interrupt -#define ISTAT_RESUME 5 -#define ISTAT_SLEEP 4 -#define ISTAT_TOKDNE 3 -#define ISTAT_SOFTOK 2 -#define ISTAT_ERROR 1 -#define ISTAT_USBRST 0 +enum { + ISTAT_STALL = 7, // Stall Interrupt + ISTAT_ATTACH = 6, // Attach Interrupt + ISTAT_RESUME = 5, + ISTAT_SLEEP = 4, + ISTAT_TOKDNE = 3, + ISTAT_SOFTOK = 2, + ISTAT_ERROR = 1, + ISTAT_USBRST = 0, +}; // Interrupt Enable register #define USB0_INTEN REG_8(0x40072084) -#define INTEN_STALLEN 7 // STALL Interrupt Enable -#define INTEN_ATTACHEN 6 // ATTACH Interrupt Enable -#define INTEN_RESUMEEN 5 // RESUME Interrupt Enable -#define INTEN_SLEEPEN 4 // SLEEP Interrupt Enable -#define INTEN_TOKDNEEN 3 // TOKDNE Interrupt Enable -#define INTEN_SOFTOKEN 2 // SOFTOK Interrupt Enable -#define INTEN_ERROREN 1 // ERROR Interrupt Enable -#define INTEN_USBRSTEN 0 // USBRST Interrupt Enable +enum { + INTEN_STALLEN = 7, // STALL Interrupt Enable + INTEN_ATTACHEN = 6, // ATTACH Interrupt Enable + INTEN_RESUMEEN = 5, // RESUME Interrupt Enable + INTEN_SLEEPEN = 4, // SLEEP Interrupt Enable + INTEN_TOKDNEEN = 3, // TOKDNE Interrupt Enable + INTEN_SOFTOKEN = 2, // SOFTOK Interrupt Enable + INTEN_ERROREN = 1, // ERROR Interrupt Enable + INTEN_USBRSTEN = 0, // USBRST Interrupt Enable +}; // Error Interrupt Status register #define USB0_ERRSTAT REG_8(0x40072088) -#define ERRSTAT_BTSERR 7 -#define ERRSTAT_DMAERR 5 -#define ERRSTAT_BTOERR 4 -#define ERRSTAT_DFN8 3 -#define ERRSTAT_CRC16 2 -#define ERRSTAT_CRC5EOF 1 -#define ERRSTAT_PIDERR 0 +enum { + ERRSTAT_BTSERR = 7, + ERRSTAT_DMAERR = 5, + ERRSTAT_BTOERR = 4, + ERRSTAT_DFN8 = 3, + ERRSTAT_CRC16 = 2, + ERRSTAT_CRC5EOF = 1, + ERRSTAT_PIDERR = 0, +}; // Error Interrupt Enable register #define USB0_ERREN REG_8(0x4007208C) -#define ERREN_BTSERREN 7 // BTSERR Interrupt Enable -#define ERREN_DMAERREN 5 // DMAERR Interrupt Enable -#define ERREN_BTOERREN 4 // BTOERR Interrupt Enable -#define ERREN_DFN8EN 3 // DFN8 Interrupt Enable -#define ERREN_CRC16EN 2 // CRC16 Interrupt Enable -#define ERREN_CRC5EOFEN 1 // CRC5EOF Interrupt Enable -#define ERREN_PIDERREN 0 // PIDERR Interrupt Enable +enum { + ERREN_BTSERREN = 7, // BTSERR Interrupt Enable + ERREN_DMAERREN = 5, // DMAERR Interrupt Enable + ERREN_BTOERREN = 4, // BTOERR Interrupt Enable + ERREN_DFN8EN = 3, // DFN8 Interrupt Enable + ERREN_CRC16EN = 2, // CRC16 Interrupt Enable + ERREN_CRC5EOFEN = 1, // CRC5EOF Interrupt Enable + ERREN_PIDERREN = 0, // PIDERR Interrupt Enable +}; // Status register #define USB0_STAT REG_8(0x40072090) -#define STAT_ENDP 4 -#define STAT_ENDP_M REG_8_M(STAT_ENDP, 4) -#define STAT_TX 3 // Transmit Indicator -#define STAT_ODD 2 +enum { + STAT_ENDP = 4, + STAT_ENDP_M = REG_8_M(STAT_ENDP, 4), + STAT_TX = 3, // Transmit Indicator + STAT_ODD = 2, +}; // Control register #define USB0_CTL REG_8(0x40072094) -#define CTL_JSTATE 7 // Live USB differential receiver JSTATE signal -#define CTL_SE0 6 // Live USB Single Ended Zero signal -#define CTL_TXSUSPENDTOKENBUSY 5 -#define CTL_RESET 4 -#define CTL_HOSTMODEEN 3 -#define CTL_RESUME 2 -#define CTL_ODDRST 1 -#define CTL_USBENSOFEN 0 // USB Enable +enum { + CTL_JSTATE = 7, // Live USB differential receiver JSTATE signal + CTL_SE0 = 6, // Live USB Single Ended Zero signal + CTL_TXSUSPENDTOKENBUSY = 5, + CTL_RESET = 4, + CTL_HOSTMODEEN = 3, + CTL_RESUME = 2, + CTL_ODDRST = 1, + CTL_USBENSOFEN = 0, // USB Enable +}; // Address register #define USB0_ADDR REG_8(0x40072098) -#define ADDR_LSEN 7 -#define ADDR_ADDR 0 -#define ADDR_ADDR_M REG_8_M(ADDR_ADDR, 7) +enum { + ADDR_LSEN = 7, + ADDR_ADDR = 0, + ADDR_ADDR_M = REG_8_M(ADDR_ADDR, 7), // BDT Page Register 1 #define USB0_BDTPAGE1 REG_8(0x4007209C) -#define BDTPAGE1_BDTBA 1 -#define BDTPAGE1_BDTBA_M REG_8_M(BDTPAGE1_BDTBA, 7) +enum { + BDTPAGE1_BDTBA = 1, + BDTPAGE1_BDTBA_M = REG_8_M(BDTPAGE1_BDTBA, 7), +}; // Frame Number Register Low #define USB0_FRMNUML REG_8(0x400720A0) -#define FRMNUML_FRM 0 -#define FRMNUML_FRM_M REG_8_M(FRMNUML_FRM, 8) +enum { + FRMNUML_FRM = 0, + FRMNUML_FRM_M = REG_8_M(FRMNUML_FRM, 8), +}; // Frame Number Register High #define USB0_FRMNUMH REG_8(0x400720A4) -#define FRMNUMH_FRM 0 -#define FRMNUMH_FRM_M REG_8_M(FRMNUMH_FRM_M, 3) +enum { + FRMNUMH_FRM = 0, + FRMNUMH_FRM_M = REG_8_M(FRMNUMH_FRM_M, 3), +}; // Token register #define USB0_TOKEN REG_8(0x400720A8) -#define TOKEN_TOKENPID 4 -#define TOKEN_TOKENPID_M REG_8_M(TOKEN_TOKENPID, 4) -#define TOKEN_TOKENENDPT 0 -#define TOKEN_TOKENENDPT_M REG_8_M(TOKEN_TOKENENDPT, 4) +enum { + TOKEN_TOKENPID = 4, + TOKEN_TOKENPID_M = REG_8_M(TOKEN_TOKENPID, 4), + TOKEN_TOKENENDPT = 0, + TOKEN_TOKENENDPT_M = REG_8_M(TOKEN_TOKENENDPT, 4), +}; // SOF Threshold Register #define USB0_SOFTHLD REG_8(0x400720AC) -#define SOFTHLD_CNT 0 -#define SOFTHLD_CNT_M REG_8_M(SOFTHLD_CNT, 8) +enum { + SOFTHLD_CNT = 0, + SOFTHLD_CNT_M = REG_8_M(SOFTHLD_CNT, 8), +}; // BDT Page Register 2 #define USB0_BDTPAGE2 REG_8(0x400720B0) -#define BDTPAGE2_BDTBA 0 -#define BDTPAGE2_BDTBA_M REG_8_M(BDTPAGE2_BDTBA, 8) +enum { + BDTPAGE2_BDTBA = 0, + BDTPAGE2_BDTBA_M = REG_8_M(BDTPAGE2_BDTBA, 8), +}; // BDT Page Register 3 #define USB0_BDTPAGE3 REG_8(0x400720B4) -#define BDTPAGE3_BDTBA 0 -#define BDTPAGE3_BDTBA_M REG_8_M(BDTPAGE3_BDTBA, 8) +enum { + BDTPAGE3_BDTBA = 0, + BDTPAGE3_BDTBA_M = REG_8_M(BDTPAGE3_BDTBA, 8), +}; // Endpoint Control register #define USB0_ENDPT(n) REG_8(0x400720C0 + 4 * (n)) -#define ENDPT_HOSTWOHUB 7 -#define ENDPT_RETRYDIS 6 -#define ENDPT_EPCTLDIS 4 -#define ENDPT_EPRXEN 3 -#define ENDPT_EPTXEN 2 -#define ENDPT_EPSTALL 1 -#define ENDPT_EPHSHK 0 +enum { + ENDPT_HOSTWOHUB = 7, + ENDPT_RETRYDIS = 6, + ENDPT_EPCTLDIS = 4, + ENDPT_EPRXEN = 3, + ENDPT_EPTXEN = 2, + ENDPT_EPSTALL = 1, + ENDPT_EPHSHK = 0, +}; // USB Control register #define USB0_USBCTRL REG_8(0x40072100) -#define USBCTRL_SUSP 7 // Places the USB transceiver into the suspend state. -#define USBCTRL_PDE 6 // Enables the weak pulldowns on the USB transceiver. +enum { + USBCTRL_SUSP = 7, // Places the USB transceiver into the suspend state. + USBCTRL_PDE = 6, // Enables the weak pulldowns on the USB transceiver. +}; // USB OTG Observe register #define USB0_OBSERVE REG_8(0x40072104) -#define OBSERVE_DPPU 7 // Provides observability of the D+ Pullup -#define OBSERVE_DPPD 6 // Provides observability of the D+ Pulldown -#define OBSERVE_DMPD 4 // Provides observability of the D- Pulldown +enum { + OBSERVE_DPPU = 7, // Provides observability of the D+ Pullup + OBSERVE_DPPD = 6, // Provides observability of the D+ Pulldown + OBSERVE_DMPD = 4, // Provides observability of the D- Pulldown +}; // USB OTG Control register #define USB0_CONTROL REG_8(0x40072108) -#define CONTROL_DPPULLUPNONOTG 4 // DP Pullup in non-OTG device mode state +enum { + CONTROL_DPPULLUPNONOTG = 4, // DP Pullup in non-OTG device mode state +}; // USB Transceiver Control Register 0 #define USB0_USBTRC0 REG_8(0x4007210C) -#define USBTRC0_USBRESET 7 // USB Reset -#define USBTRC0_USBRESMEN 5 // Asynchronous Resume Interrupt Enable -#define USBTRC0_SYNC_DET 1 // Synchronous USB Interrupt Detect -#define USBTRC0_USB_RESUME_INT 0 // USB Asynchronous Interrupt +enum { + USBTRC0_USBRESET = 7, // USB Reset + USBTRC0_USBRESMEN = 5, // Asynchronous Resume Interrupt Enable + USBTRC0_SYNC_DET = 1, // Synchronous USB Interrupt Detect + USBTRC0_USB_RESUME_INT = 0, // USB Asynchronous Interrupt +}; // Frame Adjust Register #define USB0_USBFRMADJUST REG_8(0x40072114) -#define USBFRMADJUST_ADJ 0 -#define USBFRMADJUST_ADJ_M REG_8_M(USBFRMADJUST_ADJ, 8) +enum { + USBFRMADJUST_ADJ = 0, + USBFRMADJUST_ADJ_M = REG_8_M(USBFRMADJUST_ADJ, 8), +}; // TODO: Move elsewhere __attribute__ ((packed)) @@ -204,30 +259,31 @@ struct usb0_bd { uint32_t desc; void *addr; }; -//#define USB0_BD(desc, addr) (struct usb0_bd){(desc), (addr)} #define USB0_BD_INIT(size, data01) ((size) << BD_BC | BV(BD_OWN) | \ ((data01) & 1) << BD_DATA01 | BV(BD_DTS)) -#define BD_BC 16 // Byte Count -#define BD_BC_M REG_32_M(BD_BC, 10) -#define BD_OWN 7 -#define BD_DATA01 6 -#define BD_KEEP 5 -#define BD_NINC 4 -#define BD_DTS 3 -#define BD_BDT_STALL 2 -#define BD_TOK_PID 2 -#define BD_TOK_PID_M REG_32_M(BD_TOK_PID, 4) - -#define BD_TOK_PID_OUT 0x1 -#define BD_TOK_PID_IN 0x9 -#define BD_TOK_PID_SETUP 0xd - -#define BD_TOK_PID_DATA0 0x3 -#define BD_TOK_PID_DATA1 0xb -#define BD_TOK_PID_ACK 0x2 -#define BD_TOK_PID_STALL 0xe -#define BD_TOK_PID_NAK 0xa -#define BD_TOK_PID_TIMEOUT 0x0 -#define BD_TOK_PID_ERROR 0xf +enum { + BD_BC = 16, // Byte Count + BD_BC_M = REG_32_M(BD_BC, 10), + BD_OWN = 7, + BD_DATA01 = 6, + BD_KEEP = 5, + BD_NINC = 4, + BD_DTS = 3, + BD_BDT_STALL = 2, + BD_TOK_PID = 2, + BD_TOK_PID_M = REG_32_M(BD_TOK_PID, 4), + + BD_TOK_PID_OUT = 0x1, + BD_TOK_PID_IN = 0x9, + BD_TOK_PID_SETUP = 0xd, + + BD_TOK_PID_DATA0 = 0x3, + BD_TOK_PID_DATA1 = 0xb, + BD_TOK_PID_ACK = 0x2, + BD_TOK_PID_STALL = 0xe, + BD_TOK_PID_NAK = 0xa, + BD_TOK_PID_TIMEOUT = 0x0, + BD_TOK_PID_ERROR = 0xf, +}; #endif /* MK20DX256_REG_USBOTG_H */ |