aboutsummaryrefslogtreecommitdiffstats
path: root/src
Commit message (Collapse)AuthorAgeFilesLines
* Kconfig: Support Enable/Disable lis2dw on chips with small flash sizebigtreetech2023-08-212-1/+9
| | | | Signed-off-by: Alan.Ma from BigTreeTech tech@biqu3d.com
* lis2dw12: Add support for lis2dw12 accelerometerbigtreetech2023-08-212-1/+222
| | | | | | | | lis2dw12 is an accelerometer from STMicroelectronics(https://www.st.com/resource/en/datasheet/lis2dw12.pdf) With better performance than the ADXL345 according to the datasheet. Signed-off-by: XM.Zhou from BigTreeTech zhouxm@biqu3d.com Signed-off-by: Alan.Ma from BigTreeTech tech@biqu3d.com
* hc32f460: Add app address 0x10000Falk Höppner2023-08-131-6/+9
| | | | | | Required for the Anycubic Kobra 2. Signed-off-by: Falk Höppner <falk@hoppner.se>
* atsamd: Add support for SAMD21J18 (Minitronics v2)Bart Meijer2023-07-051-2/+6
| | | | | | Adds a menu entry in menuconfig, allowing you to select the SAMD21J18 as mcu. Signed-off-by: Bart Meijer <brupje@gmail.com>
* hc32f460: Disable JTAG/SWD on pins so they can be used for GPIO/serialBoris-Chengbiao Zhou2023-06-201-0/+6
| | | | | | | | | | | | | This change is required to sucessfully use PA13/PA14 for UART. Otherwise they function as SWDIO/SWCLK. Relevant excerpt from the reference manual (translated): The initial state of PA13, PA14, PA15, PB3, and PB4 ports is that the JTAG/SWD function is valid after reset. When configuring FSEL[5:0] to select the function, you need to write 0 to the corresponding bit of the register PSPCR to invalidate the JTAG/SWD function. Signed-off-by: Boris-Chengbiao Zhou <bobo1239@web.de>
* hc32f460: Use correct USART for PH2/PB10 pinsBoris-Chengbiao Zhou2023-06-201-9/+28
| | | | | | | | | | | This fixes serial communication when selecting the PH2/PB10 pins. The chip datasheet (not reference manual) assigns pins to one of two communication function groups (`Func_Grp1/2`). Pins in group 1 have access to USART1/2 while group 2 has access to USART3/4. PH2/PB10 belong to group 2 so we now correctly use USART3 for them. Signed-off-by: Boris-Chengbiao Zhou <bobo1239@web.de>
* atsamd: Fixes for samc21 and compiler optimizations (#6198)Luke V2023-06-162-4/+26
| | | Signed-off-by: Luke Vuksta <wulfstawulfsta@gmail.com>
* Kconfig: Support selecting optional features on chips with small flash sizeKevin O'Connor2023-06-0815-36/+70
| | | | | | | | | | | | | Add a new HAVE_LIMITED_CODE_SIZE symbol that enables a menu to select optional features. This symbol is enabled on chips with small build sizes. Replace the HAVE_GPIO_BITBANGING with four new symbols: WANT_GPIO_BITBANGING, WANT_DISPLAYS, WANT_SENSORS, WANT_SOFTWARE_SPI, and WANT_SOFTWARE_I2C. This allows users a little more flexibility when selecting features they need. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* i2c_software: Implementation of software i2c (#6141)BIGTREETECH2023-06-076-10/+246
| | | Signed-off-by: Alan.Ma from BigTreeTech <tech@biqu3d.com>
* hc32f460: update for HC32F460 - clock, flash add, serial (#6235)Steve Gotthardt2023-06-062-9/+44
| | | | | | | | | Add clock speed selection Add Flash App Address selection Add alternate serial connection and remove company specific names Signed-off-by: Steven Gotthardt <gotthardt@gmail.com>
* Kconfig: Change default CANbus frequency to 1000000Kevin O'Connor2023-05-301-1/+1
| | | | | | | | Change the default CANbus frequency from 500000 to 1000000. A higher frequency allows for greater data transfer rates, lower latency of messages, and should overall be more robust. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: add PB5/PB6 as CAN pins - required for BTT U2C v2.xStefan Dej2023-05-202-2/+6
| | | | Signed-off-by: Stefan Dej <meteyou@gmail.com>
* stm32f7: add support for stm32f7 and remram boardFrederic Morin2023-05-0710-11/+217
| | | | Signed-off-by: Frederic Morin <frederic.morin.8@gmail.com>
* atsamd: Add support for SAMC21Wulfsta2023-05-0113-31/+311
| | | | Signed-off-by: Luke Vuksta <wulfstawulfsta@gmail.com>
* rp2040: Handle USB resetsKevin O'Connor2023-04-251-4/+9
| | | | | | | | | | | | On a USB bus reset the controller address needs to be reset to zero. Otherwise, the device becomes unresponsive after a USB reset and will remain unresponsive until a power cycle. This often shows up in the Linux system logs as "device descriptor read/64, error -32" messages. Make sure USB_INTE_BUS_RESET_BITS is enabled and clear the USB address on a bus reset. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* usb_canbus: Rework USB message transmit prioritizationKevin O'Connor2023-04-241-38/+38
| | | | | | | | | | | There is no need to heavily prioritize the sending of canbus packets over USB. A single check to flush the incoming canbus packets is sufficient. Also, be sure to wake up canserial_notify_tx() even if canhw_send() blocks. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* usb_canbus: No need to check if canserial can accept a packetKevin O'Connor2023-04-243-13/+8
| | | | | | | | The canserial code already advertizes a receive window, so the host should never flood the canserial code. Remove the extra scheduling checks to simplify the usb_canbus code. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* usb_canbus: Minor code reformatting of drain_hw_queue()Kevin O'Connor2023-04-241-10/+10
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* usb_canbus: Increase rx canbus packet buffer to 32Kevin O'Connor2023-04-241-1/+1
| | | | | | | | A buffer of only 8 canbus packets is only 64 bytes of data, which could be exceeded if the usb-to-canbus mcu gets busy doing other work. Increase the buffer to 32 packets. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Fix usbotg irq wakeup notificationKevin O'Connor2023-04-241-4/+4
| | | | | | | | The DAINTMSK prevents irqs but does not prevent the status reporting in the GINTSTS and DAINT fields. Thus, the mask bits should be checked prior to sending a wakeup notification. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* sensor_mpu9250: Fix or improve reliability (#6170)Dr. Matthew Swabey2023-04-191-48/+54
| | | | | | | | | | | | | | | | | | | Fixes common MPU-9250 accelerometer issues for RPi Linux MCU and improves reliability on all other architectures by adjusting the MPU-* reading algorithm to only read whole Klipper messages' worth of data from MPU-* and eliminating many unnecessary checks of the MPU FIFO fill-level that consumed bus bandwidth needed for data transfer. Fixes intermittent "Lost communication with MCU 'rpi'" due to "Timer too close" and transposed / corrupted data due to FIFO overrun/data loss when using MPU-* accelerometers. In addition FIFO overrun checks are performed by testing the MPU interrupt flag vs. inferring from the FIFO fill level. Stress tested for 13hrs with two MPU-6500 attached to one I2C bus on RPi and one on a PR2040 Stress tested for 23hrs with two MPU-6500 attached to one I2C bus on RPi and one on a ATmega328P (Seeduino Nano) Signed-off-by: Matthew Swabey <matthew@swabey.org>
* stm32: Support for USART5 on STM32G0B1 (#6105)Florin Popescu2023-04-193-0/+23
| | | | | | | Support for USART5 on PD2,3 Add exception on RCC bits for USART5&6 Signed-off-by: Florin Popescu <florinsgpopescu@gmail.com>
* scripts: Fix flash linux when OUT argument provided (#6133)visilya2023-04-071-1/+1
| | | Signed-off-by: Ilya Vislotsky <write2ilya@gmail.com>
* stm32: Improve ifdef indent in hard_pwm.cKevin O'Connor2023-04-071-4/+4
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Prefer "MACH_STM32F1" test over "MACH_STM32F103 || MACH_N32G45x"Kevin O'Connor2023-04-072-2/+2
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Add support for Nation N32G45x mcus (#6116)Alexey2023-04-075-10/+215
| | | | | N32G452/G455 are mostly compatible with STM32F103 but have M4 core and different ADC. Signed-off-by: Alexey Golyshin <stas2z@gmail.com>
* linux: Lock Memory and Increase Priority (#6131)Dr. Matthew Swabey2023-03-271-2/+9
| | | | | | | | | | | | | | | | | Realtime programming best practice is to lock realtime code memory to prevent paging which will lead to unbounded latencies. The Linux MCU process has well bounded memory and small RAM footprint so locking the entire process' RAM has no downsides and will improve behavior when the system comes under memory pressure. (See bootlin training and Linux Foundation documentation linked below.) RT process priority ranges from 0-99 (although POSIX only requires 32), boost MCU process priority to half the max/2 to improve robustness when the system comes under pressure from other RT Kernel or user processes. Reference links: bootlin: https://bootlin.com/doc/training/preempt-rt/preempt-rt-slides.pdf Linux Foundation: https://wiki.linuxfoundation.org/realtime/documentation/howto/applications/application_base#howto_build_a_simple_rt_application Signed-off-by: Matthew Swabey <matthew@swabey.org>
* stm32: Enable I2C on stm32h7 (#6130)BIGTREETECH2023-03-273-1/+13
| | | Signed-off-by: Alan.Ma from BigTreeTech <tech@biqu3d.com>
* avr: Allow I2C bus speed to be set by Klipper (#6111)Dr. Matthew Swabey2023-03-211-20/+16
| | | | | Allow I2C bus speed to be set by appropriate Klipper commands. Signed-off-by: Matthew Swabey <matthew@swabey.org>
* linux: Fast Linux MCU i2c_read() with I2C_RDRW (#6101)Dr. Matthew Swabey2023-03-142-8/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | Reading an I2C device from the Linux MCU used a separate write(2) to select the target register & read(2) to get the value(s). This implementation uses ioctl(file, I2C_RDWR, ...) to skip a large bus idle period and extra process sleep by combining them like the stm32. I2C_RDRW requires I2C_FUNC_I2C flag in the I2C driver. I2C_FUNC_I2C is defined in: BCM2835: Pi 1 Models A, A+, B, B+, the Raspberry Pi Zero, the Raspberry Pi Zero W, and the Raspberry Pi Compute Module 1 BCM2836: Pi 2 Model B Identical to BCM2835 except Cortex BCM2837: Pi 3 Model B, later models of the Raspberry Pi 2 Model B, and the Raspberry Pi Compute Module 3 BCM2837B0: Pi 3 Models A+, B+, and the Raspberry Pi Compute Module 3+ BCM2711: Pi 4 Model B, the Raspberry Pi 400, and the Raspberry Pi Compute Module 4 RK3xxx: Rockchips SoCs NanoPi, RockPi, Tinker, etc. SUNXI: H2, H3, etc. Orange Pi AMLOGIC: S905x, Banana Pi, Odroid, etc. TEGRA: NVidia Jetson etc. MediaTek: Several SBCs in other ranges Signed-off-by: Matthew Swabey <matthew@swabey.org>
* stm32h7: Restore the RCC set in the bootloader to the default value (#6092)BIGTREETECH2023-03-061-0/+6
| | | Signed-off-by: Alan.Ma from BigTreeTech <tech@biqu3d.com>
* ar100: Support for ar100 (#6054)Elias Bakken2023-02-2014-0/+706
| | | | | Add files to support AR100 Signed-off-by: Elias Bakken <elias@iagent.no>
* stm32: Add sdio supportH. Gregor Molter2023-02-2011-5/+634
| | | | | | | | Adds sdio support for the stm32f4 to allow for SD card flash updates without power cycling some boards, e.g. BTT Octopus Pro. Signed-off-by: H. Gregor Molter <gregor.molter@secretlab.de> Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* hc32f460: Add support for hc32f460 micro-controllersSteven Gotthardt2023-02-1311-0/+928
| | | | Signed-off-by: Steven Gotthardt <gotthardt@gmail.com>
* stm32: add PB12/PB13 FDCAN2 support STM32G0B1bigtreetech2023-02-032-3/+8
| | | | | Signed-off-by: Alan.Ma from BigTreeTech tech@biqu3d.com Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Fix CAN2 handling in can.cKevin O'Connor2023-01-171-13/+26
| | | | | | | Using the CAN2 interface still requires that CAN1 be enabled, and the filtering hardware is always on the CAN1 hardware block. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Increase sample time in stm32h7_adc.cKevin O'Connor2023-01-171-7/+10
| | | | | | | | The existing sample times are not long enough to reliably sample the internal temperature sensor. Longer sample times should also improve results with temperature sensors that have a higher inductance. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Don't set boost nor linear calibration on stm32h723 adc3Kevin O'Connor2023-01-171-14/+14
| | | | | | Only adc1 and adc2 have these CR register bits on stm32h723. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Reduce read-modify-write of CR in stm32h7_adc.c initKevin O'Connor2023-01-171-21/+12
| | | | | | | | | | Prefer explicitly setting the CR hardware register to defined values during initialization. Also, prefer "#if CONFIG_MACH_STM32H7" over bit definitions to make it clear that the code applies only on stm32h7. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Don't use read-modify-write on ISR register in stm32h7_adc.cKevin O'Connor2023-01-171-3/+2
| | | | | | Bits are cleared in the ISR register by writing 1, not by masking. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: ADC timing rework and fixes in stm32h7_adc.cKevin O'Connor2023-01-171-34/+23
| | | | | | | | | | | | The stm32l412 doesn't have a PLLSAI1 clock and therefore the CKMODE should not be set to zero. The stm32h7 chips run the adc at 25mhz, so BOOST should be set to 0b10. Improve timing comments. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Move clock line mapping from stm32h7_adc.c to lookup_clock_line()Kevin O'Connor2023-01-174-17/+14
| | | | | | | Use the common lookup_clock_line() code to lookup the adc clock lines. This also enables resets on the adc1/adc2 hardware block. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Simplify setting of adc_common fields in stm32h7_adc.cKevin O'Connor2023-01-171-12/+9
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Use a consistent bank size of 20 across all chips in stm32h7_adc.cKevin O'Connor2023-01-171-3/+3
| | | | | | | Add a pad entry to adc_pins[] on stm32l4 so that it matches the other chips. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Simplify setting of 12bit mode on stm32h7 in stm32h7_adc.cKevin O'Connor2023-01-171-14/+5
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: No need to use hardware oversampling in stm32h7_adc.cKevin O'Connor2023-01-171-25/+0
| | | | | | | | | Not all chips implement hardware oversampling. The software already implements oversampling, and additional hardware oversampling is unlikely to improve results. Remove the hardware oversampling to simplify the code. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Simplify CFGR register setup in stm32h7_adc.cKevin O'Connor2023-01-171-10/+2
| | | | | | | | On all chips, the JQDIS bit is set and the CONT, RES, ALIGN bits are clear after a reset. There is no need to program the OVRMOD bit. Use the same logic across chips to help unify the adc implementation. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: No need for LDORDY check in stm32h7_adc.cKevin O'Connor2023-01-171-17/+4
| | | | | | | | Not all chips have the LDORDY flag, while all chips will stabilize in 10us. There is no need for two different implementations as it is safe to wait 20us on all chips. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* linux: add -I attribute for user defined socket pathsStefan Dej2023-01-171-3/+7
| | | | Signed-off-by: Stefan Dej <meteyou@gmail.com>
* stm32: Reindent ifdefs in stm32f0_i2c.cKevin O'Connor2023-01-031-56/+55
| | | | | | A whitespace and comment change only - no functional changes. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
generated by cgit v1.2.3-70-g09d2 (git 2.50.1) at 2025-09-02 13:49:12 +0000