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| author | Kevin O'Connor <kevin@koconnor.net> | 2022-12-13 10:44:35 -0500 |
|---|---|---|
| committer | Kevin O'Connor <kevin@koconnor.net> | 2023-01-17 18:22:21 -0500 |
| commit | efdc29f5892e2da869ae1c0038f8b3cc8dc23d5c (patch) | |
| tree | bd98d59a0dab5010b1099091cec3306627f71e55 /src | |
| parent | 9b7dcfa3337b4874c92e9009b323f828a06ff5a4 (diff) | |
| download | kutter-efdc29f5892e2da869ae1c0038f8b3cc8dc23d5c.tar.gz kutter-efdc29f5892e2da869ae1c0038f8b3cc8dc23d5c.tar.xz kutter-efdc29f5892e2da869ae1c0038f8b3cc8dc23d5c.zip | |
stm32: Simplify CFGR register setup in stm32h7_adc.c
On all chips, the JQDIS bit is set and the CONT, RES, ALIGN bits are
clear after a reset. There is no need to program the OVRMOD bit. Use
the same logic across chips to help unify the adc implementation.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src')
| -rw-r--r-- | src/stm32/stm32h7_adc.c | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/src/stm32/stm32h7_adc.c b/src/stm32/stm32h7_adc.c index 1d15cc85..61e0c764 100644 --- a/src/stm32/stm32h7_adc.c +++ b/src/stm32/stm32h7_adc.c @@ -296,15 +296,9 @@ gpio_adc_setup(uint32_t pin) | (aticks << 9) | (aticks << 12) | (aticks << 15) | (aticks << 18) | (aticks << 21) | (aticks << 24) | (aticks << 27)); - // Disable Continuous Mode - MODIFY_REG(adc->CFGR, ADC_CFGR_CONT_Msk, 0); + // Set to 12 bit - if (is_stm32h723_adc3) { -#ifdef ADC3_CFGR_RES - MODIFY_REG(adc->CFGR, ADC3_CFGR_RES_Msk, 0 << ADC3_CFGR_RES_Pos); - MODIFY_REG(adc->CFGR, ADC3_CFGR_ALIGN_Msk, 0<<ADC3_CFGR_ALIGN_Pos); -#endif - } else { + if (!is_stm32h723_adc3) { MODIFY_REG(adc->CFGR, ADC_CFGR_RES_Msk, ADC_RES<<ADC_CFGR_RES_Pos); } #if CONFIG_MACH_STM32H7 @@ -321,8 +315,6 @@ gpio_adc_setup(uint32_t pin) } MODIFY_REG(adc->CFGR2, ADC_CFGR2_OVSS_Msk, OVERSAMPLES_EXPONENT << ADC_CFGR2_OVSS_Pos); -#else // stm32l4 - adc->CFGR |= ADC_CFGR_JQDIS | ADC_CFGR_OVRMOD; #endif } |