cleanup

1 files changed, 136 insertions, 92 deletions

diff --git a/reg/uart.h b/reg/uart.h
index 3b2ee12..0ec2105 100644
--- a/reg/uart.h
+++ b/reg/uart.h
@@ -26,161 +26,205 @@
 
 // UART Baud Rate Registers: High
 #define UART_BDH(base) REG_8((base) + 0x0)
-#define BDH_LBKDIE 7 // LIN Break Detect Interrupt Enable
-#define BDH_RXEDGIE 6 // RxD Input Active Edge Interrupt Enable
-#define BDH_SBR 0 // UART Baud Rate Bits
-#define BDH_SBR_M REG_8_M(BDH_SBR, 4)
+enum {
+	BDH_LBKDIE = 7, // LIN Break Detect Interrupt Enable
+	BDH_RXEDGIE = 6, // RxD Input Active Edge Interrupt Enable
+	BDH_SBR = 0, // UART Baud Rate Bits
+	BDH_SBR_M = REG_8_M(BDH_SBR, 4),
+};
 
 // UART Baud Rate Registers: Low
 #define UART_BDL(base) REG_8((base) + 0x1)
-#define BDL_SBR 0 // UART Baud Rate Bits
-#define BDL_SBR_M REG_8_M(BDL_SBR, 8)
+enum {
+	BDL_SBR = 0, // UART Baud Rate Bits
+	BDL_SBR_M = REG_8_M(BDL_SBR, 8),
+};
 
 // UART Control Register 1
 #define UART_C1(base) REG_8((base) + 0x2)
-#define C1_LOOPS 7 // Loop Mode Select
-#define C1_UARTSWAI 6 // UART Stops in Wait Mode
-#define C1_RSRC 5 // Receiver Source Select
-#define C1_M 4 // 9-bit or 8-bit Mode Select
-#define C1_WAKE 3 // Receiver Wakeup Method Select
-#define C1_ILT 2 // Idle Line Type Select
-#define C1_PE 1 // Parity Enable
-#define C1_PT 0 // Parity Type
+enum {
+	C1_LOOPS = 7, // Loop Mode Select
+	C1_UARTSWAI = 6, // UART Stops in Wait Mode
+	C1_RSRC = 5, // Receiver Source Select
+	C1_M = 4, // 9-bit or 8-bit Mode Select
+	C1_WAKE = 3, // Receiver Wakeup Method Select
+	C1_ILT = 2, // Idle Line Type Select
+	C1_PE = 1, // Parity Enable
+	C1_PT = 0, // Parity Type
+};
 
 // UART Control Register 2
 #define UART_C2(base) REG_8((base) + 0x3)
-#define C2_TIE 7 // Transmitter Interrupt or DMA Transfer Enable.
-#define C2_TCIE 6 // Transmission Complete Interrupt Enable
-#define C2_RIE 5 // Receiver Full Interrupt or DMA Transfer Enable
-#define C2_ILIE 4 // Idle Line Interrupt Enable
-#define C2_TE 3 // Transmitter Enable
-#define C2_RE 2 // Receiver Enable
-#define C2_RWU 1 // Receiver Wakeup Control
-#define C2_SBK 0 // Send Break
+enum {
+	C2_TIE = 7, // Transmitter Interrupt or DMA Transfer Enable.
+	C2_TCIE = 6, // Transmission Complete Interrupt Enable
+	C2_RIE = 5, // Receiver Full Interrupt or DMA Transfer Enable
+	C2_ILIE = 4, // Idle Line Interrupt Enable
+	C2_TE = 3, // Transmitter Enable
+	C2_RE = 2, // Receiver Enable
+	C2_RWU = 1, // Receiver Wakeup Control
+	C2_SBK = 0, // Send Break
+};
 
 // UART Status Register 1
 #define UART_S1(base) REG_8((base) + 0x4)
-#define S1_TDRE 7 // Transmit Data Register Empty Flag
-#define S1_TC 6 // Transmit Complete Flag
-#define S1_RDRF 5 // Receive Data Register Full Flag
-#define S1_IDLE 4 // Idle Line Flag
-#define S1_OR 3 // Receiver Overrun Flag
-#define S1_NF 2 // Noise Flag
-#define S1_FE 1 // Framing Error Flag
-#define S1_PF 0 // Parity Error Flag
+enum {
+	S1_TDRE = 7, // Transmit Data Register Empty Flag
+	S1_TC = 6, // Transmit Complete Flag
+	S1_RDRF = 5, // Receive Data Register Full Flag
+	S1_IDLE = 4, // Idle Line Flag
+	S1_OR = 3, // Receiver Overrun Flag
+	S1_NF = 2, // Noise Flag
+	S1_FE = 1, // Framing Error Flag
+	S1_PF = 0, // Parity Error Flag
+};
 
 // UART Status Register 2
 #define UART_S2(base) REG_8((base) + 0x5)
-#define S2_LBKDIF 7 // LIN Break Detect Interrupt Flag
-#define S2_RXEDGIF 6 // RxD Pin Active Edge Interrupt Flag
-#define S2_MSBF 5 // Most Significant Bit First
-#define S2_RXINV 4 // Receive Data Inversion
-#define S2_RWUID 3 // Receive Wakeup Idle Detect
-#define S2_BRK13 2 // Break Transmit Character Length
-#define S2_LBKDE 1 // LIN Break Detection Enable
-#define S2_RAF 0 // Receiver Active Flag
+enum {
+	S2_LBKDIF = 7, // LIN Break Detect Interrupt Flag
+	S2_RXEDGIF = 6, // RxD Pin Active Edge Interrupt Flag
+	S2_MSBF = 5, // Most Significant Bit First
+	S2_RXINV = 4, // Receive Data Inversion
+	S2_RWUID = 3, // Receive Wakeup Idle Detect
+	S2_BRK13 = 2, // Break Transmit Character Length
+	S2_LBKDE = 1, // LIN Break Detection Enable
+	S2_RAF = 0, // Receiver Active Flag
+};
 
 // UART Control Register 3
 #define UART_C3(base) REG_8((base) + 0x6)
-#define C3_R8 7 // Received Bit 8
-#define C3_T8 6 // Transmit Bit 8
-#define C3_TXDIR 5 // Transmitter Pin Data Direction in Single-Wire mode
-#define C3_TXINV 4 // Transmit Data Inversion.
-#define C3_ORIE 3 // Overrun Error Interrupt Enable
-#define C3_NEIE 2 // Noise Error Interrupt Enable
-#define C3_FEIE 1 // Framing Error Interrupt Enable
-#define C3_PEIE 0 // Parity Error Interrupt Enable
+enum {
+	C3_R8 = 7, // Received Bit 8
+	C3_T8 = 6, // Transmit Bit 8
+	C3_TXDIR = 5, // Transmitter Pin Data Direction in Single-Wire mode
+	C3_TXINV = 4, // Transmit Data Inversion.
+	C3_ORIE = 3, // Overrun Error Interrupt Enable
+	C3_NEIE = 2, // Noise Error Interrupt Enable
+	C3_FEIE = 1, // Framing Error Interrupt Enable
+	C3_PEIE = 0, // Parity Error Interrupt Enable
+};
 
 // UART Data Register
 #define UART_D(base) REG_8((base) + 0x7)
-#define D_RT 0
-#define D_RT_M REG_8_M(D_RT, 8)
+enum {
+	D_RT = 0,
+	D_RT_M = REG_8_M(D_RT, 8),
+};
 
 // UART Match Address Registers 1
 #define UART_MA1(base) REG_8((base) + 0x8)
-#define MA1_MA 0 // Match Address
-#define MA1_MA_M REG_8_M(MA1_M, 8)
+enum {
+	MA1_MA = 0, // Match Address
+	MA1_MA_M = REG_8_M(MA1_M, 8),
+};
 
 // UART Match Address Registers 2
 #define UART_MA2(base) REG_8((base) + 0x9)
-#define MA2_MA 0 // Match Address
-#define MA2_MA_M REG_8_M(MA2_M, 8)
+enum {
+	MA2_MA = 0, // Match Address
+	MA2_MA_M = REG_8_M(MA2_M, 8),
+};
 
 // UART Control Register 4
 #define UART_C4(base) REG_8((base) + 0xA)
-#define C4_MAEN1 7 // Match Address Mode Enable 1
-#define C4_MAEN2 6 // Match Address Mode Enable 2
-#define C4_M10 5 // 10-bit Mode Select
-#define C4_BRFA 0 // Baud Rate Fine Adjust
-#define C4_BRFA_M REG_8_M(C4_BRFA, 5)
+enum {
+	C4_MAEN1 = 7, // Match Address Mode Enable 1
+	C4_MAEN2 = 6, // Match Address Mode Enable 2
+	C4_M10 = 5, // 10-bit Mode Select
+	C4_BRFA = 0, // Baud Rate Fine Adjust
+	C4_BRFA_M = REG_8_M(C4_BRFA, 5),
+};
 
 // UART Control Register 5
 #define UART_C5(base) REG_8((base) + 0xB)
-#define C5_TDMAS 7 // Transmitter DMA Select
-#define C5_RDMAS 5 // Receiver Full DMA Select
+enum {
+	C5_TDMAS = 7, // Transmitter DMA Select
+	C5_RDMAS = 5, // Receiver Full DMA Select
+};
 
 // UART Extended Data Register
 #define UART_ED(base) REG_8((base) + 0xC)
-#define ED_NOISY 7 // Dataword contained in D and C3[R8] received with noise.
-#define ED_PARITYE 6 // Dataword contained in D and C3[R8] received with a parity error.
+enum {
+	ED_NOISY = 7, // Dataword contained in D and C3[R8] received with noise.
+	ED_PARITYE = 6, // Dataword contained in D and C3[R8] received with a parity error.
+};
 
 // UART Modem Register
 #define UART_MODEM(base) REG_8((base) + 0xD)
-#define MODEM_RXRTSE 3 // Receiver request-to-send enable
-#define MODEM_TXRTSPOL 2 // Transmitter request-to-send polarity
-#define MODEM_TXRTSE 1 // Transmitter request-to-send enable
-#define MODEM_TXCTSE 0 // Transmitter clear-to-send enable
+enum {
+	MODEM_RXRTSE = 3, // Receiver request-to-send enable
+	MODEM_TXRTSPOL = 2, // Transmitter request-to-send polarity
+	MODEM_TXRTSE = 1, // Transmitter request-to-send enable
+	MODEM_TXCTSE = 0, // Transmitter clear-to-send enable
+};
 
 // UART Infrared Register
 #define UART_IR(base) REG_8((base) + 0xE)
-#define IR_IREN 2 // Infrared enable
-#define IR_TNP 0 // Transmitter narrow pulse
-#define IR_TNP_M REG_8_M(IR_TNP, 2)
+enum {
+	IR_IREN = 2, // Infrared enable
+	IR_TNP = 0, // Transmitter narrow pulse
+	IR_TNP_M = REG_8_M(IR_TNP, 2),
+};
 
 // UART FIFO Parameters
 #define UART_PFIFO(base) REG_8((base) + 0x10)
-#define PFIFO_TXFE 7 // Transmit FIFO Enable
-#define PFIFO_TXFIFOSIZE 4 // Transmit FIFO, Buffer Depth
-#define PFIFO_TXFIFOSIZE_M REG_8_M(PFIFO_TXFIFOSIZE, 3)
-#define PFIFO_RXFE 3 // Receive FIFO Enable
-#define PFIFO_RXFIFOSIZE 0 // Receive FIFO, Buffer Depth
-#define PFIFO_RXFIFOSIZE_M REG_8_M(PFIFO_RXFIFOSIZE, 3)
+enum {
+	PFIFO_TXFE = 7, // Transmit FIFO Enable
+	PFIFO_TXFIFOSIZE = 4, // Transmit FIFO, Buffer Depth
+	PFIFO_TXFIFOSIZE_M = REG_8_M(PFIFO_TXFIFOSIZE, 3),
+	PFIFO_RXFE = 3, // Receive FIFO Enable
+	PFIFO_RXFIFOSIZE = 0, // Receive FIFO, Buffer Depth
+	PFIFO_RXFIFOSIZE_M = REG_8_M(PFIFO_RXFIFOSIZE, 3),
+};
 
 // UART FIFO Control Register
 #define UART_CFIFO(base) REG_8((base) + 0x11)
-#define CFIFO_TXFLUSH 7 // Transmit FIFO/Buffer Flush
-#define CFIFO_RXFLUSH 6 // Receive FIFO/Buffer Flush
-#define CFIFO_RXOFE 2 // Receive FIFO Overflow Interrupt Enable
-#define CFIFO_TXOFE 1 // Transmit FIFO Overflow Interrupt Enable
-#define CFIFO_RXUFE 0 // Receive FIFO Underflow Interrupt Enable
+enum {
+	CFIFO_TXFLUSH = 7, // Transmit FIFO/Buffer Flush
+	CFIFO_RXFLUSH = 6, // Receive FIFO/Buffer Flush
+	CFIFO_RXOFE = 2, // Receive FIFO Overflow Interrupt Enable
+	CFIFO_TXOFE = 1, // Transmit FIFO Overflow Interrupt Enable
+	CFIFO_RXUFE = 0, // Receive FIFO Underflow Interrupt Enable
+};
 
 // UART FIFO Status Register
 #define UART_SFIFO(base) REG_8((base) + 0x12)
-#define SFIFO_TXEMPT 7 // Transmit Buffer/FIFO Empty
-#define SFIFO_RXEMPT 6 // Receive Buffer/FIFO Empty
-#define SFIFO_RXOF 2 // Receiver Buffer Overflow Flag
-#define SFIFO_TXOF 1 // Transmitter Buffer Overflow Flag
-#define SFIFO_RXUF 0 // Receiver Buffer Underflow Flag
+enum {
+	SFIFO_TXEMPT = 7, // Transmit Buffer/FIFO Empty
+	SFIFO_RXEMPT = 6, // Receive Buffer/FIFO Empty
+	SFIFO_RXOF = 2, // Receiver Buffer Overflow Flag
+	SFIFO_TXOF = 1, // Transmitter Buffer Overflow Flag
+	SFIFO_RXUF = 0, // Receiver Buffer Underflow Flag
+};
 
 // UART FIFO Transmit Watermark
 #define UART_TWFIFO(base) REG_8((base) + 0x13)
-#define TWFIFO_TXWATER 0 // Transmit Watermark
-#define TWFIFO_TXWATER_M REG_8_M(TWFIFO_TXWATER, 8)
+enum {
+	TWFIFO_TXWATER = 0, // Transmit Watermark
+	TWFIFO_TXWATER_M = REG_8_M(TWFIFO_TXWATER, 8),
+};
 
 // UART FIFO Transmit Count
 #define UART_TCFIFO(base) REG_8((base) + 0x14)
-#define TCFIFO_TXCOUNT 0 // Transmit Counter
-#define TCFIFO_TXCOUNT_M REG_8_M(TCFIFO_TXCOUNT, 8)
+enum {
+	TCFIFO_TXCOUNT = 0, // Transmit Counter
+	TCFIFO_TXCOUNT_M = REG_8_M(TCFIFO_TXCOUNT, 8),
+};
 
 // UART FIFO Receive Watermark
 #define UART_RWFIFO(base) REG_8((base) + 0x15)
-#define RWFIFO_RXWATER 0 // Receive Watermark
-#define RWFIFO_RXWATER_M REG_8_M(RWFIFO_RXWATER, 8)
+enum {
+	RWFIFO_RXWATER = 0, // Receive Watermark
+	RWFIFO_RXWATER_M = REG_8_M(RWFIFO_RXWATER, 8),
+};
 
 // UART FIFO Receive Count
 #define UART_RCFIFO(base) REG_8((base) + 0x16)
-#define RCFIFO_RXCOUNT 0
-#define RCFIFO_RXCOUNT_M REG_8_M(RCFIFO_RXCOUNT, 8)
+enum {
+	RCFIFO_RXCOUNT = 0,
+	RCFIFO_RXCOUNT_M = REG_8_M(RCFIFO_RXCOUNT, 8),
+};
 
 // UART 0 Only