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| author | Tomasz Kramkowski <tk@the-tk.com> | 2017-05-19 21:29:39 +0100 |
|---|---|---|
| committer | Tomasz Kramkowski <tk@the-tk.com> | 2017-05-19 21:29:39 +0100 |
| commit | 07cce2f4e910bba661c4d60542a2333cae9cbfda (patch) | |
| tree | 78de04944006ede35241dc57e6ccd7a1ec997744 /reg/gpio.h | |
| parent | 4eab550b3b19345d271b4a93d34374a0dae867da (diff) | |
| download | mk20dx256-07cce2f4e910bba661c4d60542a2333cae9cbfda.tar.gz mk20dx256-07cce2f4e910bba661c4d60542a2333cae9cbfda.tar.xz mk20dx256-07cce2f4e910bba661c4d60542a2333cae9cbfda.zip | |
cleanup
Diffstat (limited to 'reg/gpio.h')
| -rw-r--r-- | reg/gpio.h | 90 |
1 files changed, 60 insertions, 30 deletions
@@ -3,39 +3,69 @@ #include <reg/regdefs.h> -#define GPIOA_PDOR REG_32(0x400FF000) /* Port Data Output Register */ -#define GPIOA_PSOR REG_32(0x400FF004) /* Port Set Output Register */ -#define GPIOA_PCOR REG_32(0x400FF008) /* Port Clear Output Register */ -#define GPIOA_PTOR REG_32(0x400FF00C) /* Port Toggle Output Register */ -#define GPIOA_PDIR REG_32(0x400FF010) /* Port Data Input Register */ -#define GPIOA_PDDR REG_32(0x400FF014) /* Port Data Direction Register */ +// Port Data Output Register +#define GPIOA_PDOR REG_32(0x400FF000) +// Port Set Output Register +#define GPIOA_PSOR REG_32(0x400FF004) +// Port Clear Output Register +#define GPIOA_PCOR REG_32(0x400FF008) +// Port Toggle Output Register +#define GPIOA_PTOR REG_32(0x400FF00C) +// Port Data Input Register +#define GPIOA_PDIR REG_32(0x400FF010) +// Port Data Direction Register +#define GPIOA_PDDR REG_32(0x400FF014) -#define GPIOB_PDOR REG_32(0x400FF040) /* Port Data Output Register */ -#define GPIOB_PSOR REG_32(0x400FF044) /* Port Set Output Register */ -#define GPIOB_PCOR REG_32(0x400FF048) /* Port Clear Output Register */ -#define GPIOB_PTOR REG_32(0x400FF04C) /* Port Toggle Output Register */ -#define GPIOB_PDIR REG_32(0x400FF050) /* Port Data Input Register */ -#define GPIOB_PDDR REG_32(0x400FF054) /* Port Data Direction Register */ +// Port Data Output Register +#define GPIOB_PDOR REG_32(0x400FF040) +// Port Set Output Register +#define GPIOB_PSOR REG_32(0x400FF044) +// Port Clear Output Register +#define GPIOB_PCOR REG_32(0x400FF048) +// Port Toggle Output Register +#define GPIOB_PTOR REG_32(0x400FF04C) +// Port Data Input Register +#define GPIOB_PDIR REG_32(0x400FF050) +// Port Data Direction Register +#define GPIOB_PDDR REG_32(0x400FF054) -#define GPIOC_PDOR REG_32(0x400FF080) /* Port Data Output Register */ -#define GPIOC_PSOR REG_32(0x400FF084) /* Port Set Output Register */ -#define GPIOC_PCOR REG_32(0x400FF088) /* Port Clear Output Register */ -#define GPIOC_PTOR REG_32(0x400FF08C) /* Port Toggle Output Register */ -#define GPIOC_PDIR REG_32(0x400FF090) /* Port Data Input Register */ -#define GPIOC_PDDR REG_32(0x400FF094) /* Port Data Direction Register */ +// Port Data Output Register +#define GPIOC_PDOR REG_32(0x400FF080) +// Port Set Output Register +#define GPIOC_PSOR REG_32(0x400FF084) +// Port Clear Output Register +#define GPIOC_PCOR REG_32(0x400FF088) +// Port Toggle Output Register +#define GPIOC_PTOR REG_32(0x400FF08C) +// Port Data Input Register +#define GPIOC_PDIR REG_32(0x400FF090) +// Port Data Direction Register +#define GPIOC_PDDR REG_32(0x400FF094) -#define GPIOD_PDOR REG_32(0x400FF0C0) /* Port Data Output Register */ -#define GPIOD_PSOR REG_32(0x400FF0C4) /* Port Set Output Register */ -#define GPIOD_PCOR REG_32(0x400FF0C8) /* Port Clear Output Register */ -#define GPIOD_PTOR REG_32(0x400FF0CC) /* Port Toggle Output Register */ -#define GPIOD_PDIR REG_32(0x400FF0D0) /* Port Data Input Register */ -#define GPIOD_PDDR REG_32(0x400FF0D4) /* Port Data Direction Register */ +// Port Data Output Register +#define GPIOD_PDOR REG_32(0x400FF0C0) +// Port Set Output Register +#define GPIOD_PSOR REG_32(0x400FF0C4) +// Port Clear Output Register +#define GPIOD_PCOR REG_32(0x400FF0C8) +// Port Toggle Output Register +#define GPIOD_PTOR REG_32(0x400FF0CC) +// Port Data Input Register +#define GPIOD_PDIR REG_32(0x400FF0D0) +// Port Data Direction Register +#define GPIOD_PDDR REG_32(0x400FF0D4) -#define GPIOE_PDOR REG_32(0x400FF100) /* Port Data Output Register */ -#define GPIOE_PSOR REG_32(0x400FF104) /* Port Set Output Register */ -#define GPIOE_PCOR REG_32(0x400FF108) /* Port Clear Output Register */ -#define GPIOE_PTOR REG_32(0x400FF10C) /* Port Toggle Output Register */ -#define GPIOE_PDIR REG_32(0x400FF110) /* Port Data Input Register */ -#define GPIOE_PDDR REG_32(0x400FF114) /* Port Data Direction Register */ +// Port Data Output Register +#define GPIOE_PDOR REG_32(0x400FF100) +// Port Set Output Register +#define GPIOE_PSOR REG_32(0x400FF104) +// Port Clear Output Register +#define GPIOE_PCOR REG_32(0x400FF108) +// Port Toggle Output Register +#define GPIOE_PTOR REG_32(0x400FF10C) +// Port Data Input Register +#define GPIOE_PDIR REG_32(0x400FF110) +// Port Data Direction Register +#define GPIOE_PDDR REG_32(0x400FF114) #endif /* MK20DX256_REG_GPIO_H */ |