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* stm32: Add comments on PLL frequency requirements to clock setup codeKevin O'Connor2025-06-021-0/+2
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32g0: Disable internal pull-down resistors on UCPDx CCx pins, because ↵BIGTREETECH2024-01-211-0/+2
| | | | | klipper never uses UCPD (#6462) Signed-off-by: Alan.Ma from BigTreeTech <tech@biqu3d.com>
* stm32: Support for USART5 on STM32G0B1 (#6105)Florin Popescu2023-04-191-0/+8
| | | | | | | Support for USART5 on PD2,3 Add exception on RCC bits for USART5&6 Signed-off-by: Florin Popescu <florinsgpopescu@gmail.com>
* stm32: Expand stm32g0 family (#5838)Alex Voinea2023-01-031-2/+11
| | | | | Add stm32g07x family support. Signed-off-by: Alex Voinea <voinea.dragos.alexandru@gmail.com>
* stm32: Move dfu reboot logic to new dfu_reboot.c fileKevin O'Connor2022-12-181-26/+2
| | | | | | | Move the stm32 DFU reboot logic to a new dfu_reboot.c file. This simplifies the per-chip code. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Minor changes to stm32g0b0 ifdefsKevin O'Connor2022-12-151-2/+2
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32g0: add stm32g0b0 supportAlex Voinea2022-12-151-1/+5
| | | Signed-off-by: Alex Voinea <voinea.dragos.alexandru@gmail.com>
* stm32g0: Do not disable SWD by accidentAlex Voinea2022-12-111-2/+5
| | | | | | Keep SWEN as 1 in FLASH->ACR register such that the SWD interface doesn't get disabled. Signed-off-by: Alex Voinea <voinea.dragos.alexandru@gmail.com>
* stm32: Fix i2c on stm32g0Kevin O'Connor2022-09-111-0/+2
| | | | | | Fix the gpio function. Also, add buses found only on stm32g0. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Add Hardware PWM support for STM32G0 processors (#5714)Ben Jackson2022-09-011-2/+17
| | | | | | | | | | | Uses existing common code for STM32. Adds a table for device- specific PWM mappings. Adds support for enabling all TIM timer devices. Makes it a runtime error to enable devices the code doesn't know how to enable. I have verified performance of the fan pins (PC6, PC7, PB15) on the SKR Mini E3 V3. Signed-off-by: Ben Jackson <ben@ben.com>
* stm32: Use new CONFIG_USB to determine if USB needs to be configuredKevin O'Connor2022-08-161-1/+1
| | | | | | | | | | | | Introduce a CONFIG_USB build symbol that is set whenever CONFIG_USBSERIAL or CONFIG_USBCANBUS is set. Use that symbol during setup so that the USB controller is properly initialized for both usb serial and usb canbus bridge configurations. This fixes the clock configuration for usb canbus bridge mode on stm32f446. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* usb_cdc: Rename usb_request_bootloader() to bootloader_request()Kevin O'Connor2022-07-291-2/+3
| | | | | | | Rename this board API function to a more generic name. This is in preparation for calling the function from the canbus code. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: stm32g0/h7 usb_dfu_bootloader support (#5596)BIGTREETECH2022-06-301-1/+2
| | | Signed-off-by: Alan.Ma from BigTreeTech <tech@biqu3d.com>
* armcm_reset: Add a armcm_reset.h header file for try_request_canboot()Kevin O'Connor2022-06-041-0/+1
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: call "try_request_canboot" for bootloader requestsEric Callahan2022-06-031-0/+1
| | | | Signed-off-by: Eric Callahan <arksine.code@gmail.com>
* stm32: stm32g0b1 fdcan support (#5488)BIGTREETECH2022-06-011-0/+2
| | | Signed-off-by: Alan.Ma from BigTreeTech <tech@biqu3d.com>
* stm32: Clarify CCIPR2 setting in stm32g0.cKevin O'Connor2022-03-111-1/+1
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Simplify CCIPR2 register assignment on stm32g0Kevin O'Connor2022-03-091-5/+2
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: USB clock source from PLLQCLK on stm32g0 (#5341)BIGTREETECH2022-03-091-6/+4
| | | Signed-off-by: Alan.Ma from BigTreeTech <tech@biqu3d.com>
* stm32: Unify enable_pclock() codeKevin O'Connor2021-12-301-59/+17
| | | | | | | | | Unify the handling of the enable_pclock() and is_enabled_pclock() code across all stm32 chips. All chips will now perform a peripheral reset on enable_pclock() (this is a change for stm32f0 and stm32h7). The enable_pclock() code will now also disable irqs during the enable. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Initial support for stm32g0Kevin O'Connor2021-12-231-0/+217
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
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