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| author | Ben Jackson <ben@ben.com> | 2022-09-01 10:30:11 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-09-01 13:30:11 -0400 |
| commit | b220b8bfaf9f54989286f6be373064a768ae28ae (patch) | |
| tree | 6e3a58bac4bf6fc4bd81b2416e769132ff22fce3 /src/stm32/stm32g0.c | |
| parent | 83ab6fbae537ee9a454cf804180a5a56008dfdfe (diff) | |
| download | kutter-b220b8bfaf9f54989286f6be373064a768ae28ae.tar.gz kutter-b220b8bfaf9f54989286f6be373064a768ae28ae.tar.xz kutter-b220b8bfaf9f54989286f6be373064a768ae28ae.zip | |
stm32: Add Hardware PWM support for STM32G0 processors (#5714)
Uses existing common code for STM32. Adds a table for device-
specific PWM mappings. Adds support for enabling all TIM timer
devices. Makes it a runtime error to enable devices the code
doesn't know how to enable.
I have verified performance of the fan pins (PC6, PC7, PB15)
on the SKR Mini E3 V3.
Signed-off-by: Ben Jackson <ben@ben.com>
Diffstat (limited to 'src/stm32/stm32g0.c')
| -rw-r--r-- | src/stm32/stm32g0.c | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/src/stm32/stm32g0.c b/src/stm32/stm32g0.c index 63edcbaa..1964d89f 100644 --- a/src/stm32/stm32g0.c +++ b/src/stm32/stm32g0.c @@ -38,14 +38,29 @@ lookup_clock_line(uint32_t periph_base) return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<13}; if (periph_base == CRS_BASE) return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<16}; + if (periph_base == TIM1_BASE) + return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<11}; if (periph_base == SPI1_BASE) return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<12}; if (periph_base == USART1_BASE) return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<14}; + if (periph_base == TIM14_BASE) + return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<15}; + if (periph_base == TIM15_BASE) + return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<16}; + if (periph_base == TIM16_BASE) + return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<17}; + if (periph_base == TIM17_BASE) + return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<18}; if (periph_base == ADC1_BASE) return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<20}; - uint32_t bit = 1 << ((periph_base - APBPERIPH_BASE) / 0x400); - return (struct cline){.en=&RCC->APBENR1, .rst=&RCC->APBRSTR1, .bit=bit}; + if (periph_base >= APBPERIPH_BASE && periph_base <= LPTIM1_BASE) + { + uint32_t bit = 1 << ((periph_base - APBPERIPH_BASE) / 0x400); + return (struct cline){.en=&RCC->APBENR1, .rst=&RCC->APBRSTR1, .bit=bit}; + } + // unknown peripheral. returning .bit=0 makes this a no-op + return (struct cline){.en=&RCC->APBENR1, .rst=NULL, .bit=0}; } // Return the frequency of the given peripheral clock |