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| author | Alex Voinea <voinea.dragos.alexandru@gmail.com> | 2023-01-03 19:43:46 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-01-03 12:43:46 -0500 |
| commit | 9c2ccceb9f4890abe9d2c8a0953ae59fd529b8ef (patch) | |
| tree | 706002d244b96368930ad777d434fcbcdf014815 /src/stm32/stm32g0.c | |
| parent | b337cc3ee87c6620d2211a08e5568d59ad92b681 (diff) | |
| download | kutter-9c2ccceb9f4890abe9d2c8a0953ae59fd529b8ef.tar.gz kutter-9c2ccceb9f4890abe9d2c8a0953ae59fd529b8ef.tar.xz kutter-9c2ccceb9f4890abe9d2c8a0953ae59fd529b8ef.zip | |
stm32: Expand stm32g0 family (#5838)
Add stm32g07x family support.
Signed-off-by: Alex Voinea <voinea.dragos.alexandru@gmail.com>
Diffstat (limited to 'src/stm32/stm32g0.c')
| -rw-r--r-- | src/stm32/stm32g0.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/src/stm32/stm32g0.c b/src/stm32/stm32g0.c index 41f7f6f2..b96d4a51 100644 --- a/src/stm32/stm32g0.c +++ b/src/stm32/stm32g0.c @@ -36,14 +36,18 @@ lookup_clock_line(uint32_t periph_base) if ((periph_base == FDCAN1_BASE) || (periph_base == FDCAN2_BASE)) return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<12}; #endif +#ifdef USB_BASE if (periph_base == USB_BASE) return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<13}; +#endif #ifdef CRS_BASE if (periph_base == CRS_BASE) return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<16}; #endif +#ifdef I2C3_BASE if (periph_base == I2C3_BASE) return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<23}; +#endif if (periph_base == TIM1_BASE) return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<11}; if (periph_base == SPI1_BASE) @@ -106,8 +110,11 @@ clock_setup(void) } pllcfgr |= (pll_freq/pll_base) << RCC_PLLCFGR_PLLN_Pos; pllcfgr |= (pll_freq/CONFIG_CLOCK_FREQ - 1) << RCC_PLLCFGR_PLLR_Pos; - pllcfgr |= (pll_freq/FREQ_USB - 1) << RCC_PLLCFGR_PLLQ_Pos; - RCC->PLLCFGR = pllcfgr | RCC_PLLCFGR_PLLREN | RCC_PLLCFGR_PLLQEN; +#ifdef RCC_PLLCFGR_PLLQ + pllcfgr |= ((pll_freq/FREQ_USB - 1) << RCC_PLLCFGR_PLLQ_Pos) + | RCC_PLLCFGR_PLLQEN; +#endif + RCC->PLLCFGR = pllcfgr | RCC_PLLCFGR_PLLREN; RCC->CR |= RCC_CR_PLLON; // Wait for PLL lock @@ -119,8 +126,10 @@ clock_setup(void) while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != (2 << RCC_CFGR_SWS_Pos)) ; +#ifdef USB_BASE // Use PLLQCLK for USB (setting USBSEL=2 works in practice) RCC->CCIPR2 = 2 << RCC_CCIPR2_USBSEL_Pos; +#endif } |