atsamd: Clarify clock generation code

Implement gen_clock() and route_pclock() helpers in an effort to make
the code more readable.

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>

1 files changed, 35 insertions, 30 deletions

diff --git a/src/atsamd/clock.c b/src/atsamd/clock.c
index ef0cd9bc..af4d1158 100644
--- a/src/atsamd/clock.c
+++ b/src/atsamd/clock.c
@@ -1,10 +1,9 @@
 // Code to setup peripheral clocks on the SAMD21
 //
-// Copyright (C) 2018  Kevin O'Connor <kevin@koconnor.net>
+// Copyright (C) 2018-2019  Kevin O'Connor <kevin@koconnor.net>
 //
 // This file may be distributed under the terms of the GNU GPLv3 license.
 
-#include "autoconf.h" // CONFIG_CLOCK_FREQ
 #include "compiler.h" // DIV_ROUND_CLOSEST
 #include "internal.h" // enable_pclock
 #include "samd21.h" // GCLK
@@ -14,18 +13,34 @@
 #define CLKGEN_32K 1
 #define CLKGEN_ULP32K 2
 
-// Enable a peripheral clock and power to that peripheral
-void
-enable_pclock(uint32_t clock_id, uint32_t pmask)
+#define FREQ_MAIN 48000000
+#define FREQ_32K 32768
+
+// Configure a clock generator using a given source as input
+static inline void
+gen_clock(uint32_t clkgen_id, uint32_t flags)
 {
-    GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_ID(clock_id)
-                         | GCLK_CLKCTRL_GEN(CLKGEN_MAIN) | GCLK_CLKCTRL_CLKEN);
+    GCLK->GENDIV.reg = GCLK_GENDIV_ID(clkgen_id);
+    GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(clkgen_id) | flags | GCLK_GENCTRL_GENEN;
+}
+
+// Route a peripheral clock to a given clkgen
+static inline void
+route_pclock(uint32_t pclk_id, uint32_t clkgen_id)
+{
+    GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_ID(pclk_id)
+                         | GCLK_CLKCTRL_GEN(clkgen_id) | GCLK_CLKCTRL_CLKEN);
     while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY)
         ;
-    PM->APBCMASK.reg |= pmask;
 }
 
-#define FREQ_XOSC32K 32768
+// Enable a peripheral clock and power to that peripheral
+void
+enable_pclock(uint32_t pclk_id, uint32_t pmask)
+{
+    route_pclock(pclk_id, CLKGEN_MAIN);
+    PM->APBCMASK.reg |= pmask;
+}
 
 void
 SystemInit(void)
@@ -33,31 +48,24 @@ SystemInit(void)
     // Setup flash to work with 48Mhz clock
     NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_RWS_HALF;
 
-    // Enable external 32Khz crystal
-    uint32_t val = (SYSCTRL_XOSC32K_STARTUP(6)
-                    | SYSCTRL_XOSC32K_XTALEN | SYSCTRL_XOSC32K_EN32K);
-    SYSCTRL->XOSC32K.reg = val;
-    SYSCTRL->XOSC32K.reg = val | SYSCTRL_XOSC32K_ENABLE;
-    while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_XOSC32KRDY))
-        ;
-
     // Reset GCLK
     GCLK->CTRL.reg = GCLK_CTRL_SWRST;
     while (GCLK->CTRL.reg & GCLK_CTRL_SWRST)
         ;
 
-    // Route external 32Khz clock to DFLL48M (via CLKGEN_32K)
-    GCLK->GENDIV.reg = GCLK_GENDIV_ID(CLKGEN_32K);
-    GCLK->GENCTRL.reg = (GCLK_GENCTRL_ID(CLKGEN_32K)
-                         | GCLK_GENCTRL_SRC_XOSC32K | GCLK_GENCTRL_GENEN);
-    GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_ID(SYSCTRL_GCLK_ID_DFLL48)
-                         | GCLK_CLKCTRL_GEN(CLKGEN_32K) | GCLK_CLKCTRL_CLKEN);
-    while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY)
+    // Enable external 32Khz crystal and route to CLKGEN_32K
+    uint32_t val = (SYSCTRL_XOSC32K_STARTUP(6)
+                    | SYSCTRL_XOSC32K_XTALEN | SYSCTRL_XOSC32K_EN32K);
+    SYSCTRL->XOSC32K.reg = val;
+    SYSCTRL->XOSC32K.reg = val | SYSCTRL_XOSC32K_ENABLE;
+    while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_XOSC32KRDY))
         ;
+    gen_clock(CLKGEN_32K, GCLK_GENCTRL_SRC_XOSC32K);
 
-    // Configure DFLL48M clock
+    // Configure DFLL48M clock (with CLKGEN_32K as reference)
+    route_pclock(SYSCTRL_GCLK_ID_DFLL48, CLKGEN_32K);
     SYSCTRL->DFLLCTRL.reg = 0;
-    uint32_t mul = DIV_ROUND_CLOSEST(CONFIG_CLOCK_FREQ, FREQ_XOSC32K);
+    uint32_t mul = DIV_ROUND_CLOSEST(FREQ_MAIN, FREQ_32K);
     SYSCTRL->DFLLMUL.reg = (SYSCTRL_DFLLMUL_CSTEP(31)
                             | SYSCTRL_DFLLMUL_FSTEP(511)
                             | SYSCTRL_DFLLMUL_MUL(mul));
@@ -70,8 +78,5 @@ SystemInit(void)
         ;
 
     // Switch main clock to DFLL48M clock
-    GCLK->GENDIV.reg = GCLK_GENDIV_ID(CLKGEN_MAIN);
-    GCLK->GENCTRL.reg = (GCLK_GENCTRL_ID(CLKGEN_MAIN)
-                         | GCLK_GENCTRL_SRC_DFLL48M
-                         | GCLK_GENCTRL_IDC | GCLK_GENCTRL_GENEN);
+    gen_clock(CLKGEN_MAIN, GCLK_GENCTRL_SRC_DFLL48M | GCLK_GENCTRL_IDC);
 }