diff options
| author | Dropeffect GmbH <code@dropeffect.com> | 2024-05-02 11:25:08 +0100 |
|---|---|---|
| committer | KevinOConnor <kevin@koconnor.net> | 2024-05-14 11:53:38 -0400 |
| commit | 80b55d352811c628bd0204fdda837acb9fce31d1 (patch) | |
| tree | ae82f08c7482992a79f151793259c9be6f068fa3 /src/stm32/stm32g4.c | |
| parent | 8f510da12bf51a58205ebd81873ec8efbaa32c43 (diff) | |
| download | kutter-80b55d352811c628bd0204fdda837acb9fce31d1.tar.gz kutter-80b55d352811c628bd0204fdda837acb9fce31d1.tar.xz kutter-80b55d352811c628bd0204fdda837acb9fce31d1.zip | |
stm32: Add FDCAN2 channel needed for stm32g4 alternate pins
Some of the alternate pins defined are routed to FDCAN2 instead of
FDCAN1, this commit uses the correct IRQ register and peripheral
clock enable bit to enable FDCAN on those pins.
Signed-off-by: Amr Elsayed from Dropeffect GmbH <code@dropeffect.com>
Diffstat (limited to 'src/stm32/stm32g4.c')
| -rw-r--r-- | src/stm32/stm32g4.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/stm32/stm32g4.c b/src/stm32/stm32g4.c index 139ea8ea..1eed3ec1 100644 --- a/src/stm32/stm32g4.c +++ b/src/stm32/stm32g4.c @@ -22,6 +22,12 @@ lookup_clock_line(uint32_t periph_base) if (periph_base < APB2PERIPH_BASE) { uint32_t pos = (periph_base - APB1PERIPH_BASE) / 0x400; if (pos < 32) { +#if defined(FDCAN2_BASE) + if (periph_base == FDCAN2_BASE) + return (struct cline){.en = &RCC->APB1ENR1, + .rst = &RCC->APB1RSTR1, + .bit = 1 << 25}; +#endif return (struct cline){.en = &RCC->APB1ENR1, .rst = &RCC->APB1RSTR1, .bit = 1 << pos}; |