From 80b55d352811c628bd0204fdda837acb9fce31d1 Mon Sep 17 00:00:00 2001 From: Dropeffect GmbH Date: Thu, 2 May 2024 11:25:08 +0100 Subject: stm32: Add FDCAN2 channel needed for stm32g4 alternate pins Some of the alternate pins defined are routed to FDCAN2 instead of FDCAN1, this commit uses the correct IRQ register and peripheral clock enable bit to enable FDCAN on those pins. Signed-off-by: Amr Elsayed from Dropeffect GmbH --- src/stm32/stm32g4.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/stm32/stm32g4.c') diff --git a/src/stm32/stm32g4.c b/src/stm32/stm32g4.c index 139ea8ea..1eed3ec1 100644 --- a/src/stm32/stm32g4.c +++ b/src/stm32/stm32g4.c @@ -22,6 +22,12 @@ lookup_clock_line(uint32_t periph_base) if (periph_base < APB2PERIPH_BASE) { uint32_t pos = (periph_base - APB1PERIPH_BASE) / 0x400; if (pos < 32) { +#if defined(FDCAN2_BASE) + if (periph_base == FDCAN2_BASE) + return (struct cline){.en = &RCC->APB1ENR1, + .rst = &RCC->APB1RSTR1, + .bit = 1 << 25}; +#endif return (struct cline){.en = &RCC->APB1ENR1, .rst = &RCC->APB1RSTR1, .bit = 1 << pos}; -- cgit v1.2.3-70-g09d2