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| author | Alex Maclean <monkeh@monkeh.net> | 2023-12-18 01:05:06 +0000 |
|---|---|---|
| committer | KevinOConnor <kevin@koconnor.net> | 2023-12-21 20:58:57 -0500 |
| commit | 77619e912ca704977836485204238b17fed26b6b (patch) | |
| tree | fc37338876f62a30a857583962c238251f0e5a54 /src/stm32/stm32g4.c | |
| parent | 147492b25357e486bea35fbeb57405dcc47e53aa (diff) | |
| download | kutter-77619e912ca704977836485204238b17fed26b6b.tar.gz kutter-77619e912ca704977836485204238b17fed26b6b.tar.xz kutter-77619e912ca704977836485204238b17fed26b6b.zip | |
stm32: Fix CAN for STM32G4
Signed-off-by: Alex Maclean <monkeh@monkeh.net>
Diffstat (limited to 'src/stm32/stm32g4.c')
| -rw-r--r-- | src/stm32/stm32g4.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/stm32/stm32g4.c b/src/stm32/stm32g4.c index aed9ed8f..139ea8ea 100644 --- a/src/stm32/stm32g4.c +++ b/src/stm32/stm32g4.c @@ -105,6 +105,9 @@ enable_clock_stm32g4(void) enable_pclock(CRS_BASE); CRS->CR |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN; } + + // Use PCLK for FDCAN + RCC->CCIPR = 2 << RCC_CCIPR_FDCANSEL_Pos; } // Main clock setup called at chip startup |