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| author | Alex Maclean <monkeh@monkeh.net> | 2023-12-18 01:05:06 +0000 |
|---|---|---|
| committer | KevinOConnor <kevin@koconnor.net> | 2023-12-21 20:58:57 -0500 |
| commit | 77619e912ca704977836485204238b17fed26b6b (patch) | |
| tree | fc37338876f62a30a857583962c238251f0e5a54 | |
| parent | 147492b25357e486bea35fbeb57405dcc47e53aa (diff) | |
| download | kutter-77619e912ca704977836485204238b17fed26b6b.tar.gz kutter-77619e912ca704977836485204238b17fed26b6b.tar.xz kutter-77619e912ca704977836485204238b17fed26b6b.zip | |
stm32: Fix CAN for STM32G4
Signed-off-by: Alex Maclean <monkeh@monkeh.net>
| -rw-r--r-- | src/stm32/fdcan.c | 6 | ||||
| -rw-r--r-- | src/stm32/stm32g4.c | 3 |
2 files changed, 6 insertions, 3 deletions
diff --git a/src/stm32/fdcan.c b/src/stm32/fdcan.c index a1624f8c..b0e8c01d 100644 --- a/src/stm32/fdcan.c +++ b/src/stm32/fdcan.c @@ -162,10 +162,10 @@ canhw_set_filter(uint32_t id) can_filter(1, id); can_filter(2, id + 1); -#if CONFIG_MACH_STM32G0 +#if CONFIG_MACH_STM32G0 || CONFIG_MACH_STM32G4 SOC_CAN->RXGFC = ((id ? 3 : 1) << FDCAN_RXGFC_LSS_Pos | 0x02 << FDCAN_RXGFC_ANFS_Pos); -#elif CONFIG_MACH_STM32H7 || CONFIG_MAC_STM32G4 +#elif CONFIG_MACH_STM32H7 uint32_t flssa = (uint32_t)MSG_RAM.FLS - SRAMCAN_BASE; SOC_CAN->SIDFC = flssa | ((id ? 3 : 1) << FDCAN_SIDFC_LSS_Pos); SOC_CAN->GFC = 0x02 << FDCAN_GFC_ANFS_Pos; @@ -293,7 +293,7 @@ can_init(void) SOC_CAN->NBTP = btr; -#if CONFIG_MACH_STM32H7 || CONFIG_MAC_STM32G4 +#if CONFIG_MACH_STM32H7 /* Setup message RAM addresses */ uint32_t f0sa = (uint32_t)MSG_RAM.RXF0 - SRAMCAN_BASE; SOC_CAN->RXF0C = f0sa | (ARRAY_SIZE(MSG_RAM.RXF0) << FDCAN_RXF0C_F0S_Pos); diff --git a/src/stm32/stm32g4.c b/src/stm32/stm32g4.c index aed9ed8f..139ea8ea 100644 --- a/src/stm32/stm32g4.c +++ b/src/stm32/stm32g4.c @@ -105,6 +105,9 @@ enable_clock_stm32g4(void) enable_pclock(CRS_BASE); CRS->CR |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN; } + + // Use PCLK for FDCAN + RCC->CCIPR = 2 << RCC_CCIPR_FDCANSEL_Pos; } // Main clock setup called at chip startup |