From b220b8bfaf9f54989286f6be373064a768ae28ae Mon Sep 17 00:00:00 2001 From: Ben Jackson Date: Thu, 1 Sep 2022 10:30:11 -0700 Subject: stm32: Add Hardware PWM support for STM32G0 processors (#5714) Uses existing common code for STM32. Adds a table for device- specific PWM mappings. Adds support for enabling all TIM timer devices. Makes it a runtime error to enable devices the code doesn't know how to enable. I have verified performance of the fan pins (PC6, PC7, PB15) on the SKR Mini E3 V3. Signed-off-by: Ben Jackson --- src/stm32/stm32g0.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) (limited to 'src/stm32/stm32g0.c') diff --git a/src/stm32/stm32g0.c b/src/stm32/stm32g0.c index 63edcbaa..1964d89f 100644 --- a/src/stm32/stm32g0.c +++ b/src/stm32/stm32g0.c @@ -38,14 +38,29 @@ lookup_clock_line(uint32_t periph_base) return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<13}; if (periph_base == CRS_BASE) return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<16}; + if (periph_base == TIM1_BASE) + return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<11}; if (periph_base == SPI1_BASE) return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<12}; if (periph_base == USART1_BASE) return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<14}; + if (periph_base == TIM14_BASE) + return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<15}; + if (periph_base == TIM15_BASE) + return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<16}; + if (periph_base == TIM16_BASE) + return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<17}; + if (periph_base == TIM17_BASE) + return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<18}; if (periph_base == ADC1_BASE) return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<20}; - uint32_t bit = 1 << ((periph_base - APBPERIPH_BASE) / 0x400); - return (struct cline){.en=&RCC->APBENR1, .rst=&RCC->APBRSTR1, .bit=bit}; + if (periph_base >= APBPERIPH_BASE && periph_base <= LPTIM1_BASE) + { + uint32_t bit = 1 << ((periph_base - APBPERIPH_BASE) / 0x400); + return (struct cline){.en=&RCC->APBENR1, .rst=&RCC->APBRSTR1, .bit=bit}; + } + // unknown peripheral. returning .bit=0 makes this a no-op + return (struct cline){.en=&RCC->APBENR1, .rst=NULL, .bit=0}; } // Return the frequency of the given peripheral clock -- cgit v1.2.3-70-g09d2