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| author | Kevin O'Connor <kevin@koconnor.net> | 2019-08-20 01:04:20 -0400 |
|---|---|---|
| committer | Kevin O'Connor <kevin@koconnor.net> | 2019-08-20 01:10:14 -0400 |
| commit | c930fc392b6977b17d6f7953bd738583974208c2 (patch) | |
| tree | e0198fd4ea70b358579673428da1cb91cc3ccfa9 /src/stm32/stm32f4.c | |
| parent | a67451fa3688c10faa4caf589235b07ef01c30f1 (diff) | |
| download | kutter-c930fc392b6977b17d6f7953bd738583974208c2.tar.gz kutter-c930fc392b6977b17d6f7953bd738583974208c2.tar.xz kutter-c930fc392b6977b17d6f7953bd738583974208c2.zip | |
stm32: Make sure to enable the gpio clock prior to setting the first value
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src/stm32/stm32f4.c')
| -rw-r--r-- | src/stm32/stm32f4.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/stm32/stm32f4.c b/src/stm32/stm32f4.c index dab8d524..5a09f2d6 100644 --- a/src/stm32/stm32f4.c +++ b/src/stm32/stm32f4.c @@ -53,6 +53,15 @@ get_pclock_frequency(uint32_t periph_base) return FREQ_PERIPH; } +// Enable a GPIO peripheral clock +void +gpio_clock_enable(GPIO_TypeDef *regs) +{ + uint32_t rcc_pos = ((uint32_t)regs - AHB1PERIPH_BASE) / 0x400; + RCC->AHB1ENR |= 1 << rcc_pos; + RCC->AHB1ENR; +} + // Set the mode and extended function of a pin void gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup) @@ -60,8 +69,7 @@ gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup) GPIO_TypeDef *regs = digital_regs[GPIO2PORT(gpio)]; // Enable GPIO clock - uint32_t rcc_pos = ((uint32_t)regs - AHB1PERIPH_BASE) / 0x400; - RCC->AHB1ENR |= (1<<rcc_pos); + gpio_clock_enable(regs); // Configure GPIO uint32_t mode_bits = mode & 0x0f, func = mode >> 4; |