aboutsummaryrefslogtreecommitdiffstats
path: root/src/stm32/stm32f1.c
diff options
context:
space:
mode:
authorKevin O'Connor <kevin@koconnor.net>2025-05-31 17:00:18 -0400
committerKevin O'Connor <kevin@koconnor.net>2025-06-02 13:15:53 -0400
commit105ce35e1ba813b7ebe1be2a87fd852a5f7b66f5 (patch)
tree0c0c55df7baba74b5eaf4f400744cc4e2e9a93dc /src/stm32/stm32f1.c
parentc0ca4c5cc7379046221a250ce9c90f514e85ca7e (diff)
downloadkutter-105ce35e1ba813b7ebe1be2a87fd852a5f7b66f5.tar.gz
kutter-105ce35e1ba813b7ebe1be2a87fd852a5f7b66f5.tar.xz
kutter-105ce35e1ba813b7ebe1be2a87fd852a5f7b66f5.zip
stm32: Add comments on PLL frequency requirements to clock setup code
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src/stm32/stm32f1.c')
-rw-r--r--src/stm32/stm32f1.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/stm32/stm32f1.c b/src/stm32/stm32f1.c
index 9d3c3b97..0e4cb782 100644
--- a/src/stm32/stm32f1.c
+++ b/src/stm32/stm32f1.c
@@ -51,6 +51,8 @@ gpio_clock_enable(GPIO_TypeDef *regs)
RCC->APB2ENR;
}
+// PLL (f103) input: 1 to 25Mhz, output: 16 to 72Mhz
+
// Main clock setup called at chip startup
static void
clock_setup(void)