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authorKevin O'Connor <kevin@koconnor.net>2021-12-24 12:23:56 -0500
committerKevin O'Connor <kevin@koconnor.net>2021-12-30 12:18:05 -0500
commit8b6753d68f681b0ed7e76b5e05b2bc7da6d5aa1d (patch)
treec6f888a77627d6276ed84394c203c552ba348a15 /src/stm32/clockline.c
parent9bdd61758e61d4652ae09515425c3316c6cfe905 (diff)
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stm32: Unify enable_pclock() code
Unify the handling of the enable_pclock() and is_enabled_pclock() code across all stm32 chips. All chips will now perform a peripheral reset on enable_pclock() (this is a change for stm32f0 and stm32h7). The enable_pclock() code will now also disable irqs during the enable. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src/stm32/clockline.c')
-rw-r--r--src/stm32/clockline.c32
1 files changed, 32 insertions, 0 deletions
diff --git a/src/stm32/clockline.c b/src/stm32/clockline.c
new file mode 100644
index 00000000..970ce9da
--- /dev/null
+++ b/src/stm32/clockline.c
@@ -0,0 +1,32 @@
+// Code to enable clock lines on stm32
+//
+// Copyright (C) 2021 Kevin O'Connor <kevin@koconnor.net>
+//
+// This file may be distributed under the terms of the GNU GPLv3 license.
+
+#include "board/irq.h" // irq_save
+#include "internal.h" // struct cline
+
+// Enable a peripheral clock
+void
+enable_pclock(uint32_t periph_base)
+{
+ struct cline cl = lookup_clock_line(periph_base);
+ irqstatus_t flag = irq_save();
+ *cl.en |= cl.bit;
+ *cl.en; // Pause 2 cycles to ensure peripheral is enabled
+ if (cl.rst) {
+ // Reset peripheral
+ *cl.rst = cl.bit;
+ *cl.rst = 0;
+ }
+ irq_restore(flag);
+}
+
+// Check if a peripheral clock has been enabled
+int
+is_enabled_pclock(uint32_t periph_base)
+{
+ struct cline cl = lookup_clock_line(periph_base);
+ return *cl.en & cl.bit;
+}