From 8b6753d68f681b0ed7e76b5e05b2bc7da6d5aa1d Mon Sep 17 00:00:00 2001 From: Kevin O'Connor Date: Fri, 24 Dec 2021 12:23:56 -0500 Subject: stm32: Unify enable_pclock() code Unify the handling of the enable_pclock() and is_enabled_pclock() code across all stm32 chips. All chips will now perform a peripheral reset on enable_pclock() (this is a change for stm32f0 and stm32h7). The enable_pclock() code will now also disable irqs during the enable. Signed-off-by: Kevin O'Connor --- src/stm32/clockline.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 src/stm32/clockline.c (limited to 'src/stm32/clockline.c') diff --git a/src/stm32/clockline.c b/src/stm32/clockline.c new file mode 100644 index 00000000..970ce9da --- /dev/null +++ b/src/stm32/clockline.c @@ -0,0 +1,32 @@ +// Code to enable clock lines on stm32 +// +// Copyright (C) 2021 Kevin O'Connor +// +// This file may be distributed under the terms of the GNU GPLv3 license. + +#include "board/irq.h" // irq_save +#include "internal.h" // struct cline + +// Enable a peripheral clock +void +enable_pclock(uint32_t periph_base) +{ + struct cline cl = lookup_clock_line(periph_base); + irqstatus_t flag = irq_save(); + *cl.en |= cl.bit; + *cl.en; // Pause 2 cycles to ensure peripheral is enabled + if (cl.rst) { + // Reset peripheral + *cl.rst = cl.bit; + *cl.rst = 0; + } + irq_restore(flag); +} + +// Check if a peripheral clock has been enabled +int +is_enabled_pclock(uint32_t periph_base) +{ + struct cline cl = lookup_clock_line(periph_base); + return *cl.en & cl.bit; +} -- cgit v1.2.3-70-g09d2