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authorKevin O'Connor <kevin@koconnor.net>2018-11-21 20:40:34 -0500
committerKevin O'Connor <kevin@koconnor.net>2018-11-21 20:44:39 -0500
commitcbbc6801a023684331d323366ac2795da73828f7 (patch)
treed026c8e4b6ac0236b06e3a0891f489c9f2715a8b /src/lpc176x/spi.c
parent4bbd6310864b231f26c3c069052a610a2178a456 (diff)
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lpc176x: Enable full speed peripheral clocks on SPI and I2C
Scale the bus speed within the peripheral instead of on the system bus as scaling on the system bus slows down general register access to the peripheral. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src/lpc176x/spi.c')
-rw-r--r--src/lpc176x/spi.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/lpc176x/spi.c b/src/lpc176x/spi.c
index 92e303d0..8373a39f 100644
--- a/src/lpc176x/spi.c
+++ b/src/lpc176x/spi.c
@@ -23,6 +23,9 @@ spi_init(void)
gpio_peripheral(0, 17, 2, 0);
gpio_peripheral(0, 18, 2, 0);
+ // Setup clock
+ enable_peripheral_clock(PCLK_SSP0);
+
// Set initial registers
LPC_SSP0->CR0 = 0x07;
LPC_SSP0->CPSR = 254;
@@ -40,7 +43,7 @@ spi_setup(uint32_t bus, uint8_t mode, uint32_t rate)
// Setup clock rate and mode
struct spi_config res = {0, 0};
- uint32_t pclk = SystemCoreClock / 4;
+ uint32_t pclk = SystemCoreClock;
uint32_t div = DIV_ROUND_UP(pclk/2, rate) << 1;
res.cpsr = div < 2 ? 2 : (div > 254 ? 254 : div);
res.cr0 = 0x07 | (mode << 6);