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| author | Kevin O'Connor <kevin@koconnor.net> | 2018-11-21 20:40:34 -0500 |
|---|---|---|
| committer | Kevin O'Connor <kevin@koconnor.net> | 2018-11-21 20:44:39 -0500 |
| commit | cbbc6801a023684331d323366ac2795da73828f7 (patch) | |
| tree | d026c8e4b6ac0236b06e3a0891f489c9f2715a8b /src | |
| parent | 4bbd6310864b231f26c3c069052a610a2178a456 (diff) | |
| download | kutter-cbbc6801a023684331d323366ac2795da73828f7.tar.gz kutter-cbbc6801a023684331d323366ac2795da73828f7.tar.xz kutter-cbbc6801a023684331d323366ac2795da73828f7.zip | |
lpc176x: Enable full speed peripheral clocks on SPI and I2C
Scale the bus speed within the peripheral instead of on the system bus
as scaling on the system bus slows down general register access to the
peripheral.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src')
| -rw-r--r-- | src/lpc176x/i2c.c | 3 | ||||
| -rw-r--r-- | src/lpc176x/internal.h | 2 | ||||
| -rw-r--r-- | src/lpc176x/spi.c | 5 |
3 files changed, 8 insertions, 2 deletions
diff --git a/src/lpc176x/i2c.c b/src/lpc176x/i2c.c index 50081d50..58761aba 100644 --- a/src/lpc176x/i2c.c +++ b/src/lpc176x/i2c.c @@ -29,7 +29,8 @@ i2c_init(void) gpio_peripheral(0, 1, 3, 0); // Set 100Khz frequency - uint32_t PCLK = SystemCoreClock / 4, pulse = PCLK / (100000 * 2); + enable_peripheral_clock(PCLK_I2C1); + uint32_t pclk = SystemCoreClock, pulse = pclk / (100000 * 2); LPC_I2C1->I2SCLL = pulse; LPC_I2C1->I2SCLH = pulse; diff --git a/src/lpc176x/internal.h b/src/lpc176x/internal.h index 1ea07df4..e5b0f5dc 100644 --- a/src/lpc176x/internal.h +++ b/src/lpc176x/internal.h @@ -5,6 +5,8 @@ #define PCLK_TIMER0 1 #define PCLK_UART0 3 #define PCLK_ADC 12 +#define PCLK_I2C1 19 +#define PCLK_SSP0 21 void enable_peripheral_clock(uint32_t pclk); void gpio_peripheral(int bank, int pin, int func, int pullup); diff --git a/src/lpc176x/spi.c b/src/lpc176x/spi.c index 92e303d0..8373a39f 100644 --- a/src/lpc176x/spi.c +++ b/src/lpc176x/spi.c @@ -23,6 +23,9 @@ spi_init(void) gpio_peripheral(0, 17, 2, 0); gpio_peripheral(0, 18, 2, 0); + // Setup clock + enable_peripheral_clock(PCLK_SSP0); + // Set initial registers LPC_SSP0->CR0 = 0x07; LPC_SSP0->CPSR = 254; @@ -40,7 +43,7 @@ spi_setup(uint32_t bus, uint8_t mode, uint32_t rate) // Setup clock rate and mode struct spi_config res = {0, 0}; - uint32_t pclk = SystemCoreClock / 4; + uint32_t pclk = SystemCoreClock; uint32_t div = DIV_ROUND_UP(pclk/2, rate) << 1; res.cpsr = div < 2 ? 2 : (div > 254 ? 254 : div); res.cr0 = 0x07 | (mode << 6); |