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authorKevin O'Connor <kevin@koconnor.net>2019-04-01 00:11:23 -0400
committerKevin O'Connor <kevin@koconnor.net>2019-04-04 18:29:31 -0400
commit3e71a57f67ce0dde62e942dfa33bf38d64262916 (patch)
treef4b128d810d8678d41b71c6a02aa23875c2c9ea7 /src/lpc176x/spi.c
parentbc9fd03dabc38ae55fae3151e94cffe7157b95bd (diff)
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lpc176x: Use enumerations for buses and reserve pins
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src/lpc176x/spi.c')
-rw-r--r--src/lpc176x/spi.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/lpc176x/spi.c b/src/lpc176x/spi.c
index e959877c..bfdb8fe8 100644
--- a/src/lpc176x/spi.c
+++ b/src/lpc176x/spi.c
@@ -10,6 +10,9 @@
#include "internal.h" // gpio_peripheral
#include "sched.h" // sched_shutdown
+DECL_ENUMERATION("spi_bus", "ssp0", 0);
+DECL_CONSTANT_STR("BUS_PINS_ssp0", "P0.17,P0.18,P0.15");
+
static void
spi_init(void)
{
@@ -18,10 +21,10 @@ spi_init(void)
return;
have_run_init = 1;
- // Configure SCK0, MISO0, MOSI0 pins
- gpio_peripheral(GPIO(0, 15), 2, 0);
+ // Configure MISO0, MOSI0, SCK0 pins
gpio_peripheral(GPIO(0, 17), 2, 0);
gpio_peripheral(GPIO(0, 18), 2, 0);
+ gpio_peripheral(GPIO(0, 15), 2, 0);
// Setup clock
enable_pclock(PCLK_SSP0);