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| author | Kevin O'Connor <kevin@koconnor.net> | 2025-04-28 20:14:14 -0400 |
|---|---|---|
| committer | Kevin O'Connor <kevin@koconnor.net> | 2025-05-02 11:44:31 -0400 |
| commit | ee79d0e30764b92f479bfc7126b61ecdf2f8d161 (patch) | |
| tree | d93ca82666908c283e7f755ced4f5bb219c92e59 | |
| parent | 7b697105b32cf48dfe677e047935d413f3324775 (diff) | |
| download | kutter-ee79d0e30764b92f479bfc7126b61ecdf2f8d161.tar.gz kutter-ee79d0e30764b92f479bfc7126b61ecdf2f8d161.tar.xz kutter-ee79d0e30764b92f479bfc7126b61ecdf2f8d161.zip | |
stm32: Support over 400Mhz main clock in stm32h7_adc.c
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
| -rw-r--r-- | src/stm32/stm32h7_adc.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/src/stm32/stm32h7_adc.c b/src/stm32/stm32h7_adc.c index 6740edd3..a630f266 100644 --- a/src/stm32/stm32h7_adc.c +++ b/src/stm32/stm32h7_adc.c @@ -160,10 +160,10 @@ static const uint8_t adc_pins[] = { #define ADC_CKMODE 0b11 #define ADC_ATICKS 0b110 #define ADC_ATICKS_H723_ADC3 0b111 -// stm32h7: clock=25Mhz, Tsamp=387.5, Tconv=394, total=15.76us -// stm32h723 adc3: clock=50Mhz, Tsamp=640.5, Tconv=653, total=13.06us -// stm32l4: clock=20Mhz, Tsamp=247.5, Tconv=260, total=13.0us -// stm32g4: clock=37.5Mhz, Tsamp=247.5, Tconv=260, total=6.933us +// 400Mhz stm32h7: clock=25Mhz, Tsamp=387.5, Tconv=394, total=15.76us +// 400Mhz stm32h723 adc3: clock=50Mhz, Tsamp=640.5, Tconv=653, total=13.06us +// 80Mhz stm32l4: clock=20Mhz, Tsamp=247.5, Tconv=260, total=13.0us +// 150Mhz stm32g4: clock=37.5Mhz, Tsamp=247.5, Tconv=260, total=6.933us // Handle register name differences between chips #if CONFIG_MACH_STM32H723 @@ -231,8 +231,9 @@ gpio_adc_setup(uint32_t pin) } else { // Use linear calibration on stm32h7 cr |= ADC_CR_ADCALLIN; - // Set boost mode on stm32h7 (adc clock is at 25Mhz) - cr |= 0b10 << ADC_CR_BOOST_Pos; + // Set boost mode on stm32h7 + uint32_t boost = CONFIG_CLOCK_FREQ > 400000000 ? 0b11 : 0b10; + cr |= boost << ADC_CR_BOOST_Pos; // Set 12bit samples on the stm32h7 adc->CFGR = ADC_CFGR_JQDIS | (0b110 << ADC_CFGR_RES_Pos); } |