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| author | Alex Maclean <monkeh@monkeh.net> | 2023-12-15 22:49:07 +0000 |
|---|---|---|
| committer | KevinOConnor <kevin@koconnor.net> | 2023-12-21 20:58:57 -0500 |
| commit | 147492b25357e486bea35fbeb57405dcc47e53aa (patch) | |
| tree | e14737af2648e07166075e2de727ea726e64f261 | |
| parent | 71ab6240f2dd8132ab29d9251690b3f8b6da0517 (diff) | |
| download | kutter-147492b25357e486bea35fbeb57405dcc47e53aa.tar.gz kutter-147492b25357e486bea35fbeb57405dcc47e53aa.tar.xz kutter-147492b25357e486bea35fbeb57405dcc47e53aa.zip | |
stm32: Fix ADC for STM32G4
At least STM32G4 requires four ADC clock cycles between hardware
clearing ADCCAL and setting ADEN or the write disappears. Make a
tenacious write attempt.
Signed-off-by: Alex Maclean <monkeh@monkeh.net>
| -rw-r--r-- | src/stm32/stm32h7_adc.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/stm32/stm32h7_adc.c b/src/stm32/stm32h7_adc.c index 57d4b15c..e9dc8f84 100644 --- a/src/stm32/stm32h7_adc.c +++ b/src/stm32/stm32h7_adc.c @@ -240,9 +240,10 @@ gpio_adc_setup(uint32_t pin) // Enable ADC adc->ISR = ADC_ISR_ADRDY; adc->ISR; // Dummy read to make sure write is flushed - adc->CR |= ADC_CR_ADEN; + while (!(adc->CR & ADC_CR_ADEN)) + adc->CR |= ADC_CR_ADEN; while (!(adc->ISR & ADC_ISR_ADRDY)) - ; + ; // Set ADC clock cycles sample time for every channel uint32_t av = (aticks | (aticks << 3) | (aticks << 6) |