diff options
author | Tomasz Kramkowski <tk@the-tk.com> | 2016-10-20 23:43:29 +0100 |
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committer | Tomasz Kramkowski <tk@the-tk.com> | 2016-10-20 23:43:29 +0100 |
commit | c3c5f1e5fe27574220c3e94a79048e066cacc121 (patch) | |
tree | 445096a0365cc45c959091355852c9b63d8a338a /lib | |
download | fmk-c3c5f1e5fe27574220c3e94a79048e066cacc121.tar.gz fmk-c3c5f1e5fe27574220c3e94a79048e066cacc121.tar.xz fmk-c3c5f1e5fe27574220c3e94a79048e066cacc121.zip |
Init commit
Diffstat (limited to 'lib')
-rw-r--r-- | lib/le.c | 54 | ||||
-rw-r--r-- | lib/le.h | 12 | ||||
-rw-r--r-- | lib/reg.h | 45 | ||||
-rw-r--r-- | lib/reg/gpio.h | 41 | ||||
-rw-r--r-- | lib/reg/mcg.h | 56 | ||||
-rw-r--r-- | lib/reg/pmc.h | 27 | ||||
-rw-r--r-- | lib/reg/port.h | 42 | ||||
-rw-r--r-- | lib/reg/regdefs.h | 25 | ||||
-rw-r--r-- | lib/reg/sim.h | 70 | ||||
-rw-r--r-- | lib/reg/uart.h | 8 | ||||
-rw-r--r-- | lib/reg/usbotg.h | 202 | ||||
-rw-r--r-- | lib/reg/wdog.h | 37 | ||||
-rw-r--r-- | lib/string.c | 38 | ||||
-rw-r--r-- | lib/string.h | 10 |
14 files changed, 667 insertions, 0 deletions
diff --git a/lib/le.c b/lib/le.c new file mode 100644 index 0000000..47ed5f8 --- /dev/null +++ b/lib/le.c @@ -0,0 +1,54 @@ +/* lib/le.c -- Basic little endian byte order functions + * + * Copyright (C) 2016 Tomasz Kramkowski <tk@the-tk.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#include <stdint.h> + +#include "le.h" + +uint16_t le16toh(const void *_data) +{ + const unsigned char *data = _data; + + return (uint16_t)data[0] | (uint16_t)data[1] << 8; +} + +uint32_t le32toh(const void *_data) +{ + const unsigned char *data = _data; + + return (uint32_t)data[0] | (uint32_t)data[1] << 8 + | (uint32_t)data[2] << 16 | (uint32_t)data[3] << 24; +} + +void htole16(void *_data, uint16_t value) +{ + unsigned char *data = _data; + + data[0] = value >> 0 & 0xff; + data[1] = value >> 8 & 0xff; +} + +void htole32(void *_data, uint32_t value) +{ + unsigned char *data = _data; + + data[0] = value >> 0 & 0xff; + data[1] = value >> 8 & 0xff; + data[2] = value >> 16 & 0xff; + data[3] = value >> 24 & 0xff; +} diff --git a/lib/le.h b/lib/le.h new file mode 100644 index 0000000..e1341a7 --- /dev/null +++ b/lib/le.h @@ -0,0 +1,12 @@ +#ifndef LE_H +#define LE_H + +#include <stdint.h> + +uint16_t le16toh(const void *data); +uint32_t le32toh(const void *data); + +void htole16(void *data, uint16_t value); +void htole32(void *data, uint32_t value); + +#endif /* LE_H */ diff --git a/lib/reg.h b/lib/reg.h new file mode 100644 index 0000000..1a10792 --- /dev/null +++ b/lib/reg.h @@ -0,0 +1,45 @@ +#ifndef LIB_REG_H +#define LIB_REG_H + +#include <reg/port.h> +#include <reg/sim.h> +//#include <reg/rcm.h> +//#include <reg/smc.h> +#include <reg/pmc.h> +//#include <reg/llwu.h> +//#include <reg/mcm.h> +//#include <reg/axbs.h> +//#include <reg/aips.h> +//#include <reg/dmamux.h> +//#include <reg/dma.h> +//#include <reg/ewm.h> +#include <reg/wdog.h> +#include <reg/mcg.h> +//#include <reg/osc.h> +//#include <reg/rtc.h> +//#include <reg/fmc.h> +//#include <reg/ftfl.h> +/*#include <reg/ezport.h>*/ +//#include <reg/crc.h> +//#include <reg/adc.h> +//#include <reg/cmp.h> +//#include <reg/dac.h> +//#include <reg/vref.h> +//#include <reg/pdb.h> +//#include <reg/ftm.h> +//#include <reg/pit.h> +//#include <reg/lptmr.h> +//#include <reg/cmt.h> +//#include <reg/rtc.h> +//#include <reg/usbotg.h> +//#include <reg/usbdcd.h> +//#include <reg/can.h> +//#include <reg/spi.h> +//#include <reg/i2c.h> +#include <reg/uart.h> +//#include <reg/i2s.h> +#include <reg/gpio.h> +//#include <reg/tsi.h> +//#include <reg/jtagc.h> + +#endif /* LIB_REG_H */ diff --git a/lib/reg/gpio.h b/lib/reg/gpio.h new file mode 100644 index 0000000..6bb8d34 --- /dev/null +++ b/lib/reg/gpio.h @@ -0,0 +1,41 @@ +#ifndef LIB_REG_GPIO_H +#define LIB_REG_GPIO_H + +#include <reg/regdefs.h> + +#define GPIOA_PDOR REG_32(0x400FF000) /* Port Data Output Register */ +#define GPIOA_PSOR REG_32(0x400FF004) /* Port Set Output Register */ +#define GPIOA_PCOR REG_32(0x400FF008) /* Port Clear Output Register */ +#define GPIOA_PTOR REG_32(0x400FF00C) /* Port Toggle Output Register */ +#define GPIOA_PDIR REG_32(0x400FF010) /* Port Data Input Register */ +#define GPIOA_PDDR REG_32(0x400FF014) /* Port Data Direction Register */ + +#define GPIOB_PDOR REG_32(0x400FF040) /* Port Data Output Register */ +#define GPIOB_PSOR REG_32(0x400FF044) /* Port Set Output Register */ +#define GPIOB_PCOR REG_32(0x400FF048) /* Port Clear Output Register */ +#define GPIOB_PTOR REG_32(0x400FF04C) /* Port Toggle Output Register */ +#define GPIOB_PDIR REG_32(0x400FF050) /* Port Data Input Register */ +#define GPIOB_PDDR REG_32(0x400FF054) /* Port Data Direction Register */ + +#define GPIOC_PDOR REG_32(0x400FF080) /* Port Data Output Register */ +#define GPIOC_PSOR REG_32(0x400FF084) /* Port Set Output Register */ +#define GPIOC_PCOR REG_32(0x400FF088) /* Port Clear Output Register */ +#define GPIOC_PTOR REG_32(0x400FF08C) /* Port Toggle Output Register */ +#define GPIOC_PDIR REG_32(0x400FF090) /* Port Data Input Register */ +#define GPIOC_PDDR REG_32(0x400FF094) /* Port Data Direction Register */ + +#define GPIOD_PDOR REG_32(0x400FF0C0) /* Port Data Output Register */ +#define GPIOD_PSOR REG_32(0x400FF0C4) /* Port Set Output Register */ +#define GPIOD_PCOR REG_32(0x400FF0C8) /* Port Clear Output Register */ +#define GPIOD_PTOR REG_32(0x400FF0CC) /* Port Toggle Output Register */ +#define GPIOD_PDIR REG_32(0x400FF0D0) /* Port Data Input Register */ +#define GPIOD_PDDR REG_32(0x400FF0D4) /* Port Data Direction Register */ + +#define GPIOE_PDOR REG_32(0x400FF100) /* Port Data Output Register */ +#define GPIOE_PSOR REG_32(0x400FF104) /* Port Set Output Register */ +#define GPIOE_PCOR REG_32(0x400FF108) /* Port Clear Output Register */ +#define GPIOE_PTOR REG_32(0x400FF10C) /* Port Toggle Output Register */ +#define GPIOE_PDIR REG_32(0x400FF110) /* Port Data Input Register */ +#define GPIOE_PDDR REG_32(0x400FF114) /* Port Data Direction Register */ + +#endif /* LIB_REG_GPIO_H */ diff --git a/lib/reg/mcg.h b/lib/reg/mcg.h new file mode 100644 index 0000000..bc1afcf --- /dev/null +++ b/lib/reg/mcg.h @@ -0,0 +1,56 @@ +#ifndef LIB_REG_MCG_H +#define LIB_REG_MCG_H + +#include <reg/regdefs.h> + +#define MCG_C1 REG_8(0x40064000) /* MCG Control 1 Register */ +#define C1_CLKS 6 /* Clock Source Select */ +#define C1_CLKS_M (uint8_t)(BITS(2) << C1_CLKS) +#define C1_FRDIV 3 /* FLL External Reference Divider */ +#define C1_FRDIV_M (uint8_t)(BITS(3) << C1_FRDIV) +#define C1_IREFS 2 /* Internal Reference Select */ +#define C1_IRCLKEN 1 /* Internal Reference Clock Enable */ +#define C1_IREFSTEN 0 /* Internal Reference Stop Enable */ + +#define MCG_C2 REG_8(0x40064001) /* MCG Control 2 Register */ +#define C2_LOCRE0 7 /* Loss of Clock Reset Enable */ +#define C2_RANGE0 4 /* Frequency Range Select */ +#define C2_RANGE0_M (uint8_t)(BITS(2) << C2_RANGE0) +#define C2_HGO0 3 /* High Gain Oscillator Select */ +#define C2_EREFS0 2 /* External Reference Select */ +#define C2_LP 1 /* Low Power Select */ +#define C2_IRCS 0 /* Internal Reference Clock Select */ + +#define MCG_C3 REG_8(0x40064002) /* MCG Control 3 Register */ +#define MCG_C4 REG_8(0x40064003) /* MCG Control 4 Register */ + +#define MCG_C5 REG_8(0x40064004) /* MCG Control 5 Register */ +#define C5_PLLCLKEN0 6 /* PLL Clock Enable */ +#define C5_PLLSTEN0 5 /* PLL Stop Enable */ +#define C5_PRDIV0 0 /* PLL External Reference Divider */ +#define C5_PRDIV0_M (uint8_t)(BITS(5) << C5_PRDIV0) + +#define MCG_C6 REG_8(0x40064005) /* MCG Control 6 Register */ +#define C6_LOLIE0 7 /* Loss of Lock Interrrupt Enable */ +#define C6_PLLS 6 /* PLL Select */ +#define C6_CME0 5 /* Clock Monitor Enable */ +#define C6_VDIV0 0 /* VCO 0 Divider */ +#define C6_VDIV0_M (uint8_t)(BITS(5) << C6_VDIV0) + +#define MCG_S REG_8(0x40064006) /* MCG Status Register */ +#define S_LOLS0 7 /* Loss of Lock Status */ +#define S_LOCK0 6 /* Lock Status */ +#define S_PLLST 5 /* PLL Select Status */ +#define S_IREFST 4 /* Internal Reference Status */ +#define S_CLKST 2 /* Clock Mode Status */ +#define S_CLKST_M (uint8_t)(BITS(2) << S_CLKST) +#define S_OSCINIT0 1 /* OSC Initialization */ +#define S_IRCST 0 /* Internal Reference Clock Status */ + +#define MCG_SC REG_8(0x40064008) /* MCG Status and Control Register */ +#define MCG_ATCVH REG_8(0x4006400A) /* MCG Auto Trim Compare Value High Register */ +#define MCG_ATCVL REG_8(0x4006400B) /* MCG Auto Trim Compare Value Low Register */ +#define MCG_C7 REG_8(0x4006400C) /* MCG Control 7 Register */ +#define MCG_C8 REG_8(0x4006400D) /* MCG Control 8 Register */ + +#endif /* LIB_REG_MCG_H */ diff --git a/lib/reg/pmc.h b/lib/reg/pmc.h new file mode 100644 index 0000000..4aef0be --- /dev/null +++ b/lib/reg/pmc.h @@ -0,0 +1,27 @@ +#ifndef LIB_REG_PMC_H +#define LIB_REG_PMC_H + +#include <reg/regdefs.h> + +#define PMC_LVDSC1 REG_8(0x4007D000) /* Low Voltage Detect Status And Control 1 register */ +#define LVDSC1_LVDF 7 /* Low-Voltage Detect Flag */ +#define LVDSC1_LVDACK 6 /* Low-Voltage Detect Acknowledge */ +#define LVDSC1_LVDIE 5 /* Low-Voltage Detect Interrupt Enable */ +#define LVDSC1_LVDRE 4 /* Low-Voltage Detect Reset Enable */ +#define LVDSC1_LVDV 0 /* Low-Voltage Detect Voltage Select */ +#define LVDSC1_LVDV_M (uint8_t)(BITS(2) << LVDSC1_LVDV) + +#define PMC_LVDSC2 REG_8(0x4007D001) /* Low Voltage Detect Status And Control 2 register */ +#define LVDSC2_LVWF 7 /* Low-Voltage Warning Flag */ +#define LVDSC2_LVWACK 6 /* Low-Voltage Warning Acknowledge */ +#define LVDSC2_LVWIE 5 /* Low-Voltage Warning Interrupt Enable */ +#define LVDSC2_LVWV 0 /* Low-Voltage Warning Voltage Select */ +#define LVDSC2_LVWV_M (uint8_t)(BITS(2) << LVDSC2_LVWV) + +#define PMC_REGSC REG_8(0x4007D002) /* Regulator Status And Control register */ +#define REGSC_BGEN 4 /* Bandgap Enable In VLPx Operation */ +#define REGSC_ACKISO 3 /* Acknowledge Isolation */ +#define REGSC_REGONS 2 /* Regulator In Run Regulation Status */ +#define REGSC_BGBE 1 /* Bandgap Buffer Enable */ + +#endif /* LIB_REG_PMC_H */ diff --git a/lib/reg/port.h b/lib/reg/port.h new file mode 100644 index 0000000..76b8d9c --- /dev/null +++ b/lib/reg/port.h @@ -0,0 +1,42 @@ +#ifndef LIB_REG_PORT_H +#define LIB_REG_PORT_H + +#include <reg/regdefs.h> + +#define PORTA_PCR(n) REG_32(0x40049000 + 4 * (n)) /* Pin Control Register n */ +#define PORTB_PCR(n) REG_32(0x4004A000 + 4 * (n)) /* Pin Control Register n */ +#define PORTC_PCR(n) REG_32(0x4004B000 + 4 * (n)) /* Pin Control Register n */ +#define PORTD_PCR(n) REG_32(0x4004C000 + 4 * (n)) /* Pin Control Register n */ +#define PORTE_PCR(n) REG_32(0x4004D000 + 4 * (n)) /* Pin Control Register n */ +#define PCR_ISF 24 /* Interrupt Status Flag */ +#define PCR_IRQC 16 /* Interrupt Configuration */ +#define PCR_IRQC_M (uint32_t)(BITS(4) << PCR_IRQC) +#define PCR_LK 15 /* Lock Register */ +#define PCR_MUX 8 /* Pin Mux Control */ +#define PCR_MUX_M (uint32_t)(BITS(3) << PCR_MUX) +#define PCR_DSE 6 /* Drive Strength Enable */ +#define PCR_ODE 5 /* Open Drain Enable */ +#define PCR_PFE 4 /* Passive Filter Enable */ +#define PCR_SRE 2 /* Slew Rate Enable */ +#define PCR_PE 1 /* Pull Enable */ +#define PCR_PS 0 /* Pull Select */ + +#define PORTA_GPCLR REG_32(0x40049080) /* Global Pin Control Low Register */ +#define PORTB_GPCLR REG_32(0x4004A080) /* Global Pin Control Low Register */ +#define PORTC_GPCLR REG_32(0x4004B080) /* Global Pin Control Low Register */ +#define PORTD_GPCLR REG_32(0x4004C080) /* Global Pin Control Low Register */ +#define PORTE_GPCLR REG_32(0x4004D080) /* Global Pin Control Low Register */ + +#define PORTA_GPCHR REG_32(0x40049084) /* Global Pin Control High Register */ +#define PORTB_GPCHR REG_32(0x4004A084) /* Global Pin Control High Register */ +#define PORTC_GPCHR REG_32(0x4004B084) /* Global Pin Control High Register */ +#define PORTD_GPCHR REG_32(0x4004C084) /* Global Pin Control High Register */ +#define PORTE_GPCHR REG_32(0x4004D084) /* Global Pin Control High Register */ + +#define PORTA_ISFR REG_32(0x400490A0) /* Interrupt Status Flag Register */ +#define PORTB_ISFR REG_32(0x4004A0A0) /* Interrupt Status Flag Register */ +#define PORTC_ISFR REG_32(0x4004B0A0) /* Interrupt Status Flag Register */ +#define PORTD_ISFR REG_32(0x4004C0A0) /* Interrupt Status Flag Register */ +#define PORTE_ISFR REG_32(0x4004D0A0) /* Interrupt Status Flag Register */ + +#endif /* LIB_REG_PORT_H */ diff --git a/lib/reg/regdefs.h b/lib/reg/regdefs.h new file mode 100644 index 0000000..6a38c76 --- /dev/null +++ b/lib/reg/regdefs.h @@ -0,0 +1,25 @@ +#ifndef LIB_REG_REGDEFS_H +#define LIB_REG_REGDEFS_H + +#include <stdint.h> + +#define REG_8(a) (*(volatile uint8_t *)(a)) +#define REG_16(a) (*(volatile uint16_t *)(a)) +#define REG_32(a) (*(volatile uint32_t *)(a)) + +#define BV(b) (1 << (b)) +#define IS_BIT_SET(reg, bit) (!!((reg) & BV(bit))) +#define WAIT_BIT_UNSET(reg, bit) do { } while (IS_BIT_SET(reg, bit)) +#define WAIT_BIT_SET(reg, bit) do { } while (!IS_BIT_SET(reg, bit)) + +#define SET_BIT(reg, bit) ((reg) |= BV(bit)) +#define UNSET_BIT(reg, bit) ((reg) &= ~BV(bit)) + +#define GET_BIT(reg, bit) !!((reg) & BV(bit)) +#define GET_BITS(reg, offset) (((reg) & (offset ## _M)) >> (offset)) + +#define SET_MASKED(reg, mask, bits) ((reg) = ((reg) & ~(mask)) | ((bits) & (mask))) + +#define BITS(n) (0xffffffff >> (32 - (n))) + +#endif /* LIB_REG_REGDEFS_H */ diff --git a/lib/reg/sim.h b/lib/reg/sim.h new file mode 100644 index 0000000..93839e8 --- /dev/null +++ b/lib/reg/sim.h @@ -0,0 +1,70 @@ +#ifndef LIB_REG_SIM_H +#define LIB_REG_SIM_H + +#include <reg/regdefs.h> + +#define SIM_SOPT REG_32(0x140047000) /* System Options Register 1 */ +#define SIM_SOPT1CFG REG_32(0x40047004) /* SOPT1 Configuration Register */ + +#define SIM_SOPT2 REG_32(0x40048004) /* System Options Register 2 */ +#define SOPT2_USBSRC 18 /* USB clock source select */ +#define SOPT2_PLLFLLSEL 16 /* PLL/FLL clock select */ +#define SOPT2_TRACECLKSEL 12 /* Debug trace clock select */ +#define SOPT2_PTD7PAD 11 /* PTD7 pad drive strength */ +#define SOPT2_CLKOUTSEL 5 /* CLKOUT select */ +#define SOPT2_CLKOUTSEL_M (BITS(3) << SOPT2_CLKOUTSEL) +#define SOPT2_RTCCLKOUTSEL 4 /* RTC clock out select */ + +#define SIM_SOPT4 REG_32(0x4004800C) /* System Options Register 4 */ +#define SIM_SOPT5 REG_32(0x40048010) /* System Options Register 5 */ +#define SIM_SOPT7 REG_32(0x40048018) /* System Options Register 7 */ +#define SIM_SDID REG_32(0x40048024) /* System Device Identification Register */ +#define SIM_SCGC1 REG_32(0x40048028) /* System Clock Gating Control Register 1 */ +#define SIM_SCGC2 REG_32(0x4004802C) /* System Clock Gating Control Register 2 */ +#define SIM_SCGC3 REG_32(0x40048030) /* System Clock Gating Control Register 3 */ + +#define SIM_SCGC4 REG_32(0x40048034) /* System Clock Gating Control Register 4 */ +#define SCGC4_VREF 20 /* VREF Clock Gate Control */ +#define SCGC4_CMP 19 /* Comparator Clock Gate Control */ +#define SCGC4_USBOTG 18 /* USB Clock Gate Control */ +#define SCGC4_UART2 12 /* UART2 Clock Gate Control */ +#define SCGC4_UART1 11 /* UART1 Clock Gate Control */ +#define SCGC4_UART0 10 /* UART0 Clock Gate Control */ +#define SCGC4_I2C1 7 /* I2C1 Clock Gate Control */ +#define SCGC4_I2C0 6 /* I2C0 Clock Gate Control */ +#define SCGC4_CMT 2 /* CMT Clock Gate Control */ +#define SCGC4_EWM 1 /* EWM Clock Gate Control */ + +#define SIM_SCGC5 REG_32(0x40048038) /* System Clock Gating Control Register 5 */ +#define SCGC5_PORTE 13 /* Port E Clock Gate Control */ +#define SCGC5_PORTD 12 /* Port D Clock Gate Control */ +#define SCGC5_PORTC 11 /* Port C Clock Gate Control */ +#define SCGC5_PORTB 10 /* Port B Clock Gate Control */ +#define SCGC5_PORTA 9 /* Port A Clock Gate Control */ +#define SCGC5_TSI 5 /* TSI Clock Gate Control */ +#define SCGC5_LPTIMER 0 /* Low Power Timer Access Control */ + +#define SIM_SCGC6 REG_32(0x4004803C) /* System Clock Gating Control Register 6 */ +#define SIM_SCGC7 REG_32(0x40048040) /* System Clock Gating Control Register 7 */ + +#define SIM_CLKDIV1 REG_32(0x40048044) /* System Clock Divider Register 1 */ +#define CLKDIV1_OUTDIV1 28 /* Clock 1 output divider value */ +#define CLKDIV1_OUTDIV1_M (uint32_t)(BITS(4) << CLKDIV1_OUTDIV1) +#define CLKDIV1_OUTDIV2 24 /* Clock 2 output divider value */ +#define CLKDIV1_OUTDIV2_M (uint32_t)(BITS(4) << CLKDIV1_OUTDIV2) +#define CLKDIV1_OUTDIV4 16 /* Clock 4 output divider value */ +#define CLKDIV1_OUTDIV4_M (uint32_t)(BITS(4) << CLKDIV1_OUTDIV4) + +#define SIM_CLKDIV2 REG_32(0x40048048) /* System Clock Divider Register 2 */ +#define CLKDIV2_USBDIV 1 /* USB clock divider divisor */ +#define CLKDIV2_USBDIV_M (uint32_t)(BITS(3) << CLKDIV2_USBDIV) +#define CLKDIV2_USBFRAC 0 /* USB clock divider fraction */ + +#define SIM_FCFG1 REG_32(0x4004804C) /* Flash Configuration Register 1 */ +#define SIM_FCFG2 REG_32(0x40048050) /* Flash Configuration Register 2 */ +#define SIM_UIDH REG_32(0x40048054) /* Unique Identification Register High */ +#define SIM_UIDMH REG_32(0x40048058) /* Unique Identification Register Mid-High */ +#define SIM_UIDML REG_32(0x4004805C) /* Unique Identification Register Mid Low */ +#define SIM_UIDL REG_32(0x40048060) /* Unique Identification Register Low */ + +#endif /* LIB_REG_SIM_H */ diff --git a/lib/reg/uart.h b/lib/reg/uart.h new file mode 100644 index 0000000..a23d2f6 --- /dev/null +++ b/lib/reg/uart.h @@ -0,0 +1,8 @@ +#ifndef LIB_REG_UART_H +#define LIB_REG_UART_H + +#include "regdefs.h" + + + +#endif /* LIB_REG_UART_H */ diff --git a/lib/reg/usbotg.h b/lib/reg/usbotg.h new file mode 100644 index 0000000..56f00aa --- /dev/null +++ b/lib/reg/usbotg.h @@ -0,0 +1,202 @@ +#ifndef LIB_REG_USBOTG_H +#define LIB_REG_USBOTG_H + +#include "regdefs.h" + +#define USB0_PERID REG_8(0x40072000) /* Peripheral ID register */ +#define PERID_ID 0 /* Peripheral Identification */ +#define PERID_ID_M (uint8_t)(0x3F) + +#define USB0_IDCOMP REG_8(0x40072004) /* Peripheral ID Complement register */ +#define IDCOMP_NID 0 /* Ones complement of peripheral identification bits. */ +#define IDCOMP_NID_M (uint8_t)(0x3F) + +#define USB0_REV REG_8(0x40072008) /* Peripheral Revision register */ +#define REV_REV 0 /* Revision */ +#define REV_REV_M (uint8_t)(0xFF) + +#define USB0_ADDINFO REG_8(0x4007200C) /* Peripheral Additional Info register */ +#define ADDINFO_IRQNUM 3 /* Assigned Interrupt Request Number. */ +#define ADDINFO_IRQNUM_M (uint8_t)(BITS(5) << ADDINFO_IRQNUM) +#define ADDINFO_IEHOST 0 /* Set if SIE is in host mode. */ + +#define USB0_OTGISTAT REG_8(0x40072010) /* OTG Interrupt Status register */ +#define OTGISTAT_IDCHG 7 /* Set on change in the ID Signal from the USB connector. */ +#define OTGISTAT_ONEMSEC 6 /* Set on 1 ms timer expire. */ +#define OTGISTAT_LINE_STATE_CHG 5 /* Set when USB line state changes. */ +#define OTGISTAT_SESSVLDCHG 3 +#define OTGISTAT_B_SESS_CHG 2 +#define OTGISTAT_AVBUSCHG 0 + +#define USB0_OTGICR REG_8(0x40072014) /* OTG Interrupt Control Register */ +#define OTGICR_IDEN 7 /* ID Interrupt Enable */ +#define OTGICR_ONEMSECEN 6 /* One Millisecond Interrupt Enable */ +#define OTGICR_LINESTATEEN 5 /* Line State Change Interrupt Enable */ +#define OTGICR_SESSVLDEN 3 /* Session Valid Interrupt Enable */ +#define OTGICR_BSESSEN 2 /* B Session END Interrupt Enable */ +#define OTGICR_AVBUSEN 0 /* A VBUS Valid Interrupt Enable */ + +#define USB0_OTGSTAT REG_8(0x40072018) /* OTG Status register */ +#define OTGSTAT_ID 7 +#define OTGSTAT_ONEMSECEN 6 +#define OTGSTAT_LINESTATESTABLE 5 +#define OTGSTAT_SESS_VLD 3 +#define OTGSTAT_BSESSEND 2 +#define OTGSTAT_AVBUSVLD 0 + +#define USB0_OTGCTL REG_8(0x4007201C) /* OTG Control register */ +#define OTGCTL_DPHIGH 7 /* D+ Data Line pullup resistor enable */ +#define OTGCTL_DPLOW 5 /* D+ Data Line pull-down resistor enable */ +#define OTGCTL_DMLOW 4 /* D– Data Line pull-down resistor enable */ +#define OTGCTL_OTGEN 2 /* On-The-Go pullup/pulldown resistor enable */ + +#define USB0_ISTAT REG_8(0x40072080) /* Interrupt Status register */ +#define ISTAT_STALL 7 /* Stall Interrupt */ +#define ISTAT_ATTACH 6 /* Attach Interrupt */ +#define ISTAT_RESUME 5 +#define ISTAT_SLEEP 4 +#define ISTAT_TOKDNE 3 +#define ISTAT_SOFTOK 2 +#define ISTAT_ERROR 1 +#define ISTAT_USBRST 0 + +#define USB0_INTEN REG_8(0x40072084) /* Interrupt Enable register */ +#define INTEN_STALLEN 7 /* STALL Interrupt Enable */ +#define INTEN_ATTACHEN 6 /* ATTACH Interrupt Enable */ +#define INTEN_RESUMEEN 5 /* RESUME Interrupt Enable */ +#define INTEN_SLEEPEN 4 /* SLEEP Interrupt Enable */ +#define INTEN_TOKDNEEN 3 /* TOKDNE Interrupt Enable */ +#define INTEN_SOFTOKEN 2 /* SOFTOK Interrupt Enable */ +#define INTEN_ERROREN 1 /* ERROR Interrupt Enable */ +#define INTEN_USBRSTEN 0 /* USBRST Interrupt Enable */ + +#define USB0_ERRSTAT REG_8(0x40072088) /* Error Interrupt Status register */ +#define ERRSTAT_BTSERR 7 +#define ERRSTAT_DMAERR 5 +#define ERRSTAT_BTOERR 4 +#define ERRSTAT_DFN8 3 +#define ERRSTAT_CRC16 2 +#define ERRSTAT_CRC5EOF 1 +#define ERRSTAT_PIDERR 0 + +#define USB0_ERREN REG_8(0x4007208C) /* Error Interrupt Enable register */ +#define ERREN_BTSERREN 7 /* BTSERR Interrupt Enable */ +#define ERREN_DMAERREN 5 /* DMAERR Interrupt Enable */ +#define ERREN_BTOERREN 4 /* BTOERR Interrupt Enable */ +#define ERREN_DFN8EN 3 /* DFN8 Interrupt Enable */ +#define ERREN_CRC16EN 2 /* CRC16 Interrupt Enable */ +#define ERREN_CRC5EOFEN 1 /* CRC5EOF Interrupt Enable */ +#define ERREN_PIDERREN 0 /* PIDERR Interrupt Enable */ + +#define USB0_STAT REG_8(0x40072090) /* Status register */ +#define STAT_ENDP 4 +#define STAT_ENDP_M (uint8_t)(BITS(4) << STAT_ENDP) +#define STAT_TX 3 /* Transmit Indicator */ +#define STAT_ODD 2 + +#define USB0_CTL REG_8(0x40072094) /* Control register */ +#define CTL_JSTATE 7 /* Live USB differential receiver JSTATE signal */ +#define CTL_SE0 6 /* Live USB Single Ended Zero signal */ +#define CTL_TXSUSPENDTOKENBUSY 5 +#define CTL_RESET 4 +#define CTL_HOSTMODEEN 3 +#define CTL_RESUME 2 +#define CTL_ODDRST 1 +#define CTL_USBENSOFEN 0 /* USB Enable */ + +#define USB0_ADDR REG_8(0x40072098) /* Address register */ +#define ADDR_LSEN 7 +#define ADDR_ADDR 0 +#define ADDR_ADDR_M (uint8_t)(BITS(7)) + +#define USB0_BDTPAGE1 REG_8(0x4007209C) /* BDT Page Register 1 */ + +#define USB0_FRMNUML REG_8(0x400720A0) /* Frame Number Register Low */ +#define FRMNUML_FRM 0 +#define FRMNUML_FRM_M (uint8_t)(BITS(8) << FRMNUML_FRM) + +#define USB0_FRMNUMH REG_8(0x400720A4) /* Frame Number Register High */ +#define FRMNUMH_FRM 0 +#define FRMNUMH_FRM_M (uint8_t)(BITS(3) << FRMNUMH_FRM_M) + +#define USB0_TOKEN REG_8(0x400720A8) /* Token register */ +#define TOKEN_TOKENPID 4 +#define TOKEN_TOKENPID_M (uint8_t)(BITS(4) << TOKEN_TOKENPID) +#define TOKEN_TOKENENDPT 0 +#define TOKEN_TOKENENDPT_M (uint8_t)(BITS(4) << TOKEN_TOKENENDPT) + +#define USB0_SOFTHLD REG_8(0x400720AC) /* SOF Threshold Register */ +#define SOFTHLD_CNT 0 +#define SOFTHLD_CNT_M (uint8_t)(BITS(8) << SOFTHLD_CNT) + +#define USB0_BDTPAGE2 REG_8(0x400720B0) /* BDT Page Register 2 */ +#define BDTPAGE2_BDTBA 0 +#define BDTPAGE2_BDTBA_M (uint8_t)(BITS(8) << BDTPAGE2_BDTBA) + +#define USB0_BDTPAGE3 REG_8(0x400720B4) /* BDT Page Register 3 */ +#define BDTPAGE3_BDTBA 0 +#define BDTPAGE3_BDTBA_M (uint8_t)(BITS(8) << BDTPAGE3_BDTBA) + +#define USB0_ENDPT(n) REG_8(0x400720C0 + 4 * (n)) /* Endpoint Control register */ +#define ENDPT_HOSTWOHUB 7 +#define ENDPT_RETRYDIS 6 +#define ENDPT_EPCTLDIS 4 +#define ENDPT_EPRXEN 3 +#define ENDPT_EPTXEN 2 +#define ENDPT_EPSTALL 1 +#define ENDPT_EPHSHK 0 + +#define USB0_USBCTRL REG_8(0x40072100) /* USB Control register */ +#define USBCTRL_SUSP 7 /* Places the USB transceiver into the suspend state. */ +#define USBCTRL_PDE 6 /* Enables the weak pulldowns on the USB transceiver. */ + +#define USB0_OBSERVE REG_8(0x40072104) /* USB OTG Observe register */ +#define OBSERVE_DPPU 7 /* Provides observability of the D+ Pullup */ +#define OBSERVE_DPPD 6 /* Provides observability of the D+ Pulldown */ +#define OBSERVE_DMPD 4 /* Provides observability of the D- Pulldown */ + +#define USB0_CONTROL REG_8(0x40072108) /* USB OTG Control register */ +#define CONTROL_DPPULLUPNONOTG 4 /* DP Pullup in non-OTG device mode state */ + +#define USB0_USBTRC0 REG_8(0x4007210C) /* USB Transceiver Control Register 0 */ +#define USBTRC0_USBRESET 7 /* USB Reset */ +#define USBTRC0_USBRESMEN 5 /* Asynchronous Resume Interrupt Enable */ +#define USBTRC0_SYNC_DET 1 /* Synchronous USB Interrupt Detect */ +#define USBTRC0_USB_RESUME_INT 0 /* USB Asynchronous Interrupt */ + +#define USB0_USBFRMADJUST REG_8(0x40072114) /* Frame Adjust Register */ +#define USBFRMADJUST_ADJ 0 +#define USBFRMADJUST_ADJ_M (uint8_t)(BITS(8) << USBFRMADJUST_ADJ) + +__attribute__ ((packed)) +struct usb0_bd { + uint32_t desc; + void *addr; +}; +//#define USB0_BD(desc, addr) (struct usb0_bd){(desc), (addr)} +#define USB0_BD_INIT(size, data01) ((size) << BD_BC | BV(BD_OWN) | \ + ((data01) & 1) << BD_DATA01 | BV(BD_DTS)) +#define BD_BC 16 /* Byte Count */ +#define BD_BC_M (uint32_t)(BITS(10) << BC) +#define BD_OWN 7 +#define BD_DATA01 6 +#define BD_KEEP 5 +#define BD_NINC 4 +#define BD_DTS 3 +#define BD_BDT_STALL 2 +#define BD_TOK_PID 2 +#define BD_TOK_PID_M (uint32_t)(BITS(4) << BD_TOK_PID) + +#define BD_TOK_PID_OUT 0x1 +#define BD_TOK_PID_IN 0x9 +#define BD_TOK_PID_SETUP 0xd + +#define BD_TOK_PID_DATA0 0x3 +#define BD_TOK_PID_DATA1 0xb +#define BD_TOK_PID_ACK 0x2 +#define BD_TOK_PID_STALL 0xe +#define BD_TOK_PID_NAK 0xa +#define BD_TOK_PID_TIMEOUT 0x0 +#define BD_TOK_PID_ERROR 0xf + +#endif /* LIB_REG_USBOTG_H */ diff --git a/lib/reg/wdog.h b/lib/reg/wdog.h new file mode 100644 index 0000000..a2596c8 --- /dev/null +++ b/lib/reg/wdog.h @@ -0,0 +1,37 @@ +#ifndef LIB_REG_WDOG_H +#define LIB_REG_WDOG_H + +#include <reg/regdefs.h> + +#define WDOG_STCTRLH REG_16(0x40052000) /* Watchdog Status and Control Register High */ +#define STCTRLH_DISTESTWDOG 14 /* Functional test mode disable */ +#define STCTRLH_BYTESEL 12 /* Byte test mode byte selector */ +#define STCTRLH_BYTESEL_M (uint16_t)(BITS(2) << STCTRLH_BYTESEL) +#define STCTRLH_TESTSEL 11 /* Functional test mode test selector */ +#define STCTRLH_TESTWDOG 10 /* Functional test mode enable */ +#define STCTRLH_WAITEN 7 /* Wait mode WDOG enable */ +#define STCTRLH_STOPEN 6 /* Stop mode WDOG enable */ +#define STCTRLH_DBGEN 5 /* Debug mode WDOG enable */ +#define STCTRLH_ALLOWUPDATE 4 /* Allow further updates to write-once registers */ +#define STCTRLH_WINEN 3 /* Windowing mode enable */ +#define STCTRLH_IRQRSTEN 2 /* Debug breadcrumbs feature enable */ +#define STCTRLH_CLKSRC 1 /* Clock source selector */ +#define STCTRLH_WDOGEN 0 /* WDOG enable */ + +#define WDOG_STCTRLL REG_16(0x40052002) /* Watchdog Status and Control Register Low */ +#define WDOG_TOVALH REG_16(0x40052004) /* Watchdog Time-out Value Register High */ +#define WDOG_TOVALL REG_16(0x40052006) /* Watchdog Time-out Value Register Low */ +#define WDOG_WINH REG_16(0x40052008) /* Watchdog Window Register High */ +#define WDOG_WINL REG_16(0x4005200A) /* Watchdog Window Register Low */ +#define WDOG_REFRESH REG_16(0x4005200C) /* Watchdog Refresh register */ + +#define WDOG_UNLOCK REG_16(0x4005200E) /* Watchdog Unlock Register */ +#define WDOG_UNLOCK_S1 0xC520 /* Unlock Sequence 1/2 */ +#define WDOG_UNLOCK_S2 0xD928 /* Unlock Sequence 2/2 */ + +#define WDOG_TMROUTH REG_16(0x40052010) /* Watchdog Timer Output Register High */ +#define WDOG_TMROUTL REG_16(0x40052012) /* Watchdog Timer Output Register Low */ +#define WDOG_RSTCNT REG_16(0x40052014) /* Watchdog Reset Count register */ +#define WDOG_PRESC REG_16(0x40052016) /* Watchdog Prescaler register */ + +#endif /* LIB_REG_WDOG_H */ diff --git a/lib/string.c b/lib/string.c new file mode 100644 index 0000000..25935b3 --- /dev/null +++ b/lib/string.c @@ -0,0 +1,38 @@ +#include <string.h> +#include <stddef.h> + +void *memcpy(void * restrict _dest, const void * restrict _src, size_t n) +{ + unsigned char *dest = _dest; + const unsigned char *src = _src; + + for (size_t i = 0; i < n; i++) + dest[i] = src[i]; + + return dest; +} + +void *memmove(void *_dest, const void *_src, size_t n) +{ + unsigned char *dest = _dest; + const unsigned char *src = _src; + + if (_src < _dest) { + for (size_t i = 0; i < n; i++) + dest[i] = src[i]; + } else { + for (size_t i = n; i > 0; i++) + dest[i - 1] = src[i - 1]; + } + + return dest; +} + +void *memset(void *_s, int _c, size_t n) +{ + unsigned char *s = _s, c = (unsigned char)_c; + for (size_t i = 0; i < n; i++) + s[i] = c; + + return _s; +} diff --git a/lib/string.h b/lib/string.h new file mode 100644 index 0000000..9c204dd --- /dev/null +++ b/lib/string.h @@ -0,0 +1,10 @@ +#ifndef LIB_STRING_H +#define LIB_STRING_H + +#include <stddef.h> + +void *memcpy(void * restrict dest, const void * restrict src, size_t n); +void *memmove(void *dest, const void *src, size_t n); +void *memset(void *s, int c, size_t n); + +#endif /* LIB_STRING_H */ |