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/* Port control and interrupts (PORT) (Chapter 11) */
#ifndef MK20DX256_REG_PORT_H
#define MK20DX256_REG_PORT_H
#include <reg/regdefs.h>
// Pin Control Register n
#define PORTA_PCR(n) REG_32(0x40049000 + 4 * (n))
// Pin Control Register n
#define PORTB_PCR(n) REG_32(0x4004A000 + 4 * (n))
// Pin Control Register n
#define PORTC_PCR(n) REG_32(0x4004B000 + 4 * (n))
// Pin Control Register n
#define PORTD_PCR(n) REG_32(0x4004C000 + 4 * (n))
// Pin Control Register n
#define PORTE_PCR(n) REG_32(0x4004D000 + 4 * (n))
enum {
PCR_ISF = 24, // Interrupt Status Flag
PCR_IRQC = 16, // Interrupt Configuration
PCR_IRQC_M = REG_32_M(PCR_IRQC, 4),
PCR_LK = 15, // Lock Register
PCR_MUX = 8, // Pin Mux Control
PCR_MUX_M = REG_32_M(PCR_MUX, 3),
PCR_DSE = 6, // Drive Strength Enable
PCR_ODE = 5, // Open Drain Enable
PCR_PFE = 4, // Passive Filter Enable
PCR_SRE = 2, // Slew Rate Enable
PCR_PE = 1, // Pull Enable
PCR_PS = 0, // Pull Select
};
// Global Pin Control Low Register
#define PORTA_GPCLR REG_32(0x40049080)
// Global Pin Control Low Register
#define PORTB_GPCLR REG_32(0x4004A080)
// Global Pin Control Low Register
#define PORTC_GPCLR REG_32(0x4004B080)
// Global Pin Control Low Register
#define PORTD_GPCLR REG_32(0x4004C080)
// Global Pin Control Low Register
#define PORTE_GPCLR REG_32(0x4004D080)
// Global Pin Control High Register
#define PORTA_GPCHR REG_32(0x40049084)
// Global Pin Control High Register
#define PORTB_GPCHR REG_32(0x4004A084)
// Global Pin Control High Register
#define PORTC_GPCHR REG_32(0x4004B084)
// Global Pin Control High Register
#define PORTD_GPCHR REG_32(0x4004C084)
// Global Pin Control High Register
#define PORTE_GPCHR REG_32(0x4004D084)
// Interrupt Status Flag Register
#define PORTA_ISFR REG_32(0x400490A0)
// Interrupt Status Flag Register
#define PORTB_ISFR REG_32(0x4004A0A0)
// Interrupt Status Flag Register
#define PORTC_ISFR REG_32(0x4004B0A0)
// Interrupt Status Flag Register
#define PORTD_ISFR REG_32(0x4004C0A0)
// Interrupt Status Flag Register
#define PORTE_ISFR REG_32(0x4004D0A0)
#endif /* MK20DX256_REG_PORT_H */
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