diff options
Diffstat (limited to 'reg/mcg.h')
| -rw-r--r-- | reg/mcg.h | 12 |
1 files changed, 6 insertions, 6 deletions
@@ -5,9 +5,9 @@ #define MCG_C1 REG_8(0x40064000) /* MCG Control 1 Register */ #define C1_CLKS 6 /* Clock Source Select */ -#define C1_CLKS_M (uint8_t)(BITS(2) << C1_CLKS) +#define C1_CLKS_M REG_8_M(C1_CLKS, 2) #define C1_FRDIV 3 /* FLL External Reference Divider */ -#define C1_FRDIV_M (uint8_t)(BITS(3) << C1_FRDIV) +#define C1_FRDIV_M REG_8_M(C1_FRDIV, 3) #define C1_IREFS 2 /* Internal Reference Select */ #define C1_IRCLKEN 1 /* Internal Reference Clock Enable */ #define C1_IREFSTEN 0 /* Internal Reference Stop Enable */ @@ -15,7 +15,7 @@ #define MCG_C2 REG_8(0x40064001) /* MCG Control 2 Register */ #define C2_LOCRE0 7 /* Loss of Clock Reset Enable */ #define C2_RANGE0 4 /* Frequency Range Select */ -#define C2_RANGE0_M (uint8_t)(BITS(2) << C2_RANGE0) +#define C2_RANGE0_M REG_8_M(C2_RANGE0, 2) #define C2_HGO0 3 /* High Gain Oscillator Select */ #define C2_EREFS0 2 /* External Reference Select */ #define C2_LP 1 /* Low Power Select */ @@ -28,14 +28,14 @@ #define C5_PLLCLKEN0 6 /* PLL Clock Enable */ #define C5_PLLSTEN0 5 /* PLL Stop Enable */ #define C5_PRDIV0 0 /* PLL External Reference Divider */ -#define C5_PRDIV0_M (uint8_t)(BITS(5) << C5_PRDIV0) +#define C5_PRDIV0_M REG_8_M(C5_PRDIV0, 5) #define MCG_C6 REG_8(0x40064005) /* MCG Control 6 Register */ #define C6_LOLIE0 7 /* Loss of Lock Interrrupt Enable */ #define C6_PLLS 6 /* PLL Select */ #define C6_CME0 5 /* Clock Monitor Enable */ #define C6_VDIV0 0 /* VCO 0 Divider */ -#define C6_VDIV0_M (uint8_t)(BITS(5) << C6_VDIV0) +#define C6_VDIV0_M REG_8_M(C6_VDIV0, 5) #define MCG_S REG_8(0x40064006) /* MCG Status Register */ #define S_LOLS0 7 /* Loss of Lock Status */ @@ -43,7 +43,7 @@ #define S_PLLST 5 /* PLL Select Status */ #define S_IREFST 4 /* Internal Reference Status */ #define S_CLKST 2 /* Clock Mode Status */ -#define S_CLKST_M (uint8_t)(BITS(2) << S_CLKST) +#define S_CLKST_M REG_8_M(S_CLKST, 2) #define S_OSCINIT0 1 /* OSC Initialization */ #define S_IRCST 0 /* Internal Reference Clock Status */ |