blob: 68949ce70818f2cee70fbd61b62d8730a133b8b9 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
|
// Main starting point for SAM3/SAM4 boards
//
// Copyright (C) 2016-2018 Kevin O'Connor <kevin@koconnor.net>
//
// This file may be distributed under the terms of the GNU GPLv3 license.
#include "command.h" // DECL_CONSTANT
#include "internal.h" // WDT
#include "sched.h" // sched_main
DECL_CONSTANT(MCU, CONFIG_MCU);
/****************************************************************
* watchdog handler
****************************************************************/
void
watchdog_reset(void)
{
WDT->WDT_CR = 0xA5000001;
}
DECL_TASK(watchdog_reset);
void
watchdog_init(void)
{
uint32_t timeout = 500 * 32768 / 128 / 1000; // 500ms timeout
WDT->WDT_MR = WDT_MR_WDRSTEN | WDT_MR_WDV(timeout) | WDT_MR_WDD(timeout);
}
DECL_INIT(watchdog_init);
/****************************************************************
* misc functions
****************************************************************/
// Check if a peripheral clock has been enabled
int
is_enabled_pclock(uint32_t id)
{
if (id < 32)
return !!(PMC->PMC_PCSR0 & (1 << id));
else
return !!(PMC->PMC_PCSR1 & (1 << (id - 32)));
}
// Enable a peripheral clock
void
enable_pclock(uint32_t id)
{
if (id < 32)
PMC->PMC_PCER0 = 1 << id;
else
PMC->PMC_PCER1 = 1 << (id - 32);
}
void
command_reset(uint32_t *args)
{
NVIC_SystemReset();
}
DECL_COMMAND_FLAGS(command_reset, HF_IN_SHUTDOWN, "reset");
// Main entry point
int
main(void)
{
SystemInit();
sched_main();
return 0;
}
|
