blob: 3433f6dc4e49b39d701224a3dba5926271e9f9fd (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
|
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : PSM
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_PSM_H
#define _HARDWARE_REGS_PSM_H
// =============================================================================
// Register : PSM_FRCE_ON
// Description : Force block out of reset (i.e. power it on)
#define PSM_FRCE_ON_OFFSET _u(0x00000000)
#define PSM_FRCE_ON_BITS _u(0x0001ffff)
#define PSM_FRCE_ON_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_PROC1
#define PSM_FRCE_ON_PROC1_RESET _u(0x0)
#define PSM_FRCE_ON_PROC1_BITS _u(0x00010000)
#define PSM_FRCE_ON_PROC1_MSB _u(16)
#define PSM_FRCE_ON_PROC1_LSB _u(16)
#define PSM_FRCE_ON_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_PROC0
#define PSM_FRCE_ON_PROC0_RESET _u(0x0)
#define PSM_FRCE_ON_PROC0_BITS _u(0x00008000)
#define PSM_FRCE_ON_PROC0_MSB _u(15)
#define PSM_FRCE_ON_PROC0_LSB _u(15)
#define PSM_FRCE_ON_PROC0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SIO
#define PSM_FRCE_ON_SIO_RESET _u(0x0)
#define PSM_FRCE_ON_SIO_BITS _u(0x00004000)
#define PSM_FRCE_ON_SIO_MSB _u(14)
#define PSM_FRCE_ON_SIO_LSB _u(14)
#define PSM_FRCE_ON_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_VREG_AND_CHIP_RESET
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_RESET _u(0x0)
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_BITS _u(0x00002000)
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_MSB _u(13)
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_LSB _u(13)
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_XIP
#define PSM_FRCE_ON_XIP_RESET _u(0x0)
#define PSM_FRCE_ON_XIP_BITS _u(0x00001000)
#define PSM_FRCE_ON_XIP_MSB _u(12)
#define PSM_FRCE_ON_XIP_LSB _u(12)
#define PSM_FRCE_ON_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM5
#define PSM_FRCE_ON_SRAM5_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM5_BITS _u(0x00000800)
#define PSM_FRCE_ON_SRAM5_MSB _u(11)
#define PSM_FRCE_ON_SRAM5_LSB _u(11)
#define PSM_FRCE_ON_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM4
#define PSM_FRCE_ON_SRAM4_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM4_BITS _u(0x00000400)
#define PSM_FRCE_ON_SRAM4_MSB _u(10)
#define PSM_FRCE_ON_SRAM4_LSB _u(10)
#define PSM_FRCE_ON_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM3
#define PSM_FRCE_ON_SRAM3_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM3_BITS _u(0x00000200)
#define PSM_FRCE_ON_SRAM3_MSB _u(9)
#define PSM_FRCE_ON_SRAM3_LSB _u(9)
#define PSM_FRCE_ON_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM2
#define PSM_FRCE_ON_SRAM2_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM2_BITS _u(0x00000100)
#define PSM_FRCE_ON_SRAM2_MSB _u(8)
#define PSM_FRCE_ON_SRAM2_LSB _u(8)
#define PSM_FRCE_ON_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM1
#define PSM_FRCE_ON_SRAM1_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM1_BITS _u(0x00000080)
#define PSM_FRCE_ON_SRAM1_MSB _u(7)
#define PSM_FRCE_ON_SRAM1_LSB _u(7)
#define PSM_FRCE_ON_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM0
#define PSM_FRCE_ON_SRAM0_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM0_BITS _u(0x00000040)
#define PSM_FRCE_ON_SRAM0_MSB _u(6)
#define PSM_FRCE_ON_SRAM0_LSB _u(6)
#define PSM_FRCE_ON_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_ROM
#define PSM_FRCE_ON_ROM_RESET _u(0x0)
#define PSM_FRCE_ON_ROM_BITS _u(0x00000020)
#define PSM_FRCE_ON_ROM_MSB _u(5)
#define PSM_FRCE_ON_ROM_LSB _u(5)
#define PSM_FRCE_ON_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_BUSFABRIC
#define PSM_FRCE_ON_BUSFABRIC_RESET _u(0x0)
#define PSM_FRCE_ON_BUSFABRIC_BITS _u(0x00000010)
#define PSM_FRCE_ON_BUSFABRIC_MSB _u(4)
#define PSM_FRCE_ON_BUSFABRIC_LSB _u(4)
#define PSM_FRCE_ON_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_RESETS
#define PSM_FRCE_ON_RESETS_RESET _u(0x0)
#define PSM_FRCE_ON_RESETS_BITS _u(0x00000008)
#define PSM_FRCE_ON_RESETS_MSB _u(3)
#define PSM_FRCE_ON_RESETS_LSB _u(3)
#define PSM_FRCE_ON_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_CLOCKS
#define PSM_FRCE_ON_CLOCKS_RESET _u(0x0)
#define PSM_FRCE_ON_CLOCKS_BITS _u(0x00000004)
#define PSM_FRCE_ON_CLOCKS_MSB _u(2)
#define PSM_FRCE_ON_CLOCKS_LSB _u(2)
#define PSM_FRCE_ON_CLOCKS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_XOSC
#define PSM_FRCE_ON_XOSC_RESET _u(0x0)
#define PSM_FRCE_ON_XOSC_BITS _u(0x00000002)
#define PSM_FRCE_ON_XOSC_MSB _u(1)
#define PSM_FRCE_ON_XOSC_LSB _u(1)
#define PSM_FRCE_ON_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_ROSC
#define PSM_FRCE_ON_ROSC_RESET _u(0x0)
#define PSM_FRCE_ON_ROSC_BITS _u(0x00000001)
#define PSM_FRCE_ON_ROSC_MSB _u(0)
#define PSM_FRCE_ON_ROSC_LSB _u(0)
#define PSM_FRCE_ON_ROSC_ACCESS "RW"
// =============================================================================
// Register : PSM_FRCE_OFF
// Description : Force into reset (i.e. power it off)
#define PSM_FRCE_OFF_OFFSET _u(0x00000004)
#define PSM_FRCE_OFF_BITS _u(0x0001ffff)
#define PSM_FRCE_OFF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_PROC1
#define PSM_FRCE_OFF_PROC1_RESET _u(0x0)
#define PSM_FRCE_OFF_PROC1_BITS _u(0x00010000)
#define PSM_FRCE_OFF_PROC1_MSB _u(16)
#define PSM_FRCE_OFF_PROC1_LSB _u(16)
#define PSM_FRCE_OFF_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_PROC0
#define PSM_FRCE_OFF_PROC0_RESET _u(0x0)
#define PSM_FRCE_OFF_PROC0_BITS _u(0x00008000)
#define PSM_FRCE_OFF_PROC0_MSB _u(15)
#define PSM_FRCE_OFF_PROC0_LSB _u(15)
#define PSM_FRCE_OFF_PROC0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SIO
#define PSM_FRCE_OFF_SIO_RESET _u(0x0)
#define PSM_FRCE_OFF_SIO_BITS _u(0x00004000)
#define PSM_FRCE_OFF_SIO_MSB _u(14)
#define PSM_FRCE_OFF_SIO_LSB _u(14)
#define PSM_FRCE_OFF_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_VREG_AND_CHIP_RESET
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_RESET _u(0x0)
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_BITS _u(0x00002000)
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_MSB _u(13)
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_LSB _u(13)
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_XIP
#define PSM_FRCE_OFF_XIP_RESET _u(0x0)
#define PSM_FRCE_OFF_XIP_BITS _u(0x00001000)
#define PSM_FRCE_OFF_XIP_MSB _u(12)
#define PSM_FRCE_OFF_XIP_LSB _u(12)
#define PSM_FRCE_OFF_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM5
#define PSM_FRCE_OFF_SRAM5_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM5_BITS _u(0x00000800)
#define PSM_FRCE_OFF_SRAM5_MSB _u(11)
#define PSM_FRCE_OFF_SRAM5_LSB _u(11)
#define PSM_FRCE_OFF_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM4
#define PSM_FRCE_OFF_SRAM4_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM4_BITS _u(0x00000400)
#define PSM_FRCE_OFF_SRAM4_MSB _u(10)
#define PSM_FRCE_OFF_SRAM4_LSB _u(10)
#define PSM_FRCE_OFF_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM3
#define PSM_FRCE_OFF_SRAM3_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM3_BITS _u(0x00000200)
#define PSM_FRCE_OFF_SRAM3_MSB _u(9)
#define PSM_FRCE_OFF_SRAM3_LSB _u(9)
#define PSM_FRCE_OFF_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM2
#define PSM_FRCE_OFF_SRAM2_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM2_BITS _u(0x00000100)
#define PSM_FRCE_OFF_SRAM2_MSB _u(8)
#define PSM_FRCE_OFF_SRAM2_LSB _u(8)
#define PSM_FRCE_OFF_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM1
#define PSM_FRCE_OFF_SRAM1_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM1_BITS _u(0x00000080)
#define PSM_FRCE_OFF_SRAM1_MSB _u(7)
#define PSM_FRCE_OFF_SRAM1_LSB _u(7)
#define PSM_FRCE_OFF_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM0
#define PSM_FRCE_OFF_SRAM0_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM0_BITS _u(0x00000040)
#define PSM_FRCE_OFF_SRAM0_MSB _u(6)
#define PSM_FRCE_OFF_SRAM0_LSB _u(6)
#define PSM_FRCE_OFF_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_ROM
#define PSM_FRCE_OFF_ROM_RESET _u(0x0)
#define PSM_FRCE_OFF_ROM_BITS _u(0x00000020)
#define PSM_FRCE_OFF_ROM_MSB _u(5)
#define PSM_FRCE_OFF_ROM_LSB _u(5)
#define PSM_FRCE_OFF_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_BUSFABRIC
#define PSM_FRCE_OFF_BUSFABRIC_RESET _u(0x0)
#define PSM_FRCE_OFF_BUSFABRIC_BITS _u(0x00000010)
#define PSM_FRCE_OFF_BUSFABRIC_MSB _u(4)
#define PSM_FRCE_OFF_BUSFABRIC_LSB _u(4)
#define PSM_FRCE_OFF_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_RESETS
#define PSM_FRCE_OFF_RESETS_RESET _u(0x0)
#define PSM_FRCE_OFF_RESETS_BITS _u(0x00000008)
#define PSM_FRCE_OFF_RESETS_MSB _u(3)
#define PSM_FRCE_OFF_RESETS_LSB _u(3)
#define PSM_FRCE_OFF_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_CLOCKS
#define PSM_FRCE_OFF_CLOCKS_RESET _u(0x0)
#define PSM_FRCE_OFF_CLOCKS_BITS _u(0x00000004)
#define PSM_FRCE_OFF_CLOCKS_MSB _u(2)
#define PSM_FRCE_OFF_CLOCKS_LSB _u(2)
#define PSM_FRCE_OFF_CLOCKS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_XOSC
#define PSM_FRCE_OFF_XOSC_RESET _u(0x0)
#define PSM_FRCE_OFF_XOSC_BITS _u(0x00000002)
#define PSM_FRCE_OFF_XOSC_MSB _u(1)
#define PSM_FRCE_OFF_XOSC_LSB _u(1)
#define PSM_FRCE_OFF_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_ROSC
#define PSM_FRCE_OFF_ROSC_RESET _u(0x0)
#define PSM_FRCE_OFF_ROSC_BITS _u(0x00000001)
#define PSM_FRCE_OFF_ROSC_MSB _u(0)
#define PSM_FRCE_OFF_ROSC_LSB _u(0)
#define PSM_FRCE_OFF_ROSC_ACCESS "RW"
// =============================================================================
// Register : PSM_WDSEL
// Description : Set to 1 if this peripheral should be reset when the watchdog
// fires.
#define PSM_WDSEL_OFFSET _u(0x00000008)
#define PSM_WDSEL_BITS _u(0x0001ffff)
#define PSM_WDSEL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_PROC1
#define PSM_WDSEL_PROC1_RESET _u(0x0)
#define PSM_WDSEL_PROC1_BITS _u(0x00010000)
#define PSM_WDSEL_PROC1_MSB _u(16)
#define PSM_WDSEL_PROC1_LSB _u(16)
#define PSM_WDSEL_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_PROC0
#define PSM_WDSEL_PROC0_RESET _u(0x0)
#define PSM_WDSEL_PROC0_BITS _u(0x00008000)
#define PSM_WDSEL_PROC0_MSB _u(15)
#define PSM_WDSEL_PROC0_LSB _u(15)
#define PSM_WDSEL_PROC0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SIO
#define PSM_WDSEL_SIO_RESET _u(0x0)
#define PSM_WDSEL_SIO_BITS _u(0x00004000)
#define PSM_WDSEL_SIO_MSB _u(14)
#define PSM_WDSEL_SIO_LSB _u(14)
#define PSM_WDSEL_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_VREG_AND_CHIP_RESET
#define PSM_WDSEL_VREG_AND_CHIP_RESET_RESET _u(0x0)
#define PSM_WDSEL_VREG_AND_CHIP_RESET_BITS _u(0x00002000)
#define PSM_WDSEL_VREG_AND_CHIP_RESET_MSB _u(13)
#define PSM_WDSEL_VREG_AND_CHIP_RESET_LSB _u(13)
#define PSM_WDSEL_VREG_AND_CHIP_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_XIP
#define PSM_WDSEL_XIP_RESET _u(0x0)
#define PSM_WDSEL_XIP_BITS _u(0x00001000)
#define PSM_WDSEL_XIP_MSB _u(12)
#define PSM_WDSEL_XIP_LSB _u(12)
#define PSM_WDSEL_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM5
#define PSM_WDSEL_SRAM5_RESET _u(0x0)
#define PSM_WDSEL_SRAM5_BITS _u(0x00000800)
#define PSM_WDSEL_SRAM5_MSB _u(11)
#define PSM_WDSEL_SRAM5_LSB _u(11)
#define PSM_WDSEL_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM4
#define PSM_WDSEL_SRAM4_RESET _u(0x0)
#define PSM_WDSEL_SRAM4_BITS _u(0x00000400)
#define PSM_WDSEL_SRAM4_MSB _u(10)
#define PSM_WDSEL_SRAM4_LSB _u(10)
#define PSM_WDSEL_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM3
#define PSM_WDSEL_SRAM3_RESET _u(0x0)
#define PSM_WDSEL_SRAM3_BITS _u(0x00000200)
#define PSM_WDSEL_SRAM3_MSB _u(9)
#define PSM_WDSEL_SRAM3_LSB _u(9)
#define PSM_WDSEL_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM2
#define PSM_WDSEL_SRAM2_RESET _u(0x0)
#define PSM_WDSEL_SRAM2_BITS _u(0x00000100)
#define PSM_WDSEL_SRAM2_MSB _u(8)
#define PSM_WDSEL_SRAM2_LSB _u(8)
#define PSM_WDSEL_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM1
#define PSM_WDSEL_SRAM1_RESET _u(0x0)
#define PSM_WDSEL_SRAM1_BITS _u(0x00000080)
#define PSM_WDSEL_SRAM1_MSB _u(7)
#define PSM_WDSEL_SRAM1_LSB _u(7)
#define PSM_WDSEL_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM0
#define PSM_WDSEL_SRAM0_RESET _u(0x0)
#define PSM_WDSEL_SRAM0_BITS _u(0x00000040)
#define PSM_WDSEL_SRAM0_MSB _u(6)
#define PSM_WDSEL_SRAM0_LSB _u(6)
#define PSM_WDSEL_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_ROM
#define PSM_WDSEL_ROM_RESET _u(0x0)
#define PSM_WDSEL_ROM_BITS _u(0x00000020)
#define PSM_WDSEL_ROM_MSB _u(5)
#define PSM_WDSEL_ROM_LSB _u(5)
#define PSM_WDSEL_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_BUSFABRIC
#define PSM_WDSEL_BUSFABRIC_RESET _u(0x0)
#define PSM_WDSEL_BUSFABRIC_BITS _u(0x00000010)
#define PSM_WDSEL_BUSFABRIC_MSB _u(4)
#define PSM_WDSEL_BUSFABRIC_LSB _u(4)
#define PSM_WDSEL_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_RESETS
#define PSM_WDSEL_RESETS_RESET _u(0x0)
#define PSM_WDSEL_RESETS_BITS _u(0x00000008)
#define PSM_WDSEL_RESETS_MSB _u(3)
#define PSM_WDSEL_RESETS_LSB _u(3)
#define PSM_WDSEL_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_CLOCKS
#define PSM_WDSEL_CLOCKS_RESET _u(0x0)
#define PSM_WDSEL_CLOCKS_BITS _u(0x00000004)
#define PSM_WDSEL_CLOCKS_MSB _u(2)
#define PSM_WDSEL_CLOCKS_LSB _u(2)
#define PSM_WDSEL_CLOCKS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_XOSC
#define PSM_WDSEL_XOSC_RESET _u(0x0)
#define PSM_WDSEL_XOSC_BITS _u(0x00000002)
#define PSM_WDSEL_XOSC_MSB _u(1)
#define PSM_WDSEL_XOSC_LSB _u(1)
#define PSM_WDSEL_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_ROSC
#define PSM_WDSEL_ROSC_RESET _u(0x0)
#define PSM_WDSEL_ROSC_BITS _u(0x00000001)
#define PSM_WDSEL_ROSC_MSB _u(0)
#define PSM_WDSEL_ROSC_LSB _u(0)
#define PSM_WDSEL_ROSC_ACCESS "RW"
// =============================================================================
// Register : PSM_DONE
// Description : Indicates the peripheral's registers are ready to access.
#define PSM_DONE_OFFSET _u(0x0000000c)
#define PSM_DONE_BITS _u(0x0001ffff)
#define PSM_DONE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_DONE_PROC1
#define PSM_DONE_PROC1_RESET _u(0x0)
#define PSM_DONE_PROC1_BITS _u(0x00010000)
#define PSM_DONE_PROC1_MSB _u(16)
#define PSM_DONE_PROC1_LSB _u(16)
#define PSM_DONE_PROC1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_PROC0
#define PSM_DONE_PROC0_RESET _u(0x0)
#define PSM_DONE_PROC0_BITS _u(0x00008000)
#define PSM_DONE_PROC0_MSB _u(15)
#define PSM_DONE_PROC0_LSB _u(15)
#define PSM_DONE_PROC0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SIO
#define PSM_DONE_SIO_RESET _u(0x0)
#define PSM_DONE_SIO_BITS _u(0x00004000)
#define PSM_DONE_SIO_MSB _u(14)
#define PSM_DONE_SIO_LSB _u(14)
#define PSM_DONE_SIO_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_VREG_AND_CHIP_RESET
#define PSM_DONE_VREG_AND_CHIP_RESET_RESET _u(0x0)
#define PSM_DONE_VREG_AND_CHIP_RESET_BITS _u(0x00002000)
#define PSM_DONE_VREG_AND_CHIP_RESET_MSB _u(13)
#define PSM_DONE_VREG_AND_CHIP_RESET_LSB _u(13)
#define PSM_DONE_VREG_AND_CHIP_RESET_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_XIP
#define PSM_DONE_XIP_RESET _u(0x0)
#define PSM_DONE_XIP_BITS _u(0x00001000)
#define PSM_DONE_XIP_MSB _u(12)
#define PSM_DONE_XIP_LSB _u(12)
#define PSM_DONE_XIP_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM5
#define PSM_DONE_SRAM5_RESET _u(0x0)
#define PSM_DONE_SRAM5_BITS _u(0x00000800)
#define PSM_DONE_SRAM5_MSB _u(11)
#define PSM_DONE_SRAM5_LSB _u(11)
#define PSM_DONE_SRAM5_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM4
#define PSM_DONE_SRAM4_RESET _u(0x0)
#define PSM_DONE_SRAM4_BITS _u(0x00000400)
#define PSM_DONE_SRAM4_MSB _u(10)
#define PSM_DONE_SRAM4_LSB _u(10)
#define PSM_DONE_SRAM4_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM3
#define PSM_DONE_SRAM3_RESET _u(0x0)
#define PSM_DONE_SRAM3_BITS _u(0x00000200)
#define PSM_DONE_SRAM3_MSB _u(9)
#define PSM_DONE_SRAM3_LSB _u(9)
#define PSM_DONE_SRAM3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM2
#define PSM_DONE_SRAM2_RESET _u(0x0)
#define PSM_DONE_SRAM2_BITS _u(0x00000100)
#define PSM_DONE_SRAM2_MSB _u(8)
#define PSM_DONE_SRAM2_LSB _u(8)
#define PSM_DONE_SRAM2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM1
#define PSM_DONE_SRAM1_RESET _u(0x0)
#define PSM_DONE_SRAM1_BITS _u(0x00000080)
#define PSM_DONE_SRAM1_MSB _u(7)
#define PSM_DONE_SRAM1_LSB _u(7)
#define PSM_DONE_SRAM1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM0
#define PSM_DONE_SRAM0_RESET _u(0x0)
#define PSM_DONE_SRAM0_BITS _u(0x00000040)
#define PSM_DONE_SRAM0_MSB _u(6)
#define PSM_DONE_SRAM0_LSB _u(6)
#define PSM_DONE_SRAM0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_ROM
#define PSM_DONE_ROM_RESET _u(0x0)
#define PSM_DONE_ROM_BITS _u(0x00000020)
#define PSM_DONE_ROM_MSB _u(5)
#define PSM_DONE_ROM_LSB _u(5)
#define PSM_DONE_ROM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_BUSFABRIC
#define PSM_DONE_BUSFABRIC_RESET _u(0x0)
#define PSM_DONE_BUSFABRIC_BITS _u(0x00000010)
#define PSM_DONE_BUSFABRIC_MSB _u(4)
#define PSM_DONE_BUSFABRIC_LSB _u(4)
#define PSM_DONE_BUSFABRIC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_RESETS
#define PSM_DONE_RESETS_RESET _u(0x0)
#define PSM_DONE_RESETS_BITS _u(0x00000008)
#define PSM_DONE_RESETS_MSB _u(3)
#define PSM_DONE_RESETS_LSB _u(3)
#define PSM_DONE_RESETS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_CLOCKS
#define PSM_DONE_CLOCKS_RESET _u(0x0)
#define PSM_DONE_CLOCKS_BITS _u(0x00000004)
#define PSM_DONE_CLOCKS_MSB _u(2)
#define PSM_DONE_CLOCKS_LSB _u(2)
#define PSM_DONE_CLOCKS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_XOSC
#define PSM_DONE_XOSC_RESET _u(0x0)
#define PSM_DONE_XOSC_BITS _u(0x00000002)
#define PSM_DONE_XOSC_MSB _u(1)
#define PSM_DONE_XOSC_LSB _u(1)
#define PSM_DONE_XOSC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_ROSC
#define PSM_DONE_ROSC_RESET _u(0x0)
#define PSM_DONE_ROSC_BITS _u(0x00000001)
#define PSM_DONE_ROSC_MSB _u(0)
#define PSM_DONE_ROSC_LSB _u(0)
#define PSM_DONE_ROSC_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_PSM_H
|
