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* Rename everything significant to Kutter except for docsTomasz Kramkowski2025-08-152-9/+9
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* stm32: make i2c distinguish I2C NACKsTimofey Titovets2025-07-171-22/+38
| | | | Signed-off-by: Timofey Titovets <nefelim4ag@gmail.com>
* stm32: f0 do not send empty write on readTimofey Titovets2025-07-091-9/+11
| | | | Signed-off-by: Timofey Titovets <nefelim4ag@gmail.com>
* stm32: f0 make i2c distinguish I2C NACKsTimofey Titovets2025-07-091-1/+11
| | | | | | | | | | Some devices can return a read NACK on host retries. When the MCU receives the I2C CMD, reads out data, but fails to deliver a response to the host. The host retries, the device returns NACK, and the MCU goes into the shutdown state. Signed-off-by: Timofey Titovets <nefelim4ag@gmail.com>
* stm32: Adding more hardware pwm capable pins for STM32Hx series chips (#6965)jimmyjon7112025-06-181-0/+22
| | | Signed-off-by: Jim Madill <jcmadill1@gmail.com>
* stm32: Add comments on PLL frequency requirements to clock setup codeKevin O'Connor2025-06-028-0/+20
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Run stm32g431 at 170MhzKevin O'Connor2025-05-313-5/+8
| | | | | | The chip supports 170Mhz, so no need to run at 150Mhz. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Fix spi overflow issue on stm32h7Kevin O'Connor2025-05-301-8/+6
| | | | | | | | Completely filling the spi transmit fifo could lead to a situation where the rx fifo overflows. Make sure not to write past the rx fifo size. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Support using CANBUS on PB5/PB6 on stm32h7 chipsKevin O'Connor2025-05-302-2/+6
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Simplify Kconfig HAVE_STM32_CANBUS checksKevin O'Connor2025-05-301-7/+7
| | | | | | | | | Avoid unnecessary (HAVE_STM32_CANBUS && MACH_STM32xx) checks in Kconfig. The HAVE_STM32_CANBUS is a helper symbol for all the chips that support canbus, there's no need to mix it with a check for a chip that is already known to have canbus. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: h7 spi - add a delay on SCK polarity changeTimofey Titovets2025-05-261-2/+9
| | | | Signed-off-by: Timofey Titovets <nefelim4ag@gmail.com>
* stm32: Allow stm32g4 chips to select a bootloaderKevin O'Connor2025-05-191-1/+1
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: spi enable fifo if supported (#6936)Timofey Titovets2025-05-191-7/+21
| | | | Signed-off-by: Timofey Titovets <nefelim4ag@gmail.com> Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: H7 spi enable use of fifoTimofey Titovets2025-05-191-4/+8
| | | | Signed-off-by: Timofey Titovets <nefelim4ag@gmail.com>
* stm32: Avoid read-modify-write register access in stm32h7_spi.cKevin O'Connor2025-05-161-20/+16
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Run stm32h723 at 520MhzKevin O'Connor2025-05-022-2/+4
| | | | | | Increase speed of stm32h723 chips from 400Mhz to 520Mhz. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Support over 400Mhz main clock in stm32h7_adc.cKevin O'Connor2025-05-021-6/+7
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Use 12Mhz nominal internal clock in stm32f0_i2c.cKevin O'Connor2025-05-021-9/+9
| | | | | | | Increase the internal nominal clock from 8Mhz to 12Mhz - this improves support for higher chip frequencies. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Enable VOS0 power mode on stm32h723 if frequency above 400MhzKevin O'Connor2025-04-281-11/+15
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Don't try to set incorrect PWR->CR3 register on stm32h7Kevin O'Connor2025-04-281-5/+3
| | | | | | It's not valid to set BYPASS and LDOEN at the same time. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Set the PLL frequency equal to CONFIG_CLOCK_FREQ on stm32h723Kevin O'Connor2025-04-281-1/+1
| | | | | | | | There is no reason to use a higher internal PLL frequency. This change also makes it possible to enable higher clock frequencies on the stm32h723. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Avoid read-modify-write register updates in stm32h7 clock_setup()Kevin O'Connor2025-04-281-58/+39
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Use enable_pclock() in stm32h7 clock_setup()Kevin O'Connor2025-04-281-5/+4
| | | | | | | Use the helper functions to enable the peripheral clock instead of directly manipulating the clock enable bits. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32h7: Always clear AHB1ENR at startup on stm32h7Kevin O'Connor2025-04-281-5/+1
| | | | | | | Entirely clear the AHB1ENR register. There is no need to modify AHB1LPENR. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Add support for spi6 on stm32f42x chipsRussell Cloran2025-04-191-0/+7
| | | | Signed-off-by: Russell Cloran <rcloran@gmail.com>
* stm32: Fix pll_base on stm32h7 when using a clock other than 25MhzKevin O'Connor2025-04-191-1/+1
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Add optimized stm32h7_gpio.cKevin O'Connor2025-04-194-5/+176
| | | | | | | Add optimized gpio functions for stm32h7 - caching the ODR register can notably improve the performance of the gpio_out_toggle() code. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Change hard_pwm.c MAX_PWM to 257Kevin O'Connor2025-04-172-3/+4
| | | | | | Choose a value for MAX_PWM that avoids an expensive run-time division. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Fix prescaler overflow check in hard_pwm.cKevin O'Connor2025-04-171-3/+3
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Simplify MakefileKevin O'Connor2025-04-161-31/+19
| | | | | | Breakout selection of timer and gpioperiph objects. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* Kconfig: Add new WANT_ADC option to reduce code sizeKevin O'Connor2025-04-161-10/+13
| | | | | | | Make it possible to not compile in support for ADC on chips with small flash sizes. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* Kconfig: Add new WANT_I2C option to reduce code sizeKevin O'Connor2025-04-161-9/+12
| | | | | | | Make it possible to not compile in support for I2C on chips with small flash sizes. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* Kconfig: Add new WANT_SPI option to reduce code sizeKevin O'Connor2025-04-161-1/+1
| | | | | | | Make it possible to not compile in support for SPI on chips with small flash sizes. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* Kconfig: Add new WANT_HARD_PWM option to reduce code sizeKevin O'Connor2025-04-161-1/+1
| | | | | | | Make it possible to not compile in support for hardware pwm on chips with small flash sizes. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Enable gcc -Os option on CONFIG_HAVE_LIMITED_CODE_SIZEKevin O'Connor2025-04-161-0/+1
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Turn on can.c error interruptsKevin O'Connor2025-04-031-1/+1
| | | | | | | | It seems both ERRIE and LECIE must be enabled to get hardware error interrupts. Without this, the rx_error and tx_error reports are likely to always be zero. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Add support for additional i2c busRussell Cloran2025-04-021-0/+3
| | | | Signed-off-by: Russell Cloran <rcloran@gmail.com>
* stm32: Fix RESERVE_PINS_CAN pin ordering in fdcan.cKevin O'Connor2025-04-011-1/+1
| | | | | | Always report the reserved pins in the same order (rx,tx). Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Added PH13/14 CAN pin option for stm32h743 (#6857)FrY Sennberg2025-03-272-0/+14
| | | | | Added the option to select PH13/PH14 as CAN pins. Signed-off-by: Christoph Frei <fryakatkop@gmail.com>
* stepper: Support step on both edges with custom minimum pulse durationKevin O'Connor2025-03-201-1/+1
| | | | | | | | | | Add support for "step on both edges" to the main stepper_event_full() code. This makes that mode of operation available even when the micro-controller is not compiled for "optimized step on both edges". It also enables the custom pulse duration support (step_pulse_ticks) when in "step on both edges" mode. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Add support for USART6 on STM32F401Marius Petcu2025-03-072-2/+28
| | | | | | | | | STM32F401 has USART6 on PA12/PA11 and PC7/PC6 with alternate function mapping AF08. This can be used, for example, to connect to the Elegoo Neptune 3, where PA12/PA11 are wired to an RJ10 plug going to the stock screen. Signed-off-by: Marius Petcu <marius@petcu.me>
* stm32: Add support for stm32f070x6 mcusKevin O'Connor2025-02-162-9/+13
| | | | | | This mcu has smaller memory and may require remapping of PA11/PA12. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: h7 spi support reload mode & frequencyTimofey Titovets2025-02-062-3/+17
| | | | Signed-off-by: Timofey Titovets <nefelim4ag@gmail.com>
* stm32: Add support for reporting canbus state from fdcan.cKevin O'Connor2025-02-021-2/+47
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Add support for reporting canbus state from can.cKevin O'Connor2025-02-021-2/+46
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: forward i2c errors to i2ccmdTimofey Titovets2024-10-261-13/+23
| | | | Signed-off-by: Timofey Titovets <nefelim4ag@gmail.com>
* i2c: handle errors at i2ccmdsTimofey Titovets2024-10-263-7/+17
| | | | Signed-off-by: Timofey Titovets <nefelim4ag@gmail.com>
* stm32: Add support for USART3 on PC11/PC10 on STM32G474. (#6704)Liam Powell2024-10-242-0/+12
| | | Signed-off-by: Liam Powell <liam@liampwll.com>
* stm32: allow 400Khz in stm32f0_i2c.c (#6694)Timofey Titovets2024-10-091-0/+7
| | | Signed-off-by: Timofey Titovets <nefelim4ag@gmail.com>
* stm32: Fix i2c clock speeds for chips with a peripheral clock over 48MhzKevin O'Connor2024-09-221-5/+13
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
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