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* stm32: spi enable fifo if supported (#6936)Timofey Titovets2025-05-191-7/+21
| | | | Signed-off-by: Timofey Titovets <nefelim4ag@gmail.com> Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: H7 spi enable use of fifoTimofey Titovets2025-05-191-4/+8
| | | | Signed-off-by: Timofey Titovets <nefelim4ag@gmail.com>
* stm32: Avoid read-modify-write register access in stm32h7_spi.cKevin O'Connor2025-05-161-20/+16
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Run stm32h723 at 520MhzKevin O'Connor2025-05-022-2/+4
| | | | | | Increase speed of stm32h723 chips from 400Mhz to 520Mhz. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Support over 400Mhz main clock in stm32h7_adc.cKevin O'Connor2025-05-021-6/+7
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Use 12Mhz nominal internal clock in stm32f0_i2c.cKevin O'Connor2025-05-021-9/+9
| | | | | | | Increase the internal nominal clock from 8Mhz to 12Mhz - this improves support for higher chip frequencies. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Enable VOS0 power mode on stm32h723 if frequency above 400MhzKevin O'Connor2025-04-281-11/+15
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Don't try to set incorrect PWR->CR3 register on stm32h7Kevin O'Connor2025-04-281-5/+3
| | | | | | It's not valid to set BYPASS and LDOEN at the same time. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Set the PLL frequency equal to CONFIG_CLOCK_FREQ on stm32h723Kevin O'Connor2025-04-281-1/+1
| | | | | | | | There is no reason to use a higher internal PLL frequency. This change also makes it possible to enable higher clock frequencies on the stm32h723. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Avoid read-modify-write register updates in stm32h7 clock_setup()Kevin O'Connor2025-04-281-58/+39
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Use enable_pclock() in stm32h7 clock_setup()Kevin O'Connor2025-04-281-5/+4
| | | | | | | Use the helper functions to enable the peripheral clock instead of directly manipulating the clock enable bits. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32h7: Always clear AHB1ENR at startup on stm32h7Kevin O'Connor2025-04-281-5/+1
| | | | | | | Entirely clear the AHB1ENR register. There is no need to modify AHB1LPENR. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Add support for spi6 on stm32f42x chipsRussell Cloran2025-04-191-0/+7
| | | | Signed-off-by: Russell Cloran <rcloran@gmail.com>
* stm32: Fix pll_base on stm32h7 when using a clock other than 25MhzKevin O'Connor2025-04-191-1/+1
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Add optimized stm32h7_gpio.cKevin O'Connor2025-04-194-5/+176
| | | | | | | Add optimized gpio functions for stm32h7 - caching the ODR register can notably improve the performance of the gpio_out_toggle() code. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Change hard_pwm.c MAX_PWM to 257Kevin O'Connor2025-04-172-3/+4
| | | | | | Choose a value for MAX_PWM that avoids an expensive run-time division. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Fix prescaler overflow check in hard_pwm.cKevin O'Connor2025-04-171-3/+3
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Simplify MakefileKevin O'Connor2025-04-161-31/+19
| | | | | | Breakout selection of timer and gpioperiph objects. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* Kconfig: Add new WANT_ADC option to reduce code sizeKevin O'Connor2025-04-161-10/+13
| | | | | | | Make it possible to not compile in support for ADC on chips with small flash sizes. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* Kconfig: Add new WANT_I2C option to reduce code sizeKevin O'Connor2025-04-161-9/+12
| | | | | | | Make it possible to not compile in support for I2C on chips with small flash sizes. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* Kconfig: Add new WANT_SPI option to reduce code sizeKevin O'Connor2025-04-161-1/+1
| | | | | | | Make it possible to not compile in support for SPI on chips with small flash sizes. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* Kconfig: Add new WANT_HARD_PWM option to reduce code sizeKevin O'Connor2025-04-161-1/+1
| | | | | | | Make it possible to not compile in support for hardware pwm on chips with small flash sizes. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Enable gcc -Os option on CONFIG_HAVE_LIMITED_CODE_SIZEKevin O'Connor2025-04-161-0/+1
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Turn on can.c error interruptsKevin O'Connor2025-04-031-1/+1
| | | | | | | | It seems both ERRIE and LECIE must be enabled to get hardware error interrupts. Without this, the rx_error and tx_error reports are likely to always be zero. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Add support for additional i2c busRussell Cloran2025-04-021-0/+3
| | | | Signed-off-by: Russell Cloran <rcloran@gmail.com>
* stm32: Fix RESERVE_PINS_CAN pin ordering in fdcan.cKevin O'Connor2025-04-011-1/+1
| | | | | | Always report the reserved pins in the same order (rx,tx). Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Added PH13/14 CAN pin option for stm32h743 (#6857)FrY Sennberg2025-03-272-0/+14
| | | | | Added the option to select PH13/PH14 as CAN pins. Signed-off-by: Christoph Frei <fryakatkop@gmail.com>
* stepper: Support step on both edges with custom minimum pulse durationKevin O'Connor2025-03-201-1/+1
| | | | | | | | | | Add support for "step on both edges" to the main stepper_event_full() code. This makes that mode of operation available even when the micro-controller is not compiled for "optimized step on both edges". It also enables the custom pulse duration support (step_pulse_ticks) when in "step on both edges" mode. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Add support for USART6 on STM32F401Marius Petcu2025-03-072-2/+28
| | | | | | | | | STM32F401 has USART6 on PA12/PA11 and PC7/PC6 with alternate function mapping AF08. This can be used, for example, to connect to the Elegoo Neptune 3, where PA12/PA11 are wired to an RJ10 plug going to the stock screen. Signed-off-by: Marius Petcu <marius@petcu.me>
* stm32: Add support for stm32f070x6 mcusKevin O'Connor2025-02-162-9/+13
| | | | | | This mcu has smaller memory and may require remapping of PA11/PA12. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: h7 spi support reload mode & frequencyTimofey Titovets2025-02-062-3/+17
| | | | Signed-off-by: Timofey Titovets <nefelim4ag@gmail.com>
* stm32: Add support for reporting canbus state from fdcan.cKevin O'Connor2025-02-021-2/+47
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Add support for reporting canbus state from can.cKevin O'Connor2025-02-021-2/+46
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: forward i2c errors to i2ccmdTimofey Titovets2024-10-261-13/+23
| | | | Signed-off-by: Timofey Titovets <nefelim4ag@gmail.com>
* i2c: handle errors at i2ccmdsTimofey Titovets2024-10-263-7/+17
| | | | Signed-off-by: Timofey Titovets <nefelim4ag@gmail.com>
* stm32: Add support for USART3 on PC11/PC10 on STM32G474. (#6704)Liam Powell2024-10-242-0/+12
| | | Signed-off-by: Liam Powell <liam@liampwll.com>
* stm32: allow 400Khz in stm32f0_i2c.c (#6694)Timofey Titovets2024-10-091-0/+7
| | | Signed-off-by: Timofey Titovets <nefelim4ag@gmail.com>
* stm32: Fix i2c clock speeds for chips with a peripheral clock over 48MhzKevin O'Connor2024-09-221-5/+13
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Reduce peripheral clock speed on stm32g4 chipsKevin O'Connor2024-09-221-2/+2
| | | | | | A 170mhz (or 150mhz) peripheral clock is too fast for some peripherals. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* STM32: Check for NACK (#6687)Timofey Titovets2024-09-222-0/+4
| | | Signed-off-by: Timofey Titovets <nefelim4ag@gmail.com>
* stm32: Fix setting USB clock with USB to CANbus mode on stm32g4/stm32l4Kevin O'Connor2024-08-292-2/+2
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Fix getting wrong ADC value on PA0 of STM32G431 (#6660)Nicholas Huskie2024-08-081-21/+23
| | | | | | | * Fix getting wrong ADC value on PA0 * Fix invalid/unused pin being used as adc channel on STM32H7/G431/L4 Signed-off-by: Nicholas Huskie <huskie@idealfuture.org.cn>
* armcm_link: Fix build on recent arm gcc/newlibc versionsKevin O'Connor2024-06-171-1/+1
| | | | | | | | It seems recent arm gcc versions no longer build correctly using the "--specs=nano.specs --specs=nosys.specs" linker flags. Replace those linker flags with "-nostdlib -lgcc -lc_nano". Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: STM32F031 updates (#6607)Elias Bakken2024-05-252-2/+4
| | | | | | | Add support for STM32F031x6 which is the 32 KB version of the STM32F031 MCU. Add new I2C bus variant. Signed-off by: Elias Bakken <elias@iagent.no>
* stm32: Add STM32G474 chip to KconfigDropeffect GmbH2024-05-141-0/+7
| | | | Signed-off-by: Amr Elsayed from Dropeffect GmbH <code@dropeffect.com>
* stm32: Add FDCAN2 channel needed for stm32g4 alternate pinsDropeffect GmbH2024-05-142-2/+15
| | | | | | | | Some of the alternate pins defined are routed to FDCAN2 instead of FDCAN1, this commit uses the correct IRQ register and peripheral clock enable bit to enable FDCAN on those pins. Signed-off-by: Amr Elsayed from Dropeffect GmbH <code@dropeffect.com>
* stm32g4: Fix ADC3 common interface registers name to ADC345_COMMONDropeffect GmbH2024-05-141-0/+4
| | | | | | Use ADC345_COMMON instead of ADC3_COMMON for stm32g4 ADC3 channel. Signed-off-by: Amr Elsayed from Dropeffect GmbH <code@dropeffect.com>
* stm32: Add new spi2 on stm32g0 chips (#6569)Donald A. Cupp Jr2024-05-031-15/+27
| | | Signed-off-by: Donald A. Cupp Jr <doncuppjr@yahoo.com>
* config: Artillery Sidewinder X3 (#6534)TheFeralEngineer2024-04-121-1/+1
| | | Signed-off-by: Phil Timpson <theferalengineer@gmail.com>
* stm32: fix support for USARTs on STM32G0B0Robert Cambridge2024-04-031-0/+7
| | | | Signed-off-by: Robert Cambridge <robert@cambridge.me>
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