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* stm32: Remove unused header from can.cKevin O'Connor2022-05-101-1/+0
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: add 8 KiB bootloader option for F0x2 devicesEric Callahan2022-05-101-1/+1
| | | | Signed-off-by: Eric Callahan <arksine.code@gmail.com>
* stm32: Fix typo in i2c.cKevin O'Connor2022-05-071-2/+2
| | | | | | Reported by @kaidegit. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Add 64kib bootloader offset option to STM32F401 (#5457)JamesH19782022-04-251-1/+1
| | | | | This is needed for the Creality Ender 3 S1 with the STM32F401 chips to enable a 64kib bootloader offset Signed-off-by: James Hartley <james@hartleyns.com>
* stm32: Add STM32F072 16KiB bootloader option (#5404)alstoepp2022-04-131-1/+1
| | | Signed-off-by: Alexander Stöpperger <a.stoepperger@gmx-topmail.de>
* stm32: Add support for additional i2c busesKevin O'Connor2022-04-111-0/+17
| | | | | | Reported by @StoneColdCrazy. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Allow 32KiB bootloader to be specified for all STM32F4 buildsKevin O'Connor2022-03-141-1/+1
| | | | | | Reported by @GerogeFu. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Clarify CCIPR2 setting in stm32g0.cKevin O'Connor2022-03-111-1/+1
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Simplify CCIPR2 register assignment on stm32g0Kevin O'Connor2022-03-091-5/+2
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: USB clock source from PLLQCLK on stm32g0 (#5341)BIGTREETECH2022-03-091-6/+4
| | | Signed-off-by: Alan.Ma from BigTreeTech <tech@biqu3d.com>
* stm32: Clear SPE flag on a change to SPI CR1 registerKevin O'Connor2022-02-101-0/+6
| | | | | | | | | The stm32 specs indicate that the SPE bit must be cleared before changing the CPHA or CPOL bits. Reported by @cbc02009 and @bigtreetech. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Wait for transmission to complete before returning from spi_transfer()Kevin O'Connor2022-02-101-2/+5
| | | | | | | | | | | | | It's possible for the SCLK pin to still be updating even after the last byte of data has been read from the receive pin. (In particular in spi mode 0 and 1.) Exiting early from spi_transfer() in this case could result in the CS pin being raised before the final updates to SCLK pin. Add an additional wait at the end of spi_transfer() to avoid this issue. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Fix ADC on stm32h7 (#5239)adelyser2022-02-061-1/+3
| | | | | | Don't reset the ADC peripheral if the clock is already enabled. Fixes #5236 Signed-off-by: Aaron DeLyser <bluwolf@gmail.com>
* stm32: Add remap CAN to PD0/PD1 for stm32f103 (#5173)Sergey15602022-01-262-1/+4
| | | Signed-off-by: Sergey Terentiev <sergey@terentiev.me>
* stm32: Update Kconfig as CANBUS isn't available on stm32f401Kevin O'Connor2022-01-071-8/+15
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Unify enable_pclock() codeKevin O'Connor2021-12-308-238/+125
| | | | | | | | | Unify the handling of the enable_pclock() and is_enabled_pclock() code across all stm32 chips. All chips will now perform a peripheral reset on enable_pclock() (this is a change for stm32f0 and stm32h7). The enable_pclock() code will now also disable irqs during the enable. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Fix the GPIO register for stm32h7 (#5077)adelyser2021-12-291-3/+3
| | | Signed-off-by: Aaron DeLyser <bluwolf@gmail.com>
* stm32: Fix ADC on stm32f042Kevin O'Connor2021-12-241-0/+1
| | | | | | It seems the stm32f042 chip needs a small delay during ADC enable. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Enable SPI support on stm32g0Kevin O'Connor2021-12-232-4/+8
| | | | | Signed-off-by: Alan.Ma from BigTreeTech <tech@biqu3d.com> Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Enable ADC support on stm32g0Kevin O'Connor2021-12-233-12/+51
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Rework register access on stm32f0_adc.cKevin O'Connor2021-12-231-34/+25
| | | | | | | | | | | Avoid read-modify-write operations where possible. The register values are in a known state so prefer absolute writes. Improve handling of race conditions with hardware updates. Remove the adc reference from "struct gpio_adc" as it is a constant. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Minor whitespace changes to stm32f0_adc.cKevin O'Connor2021-12-231-12/+8
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Enable I2C on stm32g0Kevin O'Connor2021-12-232-1/+2
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Add support for USB on stm32g0Kevin O'Connor2021-12-232-21/+70
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Rework USB transfer memory layout in usbfs.cKevin O'Connor2021-12-231-46/+55
| | | | | | | | | Use a fixed layout for the USB transfer memory and remove the ep_mem struct definition. This is in preparation for stm32g0 support. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Fix buffer size calculation in usbfs.cKevin O'Connor2021-12-231-1/+1
| | | | | | When the buffers are over 32 bytes, a block count of 1 starts at 0. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Simplify irq declaration in usbfs.cKevin O'Connor2021-12-231-11/+11
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Initial support for stm32g0Kevin O'Connor2021-12-236-8/+253
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Enable optimized gpio_clock_enable() function on stm32h7Kevin O'Connor2021-12-231-1/+3
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Reorganize stm32h7.c into major code blocksKevin O'Connor2021-12-231-10/+21
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Remove USB boot stubs from stm32h7.cKevin O'Connor2021-12-231-8/+0
| | | | | | | The USB dfu bootloader wasn't enabled on stm32h7, so remove the copy-and-paste code stubs for it. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Fix DFU entry point on stm32f072Kevin O'Connor2021-12-231-0/+2
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Reorganize usb bootloader code in stm32f0.cKevin O'Connor2021-12-231-38/+65
| | | | | | Reorganize stm32f0.c into major code blocks. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Reorganize usb bootloader code in stm32f4.cKevin O'Connor2021-12-231-30/+63
| | | | | | Reorganize stm32f4.c into major code blocks. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Reorganize code in stm32f1.cKevin O'Connor2021-12-231-47/+82
| | | | | | Reorganize stm32f1.c into major code blocks. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Add new gpioperiph.c file for gpio_peripheral() codeKevin O'Connor2021-12-235-83/+45
| | | | | | | | The gpio_peripheral() code is the same in stm32f0.c, stm32f4.c, and stm32h7.c. Move that function to a new gpioperiph.c file to avoid code duplication. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Add option to disable SWD on GigaDevice STM32F103 clonesKevin O'Connor2021-11-252-2/+17
| | | | | | Tested by @FotoFieber. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Add USBOTG support to stm32h7adelyser2021-11-213-23/+81
| | | | | Signed-off-by: Aaron DeLyser <bluwolf@gmail.com> Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Enable SPI on stm32h7Kevin O'Connor2021-11-201-1/+1
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Add stm32h7 SPI support (#4850)adelyser2021-11-203-3/+159
| | | Signed-off-by: Aaron DeLyser <bluwolf@gmail.com>
* stm32: Add STM32H743 supportadelyser2021-11-201-3/+17
| | | | | Signed-off-by: Aaron DeLyser <bluwolf@gmail.com> Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Limit stm32h7 chips to 400MhzKevin O'Connor2021-11-201-1/+1
| | | | | | | | Don't go above 400Mhz as otherwise it causes 32bit rollover issues. (Parts of the code expect a rollover will not occur faster than 10 seconds.) Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Add UART4 to stm32h7 (#4848)adelyser2021-11-191-2/+13
| | | Signed-off-by: Aaron DeLyser <bluwolf@gmail.com>
* stm32f4: reset peripherals in enable_pcclock()Eric Callahan2021-11-081-0/+7
| | | | | | | Reset peripherals to after enabling to clear stale registers set by the bootloader. Signed-off-by: Eric Callahan <arksine.code@gmail.com>
* stm32f4: reset peripheral clocks on initEric Callahan2021-11-081-0/+6
| | | | Signed-off-by: Eric Callahan <arksine.code@gmail.com>
* stepper: Add support for stepping on both edges of a step pulseKevin O'Connor2021-11-041-0/+1
| | | | | | | | | | Add an optimized step function for drivers that support stepping on both rising and falling edges of the step pin. Enable this optimization on 32bit ARM micro-controllers. Automatically detect this capability in the host code and enable on TMC drivers running in SPI/UART mode. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Remove gcc -mfpu=fpv4-sp-d16 floating point optionKevin O'Connor2021-10-301-1/+0
| | | | | | | | The floating point unit must be enabled in order to use it and Klipper does not currently implement that. Newer versions of gcc may spill registers to the floating point unit causing failures. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Add a MACH_STM32F0x2 alias for F042 and F072 chipsKevin O'Connor2021-10-132-7/+11
| | | | | | | | The F042 and F072 chips are in the same series and the code should be nearly identical for these chips. Implement the alias and enable USB for the F072 chips. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Rework HAVE_GPIO_HARD_PWM in KconfigKevin O'Connor2021-10-131-7/+1
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* stm32: Change stm32f0 OSPEEDR to "medium" speedKevin O'Connor2021-10-121-1/+1
| | | | | | | | | The previous OSPEEDR value of 0x2 was copied from the stm32f4.c code, but the stm32f0 interprets that value the same as 0x0 - which is "low" speed. Change the OSPEEDR value to "medium" speed so that it matches the configuration of stm32f1 chips. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
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