diff options
Diffstat (limited to 'src/stm32/stm32h7.c')
| -rw-r--r-- | src/stm32/stm32h7.c | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/src/stm32/stm32h7.c b/src/stm32/stm32h7.c index 122ce64b..056f7be2 100644 --- a/src/stm32/stm32h7.c +++ b/src/stm32/stm32h7.c @@ -46,8 +46,16 @@ lookup_clock_line(uint32_t periph_base) uint32_t bit = 1 << ((periph_base - D2_APB2PERIPH_BASE) / 0x400); return (struct cline){.en=&RCC->APB2ENR, .rst=&RCC->APB2RSTR, .bit=bit}; } else { - uint32_t bit = 1 << ((periph_base - D2_APB1PERIPH_BASE) / 0x400); - return (struct cline){.en=&RCC->APB1LENR,.rst=&RCC->APB1LRSTR,.bit=bit}; + uint32_t offset = ((periph_base - D2_APB1PERIPH_BASE) / 0x400); + if (offset < 32) { + uint32_t bit = 1 << offset; + return (struct cline){ + .en=&RCC->APB1LENR, .rst=&RCC->APB1LRSTR, .bit=bit}; + } else { + uint32_t bit = 1 << (offset - 32); + return (struct cline){ + .en=&RCC->APB1HENR, .rst=&RCC->APB1HRSTR, .bit=bit}; + } } } @@ -170,6 +178,9 @@ clock_setup(void) while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL1) ; + // Set the source of FDCAN clock + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, RCC_D2CCIP1R_FDCANSEL_0); + // Configure HSI48 clock for USB if (CONFIG_USB) { SET_BIT(RCC->CR, RCC_CR_HSI48ON); |