diff options
Diffstat (limited to 'src/stm32/stm32f4.c')
| -rw-r--r-- | src/stm32/stm32f4.c | 28 |
1 files changed, 26 insertions, 2 deletions
diff --git a/src/stm32/stm32f4.c b/src/stm32/stm32f4.c index 9b5433af..bc8d0eb2 100644 --- a/src/stm32/stm32f4.c +++ b/src/stm32/stm32f4.c @@ -1,4 +1,4 @@ -// Code to setup clocks and gpio on stm32f4 +// Code to setup clocks and gpio on stm32f2/stm32f4 // // Copyright (C) 2019 Kevin O'Connor <kevin@koconnor.net> // @@ -119,6 +119,28 @@ DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PH0,PH1"); // Clock configuration static void +enable_clock_stm32f20x(void) +{ +#if CONFIG_MACH_STM32F207 + uint32_t pll_base = 1000000, pll_freq = CONFIG_CLOCK_FREQ * 2, pllcfgr; + if (!CONFIG_STM32_CLOCK_REF_INTERNAL) { + // Configure 120Mhz PLL from external crystal (HSE) + uint32_t div = CONFIG_CLOCK_REF_FREQ / pll_base; + RCC->CR |= RCC_CR_HSEON; + pllcfgr = RCC_PLLCFGR_PLLSRC_HSE | (div << RCC_PLLCFGR_PLLM_Pos); + } else { + // Configure 120Mhz PLL from internal 16Mhz oscillator (HSI) + uint32_t div = 16000000 / pll_base; + pllcfgr = RCC_PLLCFGR_PLLSRC_HSI | (div << RCC_PLLCFGR_PLLM_Pos); + } + RCC->PLLCFGR = (pllcfgr | ((pll_freq/pll_base) << RCC_PLLCFGR_PLLN_Pos) + | (0 << RCC_PLLCFGR_PLLP_Pos) + | ((pll_freq/FREQ_USB) << RCC_PLLCFGR_PLLQ_Pos)); + RCC->CR |= RCC_CR_PLLON; +#endif +} + +static void enable_clock_stm32f40x(void) { #if CONFIG_MACH_STM32F405 || CONFIG_MACH_STM32F407 @@ -194,7 +216,9 @@ static void clock_setup(void) { // Configure and enable PLL - if (CONFIG_MACH_STM32F405 || CONFIG_MACH_STM32F407) + if (CONFIG_MACH_STM32F207) + enable_clock_stm32f20x(); + else if (CONFIG_MACH_STM32F405 || CONFIG_MACH_STM32F407) enable_clock_stm32f40x(); else enable_clock_stm32f446(); |