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-rw-r--r--src/sam3x8e/timer.c24
1 files changed, 11 insertions, 13 deletions
diff --git a/src/sam3x8e/timer.c b/src/sam3x8e/timer.c
index ba1124cb..3a441062 100644
--- a/src/sam3x8e/timer.c
+++ b/src/sam3x8e/timer.c
@@ -1,6 +1,6 @@
// SAM3x8e timer interrupt scheduling
//
-// Copyright (C) 2016 Kevin O'Connor <kevin@koconnor.net>
+// Copyright (C) 2016,2017 Kevin O'Connor <kevin@koconnor.net>
//
// This file may be distributed under the terms of the GNU GPLv3 license.
@@ -9,7 +9,7 @@
#include "board/timer_irq.h" // timer_dispatch_many
#include "command.h" // DECL_SHUTDOWN
#include "sam3x8e.h" // TC0
-#include "sched.h" // sched_timer_kick
+#include "sched.h" // DECL_INIT
// Set the next irq time
static void
@@ -32,6 +32,14 @@ timer_read_time(void)
return TC0->TC_CHANNEL[0].TC_CV;
}
+// Activate timer dispatch as soon as possible
+void
+timer_kick(void)
+{
+ timer_set(timer_read_time() + 50);
+ TC0->TC_CHANNEL[0].TC_SR; // read to clear irq pending
+}
+
void
timer_init(void)
{
@@ -39,27 +47,17 @@ timer_init(void)
// Reset the timer
tc->TC_CCR = TC_CCR_CLKDIS;
tc->TC_IDR = 0xFFFFFFFF;
- tc->TC_SR;
// Enable it
PMC->PMC_PCER0 = 1 << ID_TC0;
tc->TC_CMR = TC_CMR_WAVE | TC_CMR_WAVSEL_UP | TC_CMR_TCCLKS_TIMER_CLOCK1;
tc->TC_IER = TC_IER_CPAS;
NVIC_SetPriority(TC0_IRQn, 1);
NVIC_EnableIRQ(TC0_IRQn);
- timer_set(1);
+ timer_kick();
tc->TC_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG;
}
DECL_INIT(timer_init);
-void
-timer_shutdown(void)
-{
- // Reenable timer irq
- timer_set(timer_read_time() + 50);
- TC0->TC_CHANNEL[0].TC_SR; // read to clear irq pending
-}
-DECL_SHUTDOWN(timer_shutdown);
-
// IRQ handler
void __visible __aligned(16) // aligning helps stabilize perf benchmarks
TC0_Handler(void)