diff options
Diffstat (limited to 'lib/rp2040/hardware/structs')
31 files changed, 1238 insertions, 0 deletions
diff --git a/lib/rp2040/hardware/structs/adc.h b/lib/rp2040/hardware/structs/adc.h new file mode 100644 index 00000000..559b5f17 --- /dev/null +++ b/lib/rp2040/hardware/structs/adc.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_ADC_H +#define _HARDWARE_STRUCTS_ADC_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/adc.h" + +typedef struct { + io_rw_32 cs; + io_rw_32 result; + io_rw_32 fcs; + io_rw_32 fifo; + io_rw_32 div; + io_rw_32 intr; + io_rw_32 inte; + io_rw_32 intf; + io_rw_32 ints; +} adc_hw_t; + +check_hw_layout(adc_hw_t, ints, ADC_INTS_OFFSET); + +#define adc_hw ((adc_hw_t *const)ADC_BASE) + +#endif diff --git a/lib/rp2040/hardware/structs/bus_ctrl.h b/lib/rp2040/hardware/structs/bus_ctrl.h new file mode 100644 index 00000000..ce95a7c1 --- /dev/null +++ b/lib/rp2040/hardware/structs/bus_ctrl.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_BUS_CTRL_H +#define _HARDWARE_STRUCTS_BUS_CTRL_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/busctrl.h" + +enum bus_ctrl_perf_counter { + arbiter_rom_perf_event_access = 19, + arbiter_rom_perf_event_access_contested = 18, + arbiter_xip_main_perf_event_access = 17, + arbiter_xip_main_perf_event_access_contested = 16, + arbiter_sram0_perf_event_access = 15, + arbiter_sram0_perf_event_access_contested = 14, + arbiter_sram1_perf_event_access = 13, + arbiter_sram1_perf_event_access_contested = 12, + arbiter_sram2_perf_event_access = 11, + arbiter_sram2_perf_event_access_contested = 10, + arbiter_sram3_perf_event_access = 9, + arbiter_sram3_perf_event_access_contested = 8, + arbiter_sram4_perf_event_access = 7, + arbiter_sram4_perf_event_access_contested = 6, + arbiter_sram5_perf_event_access = 5, + arbiter_sram5_perf_event_access_contested = 4, + arbiter_fastperi_perf_event_access = 3, + arbiter_fastperi_perf_event_access_contested = 2, + arbiter_apb_perf_event_access = 1, + arbiter_apb_perf_event_access_contested = 0 +}; + +typedef struct { + io_rw_32 priority; + io_ro_32 priority_ack; + struct { + io_rw_32 value; + io_rw_32 sel; + } counter[4]; +} bus_ctrl_hw_t; + +check_hw_layout(bus_ctrl_hw_t, counter[0].value, BUSCTRL_PERFCTR0_OFFSET); + +#define bus_ctrl_hw ((bus_ctrl_hw_t *const)BUSCTRL_BASE) + +#endif diff --git a/lib/rp2040/hardware/structs/clocks.h b/lib/rp2040/hardware/structs/clocks.h new file mode 100644 index 00000000..489876d1 --- /dev/null +++ b/lib/rp2040/hardware/structs/clocks.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_CLOCKS_H +#define _HARDWARE_STRUCTS_CLOCKS_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/clocks.h" + +/*! \brief Enumeration identifying a hardware clock + * \ingroup hardware_clocks + */ +/// \tag::clkenum[] +enum clock_index { + clk_gpout0 = 0, ///< GPIO Muxing 0 + clk_gpout1, ///< GPIO Muxing 1 + clk_gpout2, ///< GPIO Muxing 2 + clk_gpout3, ///< GPIO Muxing 3 + clk_ref, ///< Watchdog and timers reference clock + clk_sys, ///< Processors, bus fabric, memory, memory mapped registers + clk_peri, ///< Peripheral clock for UART and SPI + clk_usb, ///< USB clock + clk_adc, ///< ADC clock + clk_rtc, ///< Real time clock + CLK_COUNT +}; +/// \end::clkenum[] + +/// \tag::clock_hw[] +typedef struct { + io_rw_32 ctrl; + io_rw_32 div; + io_rw_32 selected; +} clock_hw_t; +/// \end::clock_hw[] + +typedef struct { + io_rw_32 ref_khz; + io_rw_32 min_khz; + io_rw_32 max_khz; + io_rw_32 delay; + io_rw_32 interval; + io_rw_32 src; + io_ro_32 status; + io_ro_32 result; +} fc_hw_t; + +typedef struct { + clock_hw_t clk[CLK_COUNT]; + struct { + io_rw_32 ctrl; + io_rw_32 status; + } resus; + fc_hw_t fc0; + io_rw_32 wake_en0; + io_rw_32 wake_en1; + io_rw_32 sleep_en0; + io_rw_32 sleep_en1; + io_rw_32 enabled0; + io_rw_32 enabled1; + io_rw_32 intr; + io_rw_32 inte; + io_rw_32 intf; + io_rw_32 ints; +} clocks_hw_t; + +#define clocks_hw ((clocks_hw_t *const)CLOCKS_BASE) +#endif diff --git a/lib/rp2040/hardware/structs/dma.h b/lib/rp2040/hardware/structs/dma.h new file mode 100644 index 00000000..06cdf792 --- /dev/null +++ b/lib/rp2040/hardware/structs/dma.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_DMA_H +#define _HARDWARE_STRUCTS_DMA_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/dma.h" + +typedef struct { + io_rw_32 read_addr; + io_rw_32 write_addr; + io_rw_32 transfer_count; + io_rw_32 ctrl_trig; + io_rw_32 al1_ctrl; + io_rw_32 al1_read_addr; + io_rw_32 al1_write_addr; + io_rw_32 al1_transfer_count_trig; + io_rw_32 al2_ctrl; + io_rw_32 al2_transfer_count; + io_rw_32 al2_read_addr; + io_rw_32 al2_write_addr_trig; + io_rw_32 al3_ctrl; + io_rw_32 al3_write_addr; + io_rw_32 al3_transfer_count; + io_rw_32 al3_read_addr_trig; +} dma_channel_hw_t; + +typedef struct { + dma_channel_hw_t ch[NUM_DMA_CHANNELS]; + uint32_t _pad0[16 * (16 - NUM_DMA_CHANNELS)]; + io_ro_32 intr; + io_rw_32 inte0; + io_rw_32 intf0; + io_rw_32 ints0; + uint32_t _pad1[1]; + io_rw_32 inte1; + io_rw_32 intf1; + io_rw_32 ints1; + io_rw_32 timer[4]; + io_wo_32 multi_channel_trigger; + io_rw_32 sniff_ctrl; + io_rw_32 sniff_data; + uint32_t _pad2[1]; + io_ro_32 fifo_levels; + io_wo_32 abort; +} dma_hw_t; + +typedef struct { + struct dma_debug_hw_channel { + io_ro_32 ctrdeq; + io_ro_32 tcr; + uint32_t pad[14]; + } ch[NUM_DMA_CHANNELS]; +} dma_debug_hw_t; + +#define dma_hw ((dma_hw_t *const)DMA_BASE) +#define dma_debug_hw ((dma_debug_hw_t *const)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET)) + +#endif diff --git a/lib/rp2040/hardware/structs/i2c.h b/lib/rp2040/hardware/structs/i2c.h new file mode 100644 index 00000000..1a58c50d --- /dev/null +++ b/lib/rp2040/hardware/structs/i2c.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_I2C_H +#define _HARDWARE_STRUCTS_I2C_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/i2c.h" + +typedef struct { + io_rw_32 con; + io_rw_32 tar; + io_rw_32 sar; + uint32_t _pad0; + io_rw_32 data_cmd; + io_rw_32 ss_scl_hcnt; + io_rw_32 ss_scl_lcnt; + io_rw_32 fs_scl_hcnt; + io_rw_32 fs_scl_lcnt; + uint32_t _pad1[2]; + io_rw_32 intr_stat; + io_rw_32 intr_mask; + io_rw_32 raw_intr_stat; + io_rw_32 rx_tl; + io_rw_32 tx_tl; + io_rw_32 clr_intr; + io_rw_32 clr_rx_under; + io_rw_32 clr_rx_over; + io_rw_32 clr_tx_over; + io_rw_32 clr_rd_req; + io_rw_32 clr_tx_abrt; + io_rw_32 clr_rx_done; + io_rw_32 clr_activity; + io_rw_32 clr_stop_det; + io_rw_32 clr_start_det; + io_rw_32 clr_gen_call; + io_rw_32 enable; + io_rw_32 status; + io_rw_32 txflr; + io_rw_32 rxflr; + io_rw_32 sda_hold; + io_rw_32 tx_abrt_source; + io_rw_32 slv_data_nack_only; + io_rw_32 dma_cr; + io_rw_32 dma_tdlr; + io_rw_32 dma_rdlr; + io_rw_32 sda_setup; + io_rw_32 ack_general_call; + io_rw_32 enable_status; + io_rw_32 fs_spklen; + uint32_t _pad2; + io_rw_32 clr_restart_det; +} i2c_hw_t; + +#define i2c0_hw ((i2c_hw_t *const)I2C0_BASE) +#define i2c1_hw ((i2c_hw_t *const)I2C1_BASE) + +// List of configuration constants for the Synopsys I2C hardware (you may see +// references to these in I2C register header; these are *fixed* values, +// set at hardware design time): + +// IC_ULTRA_FAST_MODE ................ 0x0 +// IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 +// IC_UFM_SCL_LOW_COUNT .............. 0x0008 +// IC_UFM_SCL_HIGH_COUNT ............. 0x0006 +// IC_TX_TL .......................... 0x0 +// IC_TX_CMD_BLOCK ................... 0x1 +// IC_HAS_DMA ........................ 0x1 +// IC_HAS_ASYNC_FIFO ................. 0x0 +// IC_SMBUS_ARP ...................... 0x0 +// IC_FIRST_DATA_BYTE_STATUS ......... 0x1 +// IC_INTR_IO ........................ 0x1 +// IC_MASTER_MODE .................... 0x1 +// IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 +// IC_INTR_POL ....................... 0x1 +// IC_OPTIONAL_SAR ................... 0x0 +// IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 +// IC_DEFAULT_SLAVE_ADDR ............. 0x055 +// IC_DEFAULT_HS_SPKLEN .............. 0x1 +// IC_FS_SCL_HIGH_COUNT .............. 0x0006 +// IC_HS_SCL_LOW_COUNT ............... 0x0008 +// IC_DEVICE_ID_VALUE ................ 0x0 +// IC_10BITADDR_MASTER ............... 0x0 +// IC_CLK_FREQ_OPTIMIZATION .......... 0x0 +// IC_DEFAULT_FS_SPKLEN .............. 0x7 +// IC_ADD_ENCODED_PARAMS ............. 0x0 +// IC_DEFAULT_SDA_HOLD ............... 0x000001 +// IC_DEFAULT_SDA_SETUP .............. 0x64 +// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 +// IC_CLOCK_PERIOD ................... 100 +// IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 +// IC_RESTART_EN ..................... 0x1 +// IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 +// IC_BUS_CLEAR_FEATURE .............. 0x0 +// IC_CAP_LOADING .................... 100 +// IC_FS_SCL_LOW_COUNT ............... 0x000d +// APB_DATA_WIDTH .................... 32 +// IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff +// IC_SLV_DATA_NACK_ONLY ............. 0x1 +// IC_10BITADDR_SLAVE ................ 0x0 +// IC_CLK_TYPE ....................... 0x0 +// IC_SMBUS_UDID_MSB ................. 0x0 +// IC_SMBUS_SUSPEND_ALERT ............ 0x0 +// IC_HS_SCL_HIGH_COUNT .............. 0x0006 +// IC_SLV_RESTART_DET_EN ............. 0x1 +// IC_SMBUS .......................... 0x0 +// IC_OPTIONAL_SAR_DEFAULT ........... 0x0 +// IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 +// IC_USE_COUNTS ..................... 0x0 +// IC_RX_BUFFER_DEPTH ................ 16 +// IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff +// IC_RX_FULL_HLD_BUS_EN ............. 0x1 +// IC_SLAVE_DISABLE .................. 0x1 +// IC_RX_TL .......................... 0x0 +// IC_DEVICE_ID ...................... 0x0 +// IC_HC_COUNT_VALUES ................ 0x0 +// I2C_DYNAMIC_TAR_UPDATE ............ 0 +// IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff +// IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff +// IC_HS_MASTER_CODE ................. 0x1 +// IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff +// IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff +// IC_SS_SCL_HIGH_COUNT .............. 0x0028 +// IC_SS_SCL_LOW_COUNT ............... 0x002f +// IC_MAX_SPEED_MODE ................. 0x2 +// IC_STAT_FOR_CLK_STRETCH ........... 0x0 +// IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 +// IC_DEFAULT_UFM_SPKLEN ............. 0x1 +// IC_TX_BUFFER_DEPTH ................ 16 + +#endif diff --git a/lib/rp2040/hardware/structs/interp.h b/lib/rp2040/hardware/structs/interp.h new file mode 100644 index 00000000..68375073 --- /dev/null +++ b/lib/rp2040/hardware/structs/interp.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_INTERP_H +#define _HARDWARE_STRUCTS_INTERP_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/sio.h" + +typedef struct { + io_rw_32 accum[2]; + io_rw_32 base[3]; + io_ro_32 pop[3]; + io_ro_32 peek[3]; + io_rw_32 ctrl[2]; + io_rw_32 add_raw[2]; + io_wo_32 base01; +} interp_hw_t; + +#define interp_hw_array ((interp_hw_t *)(SIO_BASE + SIO_INTERP0_ACCUM0_OFFSET)) +#define interp0_hw (&interp_hw_array[0]) +#define interp1_hw (&interp_hw_array[1]) + +#endif diff --git a/lib/rp2040/hardware/structs/iobank0.h b/lib/rp2040/hardware/structs/iobank0.h new file mode 100644 index 00000000..b19800fa --- /dev/null +++ b/lib/rp2040/hardware/structs/iobank0.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_IOBANK0_H +#define _HARDWARE_STRUCTS_IOBANK0_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/io_bank0.h" + +typedef struct { + io_rw_32 inte[4]; + io_rw_32 intf[4]; + io_rw_32 ints[4]; +} io_irq_ctrl_hw_t; + +/// \tag::iobank0_hw[] +typedef struct { + struct { + io_rw_32 status; + io_rw_32 ctrl; + } io[30]; + io_rw_32 intr[4]; + io_irq_ctrl_hw_t proc0_irq_ctrl; + io_irq_ctrl_hw_t proc1_irq_ctrl; + io_irq_ctrl_hw_t dormant_wake_irq_ctrl; +} iobank0_hw_t; +/// \end::iobank0_hw[] + +#define iobank0_hw ((iobank0_hw_t *const)IO_BANK0_BASE) + +#endif diff --git a/lib/rp2040/hardware/structs/ioqspi.h b/lib/rp2040/hardware/structs/ioqspi.h new file mode 100644 index 00000000..48d08a7c --- /dev/null +++ b/lib/rp2040/hardware/structs/ioqspi.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_IOQSPI_H +#define _HARDWARE_STRUCTS_IOQSPI_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/io_qspi.h" + +typedef struct { + struct { + io_rw_32 status; + io_rw_32 ctrl; + } io[6]; +} ioqspi_hw_t; + +#define ioqspi_hw ((ioqspi_hw_t *const)IO_QSPI_BASE) + +#endif diff --git a/lib/rp2040/hardware/structs/mpu.h b/lib/rp2040/hardware/structs/mpu.h new file mode 100644 index 00000000..34e5c39e --- /dev/null +++ b/lib/rp2040/hardware/structs/mpu.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_MPU_H +#define _HARDWARE_STRUCTS_MPU_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/m0plus.h" + +typedef struct { + io_ro_32 type; + io_rw_32 ctrl; + io_rw_32 rnr; + io_rw_32 rbar; + io_rw_32 rasr; +} mpu_hw_t; + +#define mpu_hw ((mpu_hw_t *const)(PPB_BASE + M0PLUS_MPU_TYPE_OFFSET)) + +#endif diff --git a/lib/rp2040/hardware/structs/pads_qspi.h b/lib/rp2040/hardware/structs/pads_qspi.h new file mode 100644 index 00000000..451d7ebc --- /dev/null +++ b/lib/rp2040/hardware/structs/pads_qspi.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_PADS_QSPI_H +#define _HARDWARE_STRUCTS_PADS_QSPI_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/pads_qspi.h" + +typedef struct { + io_rw_32 voltage_select; + io_rw_32 io[6]; +} pads_qspi_hw_t; + +#define pads_qspi_hw ((pads_qspi_hw_t *const)PADS_QSPI_BASE) + +#endif diff --git a/lib/rp2040/hardware/structs/padsbank0.h b/lib/rp2040/hardware/structs/padsbank0.h new file mode 100644 index 00000000..f56dc401 --- /dev/null +++ b/lib/rp2040/hardware/structs/padsbank0.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_PADSBANK0_H +#define _HARDWARE_STRUCTS_PADSBANK0_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/pads_bank0.h" + +typedef struct { + io_rw_32 voltage_select; + io_rw_32 io[30]; +} padsbank0_hw_t; + +#define padsbank0_hw ((padsbank0_hw_t *)PADS_BANK0_BASE) + +#endif diff --git a/lib/rp2040/hardware/structs/pio.h b/lib/rp2040/hardware/structs/pio.h new file mode 100644 index 00000000..176863bb --- /dev/null +++ b/lib/rp2040/hardware/structs/pio.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_PIO_H +#define _HARDWARE_STRUCTS_PIO_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/pio.h" + +typedef struct { + io_rw_32 ctrl; + io_ro_32 fstat; + io_rw_32 fdebug; + io_ro_32 flevel; + io_wo_32 txf[NUM_PIO_STATE_MACHINES]; + io_ro_32 rxf[NUM_PIO_STATE_MACHINES]; + io_rw_32 irq; + io_wo_32 irq_force; + io_rw_32 input_sync_bypass; + io_rw_32 dbg_padout; + io_rw_32 dbg_padoe; + io_rw_32 dbg_cfginfo; + io_wo_32 instr_mem[32]; + struct pio_sm_hw { + io_rw_32 clkdiv; + io_rw_32 execctrl; + io_rw_32 shiftctrl; + io_ro_32 addr; + io_rw_32 instr; + io_rw_32 pinctrl; + } sm[NUM_PIO_STATE_MACHINES]; + io_rw_32 intr; + io_rw_32 inte0; + io_rw_32 intf0; + io_ro_32 ints0; + io_rw_32 inte1; + io_rw_32 intf1; + io_ro_32 ints1; +} pio_hw_t; + +#define pio0_hw ((pio_hw_t *const)PIO0_BASE) +#define pio1_hw ((pio_hw_t *const)PIO1_BASE) + +#endif diff --git a/lib/rp2040/hardware/structs/pll.h b/lib/rp2040/hardware/structs/pll.h new file mode 100644 index 00000000..4d5b5b78 --- /dev/null +++ b/lib/rp2040/hardware/structs/pll.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_PLL_H +#define _HARDWARE_STRUCTS_PLL_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/pll.h" + +/// \tag::pll_hw[] +typedef struct { + io_rw_32 cs; + io_rw_32 pwr; + io_rw_32 fbdiv_int; + io_rw_32 prim; +} pll_hw_t; + +#define pll_sys_hw ((pll_hw_t *const)PLL_SYS_BASE) +#define pll_usb_hw ((pll_hw_t *const)PLL_USB_BASE) +/// \end::pll_hw[] + +#endif diff --git a/lib/rp2040/hardware/structs/psm.h b/lib/rp2040/hardware/structs/psm.h new file mode 100644 index 00000000..cc9fb97e --- /dev/null +++ b/lib/rp2040/hardware/structs/psm.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_PSM_H +#define _HARDWARE_STRUCTS_PSM_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/psm.h" + +typedef struct { + io_rw_32 frce_on; + io_rw_32 frce_off; + io_rw_32 wdsel; + io_rw_32 done; +} psm_hw_t; + +#define psm_hw ((psm_hw_t *const)PSM_BASE) + +#endif diff --git a/lib/rp2040/hardware/structs/pwm.h b/lib/rp2040/hardware/structs/pwm.h new file mode 100644 index 00000000..54995610 --- /dev/null +++ b/lib/rp2040/hardware/structs/pwm.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_PWM_H +#define _HARDWARE_STRUCTS_PWM_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/pwm.h" + +typedef struct pwm_slice_hw { + io_rw_32 csr; + io_rw_32 div; + io_rw_32 ctr; + io_rw_32 cc; + io_rw_32 top; +} pwm_slice_hw_t; + +typedef struct { + pwm_slice_hw_t slice[NUM_PWM_SLICES]; + io_rw_32 en; + io_rw_32 intr; + io_rw_32 inte; + io_rw_32 intf; + io_rw_32 ints; +} pwm_hw_t; + +#define pwm_hw ((pwm_hw_t *const)PWM_BASE) + +#endif diff --git a/lib/rp2040/hardware/structs/resets.h b/lib/rp2040/hardware/structs/resets.h new file mode 100644 index 00000000..a96ddebd --- /dev/null +++ b/lib/rp2040/hardware/structs/resets.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_RESETS_H +#define _HARDWARE_STRUCTS_RESETS_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/resets.h" + +/// \tag::resets_hw[] +typedef struct { + io_rw_32 reset; + io_rw_32 wdsel; + io_rw_32 reset_done; +} resets_hw_t; + +#define resets_hw ((resets_hw_t *const)RESETS_BASE) +/// \end::resets_hw[] + +#endif diff --git a/lib/rp2040/hardware/structs/rosc.h b/lib/rp2040/hardware/structs/rosc.h new file mode 100644 index 00000000..10543937 --- /dev/null +++ b/lib/rp2040/hardware/structs/rosc.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_ROSC_H +#define _HARDWARE_STRUCTS_ROSC_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/rosc.h" + +typedef struct { + io_rw_32 ctrl; + io_rw_32 freqa; + io_rw_32 freqb; + io_rw_32 dormant; + io_rw_32 div; + io_rw_32 phase; + io_rw_32 status; + io_rw_32 randombit; + io_rw_32 count; + io_rw_32 dftx; +} rosc_hw_t; + +#define rosc_hw ((rosc_hw_t *const)ROSC_BASE) + +#endif diff --git a/lib/rp2040/hardware/structs/rtc.h b/lib/rp2040/hardware/structs/rtc.h new file mode 100644 index 00000000..276bd7a2 --- /dev/null +++ b/lib/rp2040/hardware/structs/rtc.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_RTC_H +#define _HARDWARE_STRUCTS_RTC_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/rtc.h" + +typedef struct { + io_rw_32 clkdiv_m1; + io_rw_32 setup_0; + io_rw_32 setup_1; + io_rw_32 ctrl; + io_rw_32 irq_setup_0; + io_rw_32 irq_setup_1; + io_rw_32 rtc_1; + io_rw_32 rtc_0; + io_rw_32 intr; + io_rw_32 inte; + io_rw_32 intf; + io_rw_32 ints; +} rtc_hw_t; + +#define rtc_hw ((rtc_hw_t *const)RTC_BASE) + +#endif diff --git a/lib/rp2040/hardware/structs/scb.h b/lib/rp2040/hardware/structs/scb.h new file mode 100644 index 00000000..b48a8725 --- /dev/null +++ b/lib/rp2040/hardware/structs/scb.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SCB_H +#define _HARDWARE_STRUCTS_SCB_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/m0plus.h" + +// SCB == System Control Block +typedef struct { + io_ro_32 cpuid; + io_rw_32 icsr; + io_rw_32 vtor; + io_rw_32 aircr; + io_rw_32 scr; + // ... +} armv6m_scb_t; + +#define scb_hw ((armv6m_scb_t *const)(PPB_BASE + M0PLUS_CPUID_OFFSET)) + +#endif diff --git a/lib/rp2040/hardware/structs/sio.h b/lib/rp2040/hardware/structs/sio.h new file mode 100644 index 00000000..bc277afc --- /dev/null +++ b/lib/rp2040/hardware/structs/sio.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_SIO_H +#define _HARDWARE_STRUCTS_SIO_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/sio.h" +#include "hardware/structs/interp.h" + +typedef struct { + io_ro_32 cpuid; + io_ro_32 gpio_in; + io_ro_32 gpio_hi_in; + uint32_t _pad; + + io_rw_32 gpio_out; + io_wo_32 gpio_set; + io_wo_32 gpio_clr; + io_wo_32 gpio_togl; + + io_wo_32 gpio_oe; + io_wo_32 gpio_oe_set; + io_wo_32 gpio_oe_clr; + io_wo_32 gpio_oe_togl; + + io_rw_32 gpio_hi_out; + io_wo_32 gpio_hi_set; + io_wo_32 gpio_hi_clr; + io_wo_32 gpio_hi_togl; + + io_wo_32 gpio_hi_oe; + io_wo_32 gpio_hi_oe_set; + io_wo_32 gpio_hi_oe_clr; + io_wo_32 gpio_hi_oe_togl; + + io_rw_32 fifo_st; + io_wo_32 fifo_wr; + io_ro_32 fifo_rd; + io_ro_32 spinlock_st; + + io_rw_32 div_udividend; + io_rw_32 div_udivisor; + io_rw_32 div_sdividend; + io_rw_32 div_sdivisor; + + io_rw_32 div_quotient; + io_rw_32 div_remainder; + io_rw_32 div_csr; + + uint32_t _pad2; + + interp_hw_t interp[2]; +} sio_hw_t; + +#define sio_hw ((sio_hw_t *)SIO_BASE) + +#endif diff --git a/lib/rp2040/hardware/structs/spi.h b/lib/rp2040/hardware/structs/spi.h new file mode 100644 index 00000000..5b3b2bab --- /dev/null +++ b/lib/rp2040/hardware/structs/spi.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_SPI_H +#define _HARDWARE_STRUCTS_SPI_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/spi.h" + +typedef struct { + io_rw_32 cr0; + io_rw_32 cr1; + io_rw_32 dr; + io_rw_32 sr; + io_rw_32 cpsr; + io_rw_32 imsc; + io_rw_32 ris; + io_rw_32 mis; + io_rw_32 icr; + io_rw_32 dmacr; +} spi_hw_t; + +#define spi0_hw ((spi_hw_t *const)SPI0_BASE) +#define spi1_hw ((spi_hw_t *const)SPI1_BASE) + +#endif diff --git a/lib/rp2040/hardware/structs/ssi.h b/lib/rp2040/hardware/structs/ssi.h new file mode 100644 index 00000000..80779fe6 --- /dev/null +++ b/lib/rp2040/hardware/structs/ssi.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_SSI_H +#define _HARDWARE_STRUCTS_SSI_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/ssi.h" + +typedef struct { + io_rw_32 ctrlr0; + io_rw_32 ctrlr1; + io_rw_32 ssienr; + io_rw_32 mwcr; + io_rw_32 ser; + io_rw_32 baudr; + io_rw_32 txftlr; + io_rw_32 rxftlr; + io_rw_32 txflr; + io_rw_32 rxflr; + io_rw_32 sr; + io_rw_32 imr; + io_rw_32 isr; + io_rw_32 risr; + io_rw_32 txoicr; + io_rw_32 rxoicr; + io_rw_32 rxuicr; + io_rw_32 msticr; + io_rw_32 icr; + io_rw_32 dmacr; + io_rw_32 dmatdlr; + io_rw_32 dmardlr; + io_rw_32 idr; + io_rw_32 ssi_version_id; + io_rw_32 dr0; + uint32_t _pad[(0xf0 - 0x60) / 4 - 1]; + io_rw_32 rx_sample_dly; + io_rw_32 spi_ctrlr0; + io_rw_32 txd_drive_edge; +} ssi_hw_t; + +#define ssi_hw ((ssi_hw_t *const)XIP_SSI_BASE) +#endif diff --git a/lib/rp2040/hardware/structs/syscfg.h b/lib/rp2040/hardware/structs/syscfg.h new file mode 100644 index 00000000..0bfc7293 --- /dev/null +++ b/lib/rp2040/hardware/structs/syscfg.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_SYSCFG_H +#define _HARDWARE_STRUCTS_SYSCFG_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/syscfg.h" + +typedef struct { + io_rw_32 proc0_nmi_mask; + io_rw_32 proc1_nmi_mask; + io_rw_32 proc_config; + io_rw_32 proc_in_sync_bypass; + io_rw_32 proc_in_sync_bypass_hi; + io_rw_32 dbgforce; + io_rw_32 mempowerdown; +} syscfg_hw_t; + +#define syscfg_hw ((syscfg_hw_t *const)SYSCFG_BASE) + +#endif diff --git a/lib/rp2040/hardware/structs/systick.h b/lib/rp2040/hardware/structs/systick.h new file mode 100644 index 00000000..24673fbc --- /dev/null +++ b/lib/rp2040/hardware/structs/systick.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_SYSTICK_H +#define _HARDWARE_STRUCTS_SYSTICK_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/m0plus.h" + +typedef struct { + io_rw_32 csr; + io_rw_32 rvr; + io_rw_32 cvr; + io_ro_32 calib; +} systick_hw_t; + +#define systick_hw ((systick_hw_t *const)(PPB_BASE + M0PLUS_SYST_CSR_OFFSET)) + +#endif diff --git a/lib/rp2040/hardware/structs/timer.h b/lib/rp2040/hardware/structs/timer.h new file mode 100644 index 00000000..e051a069 --- /dev/null +++ b/lib/rp2040/hardware/structs/timer.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_TIMER_H +#define _HARDWARE_STRUCTS_TIMER_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/timer.h" + +#define NUM_TIMERS 4 + +typedef struct { + io_wo_32 timehw; + io_wo_32 timelw; + io_ro_32 timehr; + io_ro_32 timelr; + io_rw_32 alarm[NUM_TIMERS]; + io_rw_32 armed; + io_ro_32 timerawh; + io_ro_32 timerawl; + io_rw_32 dbgpause; + io_rw_32 pause; + io_rw_32 intr; + io_rw_32 inte; + io_rw_32 intf; + io_ro_32 ints; +} timer_hw_t; + +#define timer_hw ((timer_hw_t *const)TIMER_BASE) + +#endif diff --git a/lib/rp2040/hardware/structs/uart.h b/lib/rp2040/hardware/structs/uart.h new file mode 100644 index 00000000..42fe8e88 --- /dev/null +++ b/lib/rp2040/hardware/structs/uart.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_UART_H +#define _HARDWARE_STRUCTS_UART_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/uart.h" + +typedef struct { + io_rw_32 dr; + io_rw_32 rsr; + uint32_t _pad0[4]; + io_rw_32 fr; + uint32_t _pad1; + io_rw_32 ilpr; + io_rw_32 ibrd; + io_rw_32 fbrd; + io_rw_32 lcr_h; + io_rw_32 cr; + io_rw_32 ifls; + io_rw_32 imsc; + io_rw_32 ris; + io_rw_32 mis; + io_rw_32 icr; + io_rw_32 dmacr; +} uart_hw_t; + +#define uart0_hw ((uart_hw_t *const)UART0_BASE) +#define uart1_hw ((uart_hw_t *const)UART1_BASE) + +#endif diff --git a/lib/rp2040/hardware/structs/usb.h b/lib/rp2040/hardware/structs/usb.h new file mode 100644 index 00000000..0254e61d --- /dev/null +++ b/lib/rp2040/hardware/structs/usb.h @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_USB_H +#define _HARDWARE_STRUCTS_USB_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/usb.h" + +// 0-15 +#define USB_NUM_ENDPOINTS 16 + +// allow user to restrict number of endpoints available to save RAN +#ifndef USB_MAX_ENDPOINTS +#define USB_MAX_ENDPOINTS USB_NUM_ENDPOINTS +#endif + +// 1-15 +#define USB_HOST_INTERRUPT_ENDPOINTS (USB_NUM_ENDPOINTS - 1) + +// Endpoint buffer control bits +#define USB_BUF_CTRL_FULL 0x00008000u +#define USB_BUF_CTRL_LAST 0x00004000u +#define USB_BUF_CTRL_DATA0_PID 0x00000000u +#define USB_BUF_CTRL_DATA1_PID 0x00002000u +#define USB_BUF_CTRL_SEL 0x00001000u +#define USB_BUF_CTRL_STALL 0x00000800u +#define USB_BUF_CTRL_AVAIL 0x00000400u +#define USB_BUF_CTRL_LEN_MASK 0x000003FFu +#define USB_BUF_CTRL_LEN_LSB 0 + +// ep_inout_ctrl bits +#define EP_CTRL_ENABLE_BITS (1u << 31u) +#define EP_CTRL_DOUBLE_BUFFERED_BITS (1u << 30) +#define EP_CTRL_INTERRUPT_PER_BUFFER (1u << 29) +#define EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER (1u << 28) +#define EP_CTRL_INTERRUPT_ON_NAK (1u << 16) +#define EP_CTRL_INTERRUPT_ON_STALL (1u << 17) +#define EP_CTRL_BUFFER_TYPE_LSB 26 +#define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16 + +#define USB_DPRAM_SIZE 4096 + +// PICO_CONFIG: USB_DPRAM_MAX, Set amount of USB RAM used by USB system, min=0, max=4096, default=4096, group=hardware_usb +// Allow user to claim some of the USB RAM for themselves +#ifndef USB_DPRAM_MAX +#define USB_DPRAM_MAX USB_DPRAM_SIZE +#endif + +// Define maximum packet sizes +#define USB_MAX_ISO_PACKET_SIZE 1023 +#define USB_MAX_PACKET_SIZE 64 + +typedef struct { + // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses + volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets + + // Starts at ep1 + struct usb_device_dpram_ep_ctrl { + io_rw_32 in; + io_rw_32 out; + } ep_ctrl[USB_NUM_ENDPOINTS - 1]; + + // Starts at ep0 + struct usb_device_dpram_ep_buf_ctrl { + io_rw_32 in; + io_rw_32 out; + } ep_buf_ctrl[USB_NUM_ENDPOINTS]; + + // EP0 buffers are fixed. Assumes single buffered mode for EP0 + uint8_t ep0_buf_a[0x40]; + uint8_t ep0_buf_b[0x40]; + + // Rest of DPRAM can be carved up as needed + uint8_t epx_data[USB_DPRAM_MAX - 0x180]; +} usb_device_dpram_t; + +static_assert(sizeof(usb_device_dpram_t) == USB_DPRAM_MAX, ""); +static_assert(offsetof(usb_device_dpram_t, epx_data) == 0x180, ""); + +typedef struct { + // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses + volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets + + // Interrupt endpoint control 1 -> 15 + struct usb_host_dpram_ep_ctrl { + io_rw_32 ctrl; + io_rw_32 spare; + } int_ep_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; + + io_rw_32 epx_buf_ctrl; + io_rw_32 _spare0; + + // Interrupt endpoint buffer control + struct usb_host_dpram_ep_buf_ctrl { + io_rw_32 ctrl; + io_rw_32 spare; + } int_ep_buffer_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; + + io_rw_32 epx_ctrl; + + uint8_t _spare1[124]; + + // Should start at 0x180 + uint8_t epx_data[USB_DPRAM_MAX - 0x180]; +} usb_host_dpram_t; + +static_assert(sizeof(usb_host_dpram_t) == USB_DPRAM_MAX, ""); +static_assert(offsetof(usb_host_dpram_t, epx_data) == 0x180, ""); + +typedef struct { + io_rw_32 dev_addr_ctrl; + io_rw_32 int_ep_addr_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; + io_rw_32 main_ctrl; + io_rw_32 sof_rw; + io_ro_32 sof_rd; + io_rw_32 sie_ctrl; + io_rw_32 sie_status; + io_rw_32 int_ep_ctrl; + io_rw_32 buf_status; + io_rw_32 buf_cpu_should_handle; // for double buff + io_rw_32 abort; + io_rw_32 abort_done; + io_rw_32 ep_stall_arm; + io_rw_32 nak_poll; + io_rw_32 ep_nak_stall_status; + io_rw_32 muxing; + io_rw_32 pwr; + io_rw_32 phy_direct; + io_rw_32 phy_direct_override; + io_rw_32 phy_trim; + io_rw_32 linestate_tuning; + io_rw_32 intr; + io_rw_32 inte; + io_rw_32 intf; + io_rw_32 ints; +} usb_hw_t; + +check_hw_layout(usb_hw_t, ints, USB_INTS_OFFSET); + +#define usb_hw ((usb_hw_t *)USBCTRL_REGS_BASE) + +#define usb_dpram ((usb_device_dpram_t *)USBCTRL_DPRAM_BASE) +#define usbh_dpram ((usb_host_dpram_t *)USBCTRL_DPRAM_BASE) + +#endif diff --git a/lib/rp2040/hardware/structs/vreg_and_chip_reset.h b/lib/rp2040/hardware/structs/vreg_and_chip_reset.h new file mode 100644 index 00000000..9956d683 --- /dev/null +++ b/lib/rp2040/hardware/structs/vreg_and_chip_reset.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H +#define _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/vreg_and_chip_reset.h" + +typedef struct { + io_rw_32 vreg; + io_rw_32 bod; + io_rw_32 chip_reset; +} vreg_and_chip_reset_hw_t; + +#define vreg_and_chip_reset_hw ((vreg_and_chip_reset_hw_t *const)VREG_AND_CHIP_RESET_BASE) + +#endif diff --git a/lib/rp2040/hardware/structs/watchdog.h b/lib/rp2040/hardware/structs/watchdog.h new file mode 100644 index 00000000..2cf05f19 --- /dev/null +++ b/lib/rp2040/hardware/structs/watchdog.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_WATCHDOG_H +#define _HARDWARE_STRUCTS_WATCHDOG_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/watchdog.h" + +typedef struct { + io_rw_32 ctrl; + io_wo_32 load; + io_ro_32 reason; + io_rw_32 scratch[8]; + io_rw_32 tick; +} watchdog_hw_t; + +#define watchdog_hw ((watchdog_hw_t *const)WATCHDOG_BASE) + +#endif diff --git a/lib/rp2040/hardware/structs/xip_ctrl.h b/lib/rp2040/hardware/structs/xip_ctrl.h new file mode 100644 index 00000000..bfa5b1c0 --- /dev/null +++ b/lib/rp2040/hardware/structs/xip_ctrl.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_XIP_CTRL_H +#define _HARDWARE_STRUCTS_XIP_CTRL_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/xip.h" + +typedef struct { + io_rw_32 ctrl; + io_rw_32 flush; + io_rw_32 stat; + io_rw_32 ctr_hit; + io_rw_32 ctr_acc; + io_rw_32 stream_addr; + io_rw_32 stream_ctr; + io_rw_32 stream_fifo; +} xip_ctrl_hw_t; + +#define XIP_STAT_FIFO_FULL 0x4u +#define XIP_STAT_FIFO_EMPTY 0x2u +#define XIP_STAT_FLUSH_RDY 0x1u + +#define xip_ctrl_hw ((xip_ctrl_hw_t *const)XIP_CTRL_BASE) + +#endif diff --git a/lib/rp2040/hardware/structs/xosc.h b/lib/rp2040/hardware/structs/xosc.h new file mode 100644 index 00000000..698e6a2f --- /dev/null +++ b/lib/rp2040/hardware/structs/xosc.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_XOSC_H +#define _HARDWARE_STRUCTS_XOSC_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/xosc.h" + +/// \tag::xosc_hw[] +typedef struct { + io_rw_32 ctrl; + io_rw_32 status; + io_rw_32 dormant; + io_rw_32 startup; + io_rw_32 _reserved[3]; + io_rw_32 count; +} xosc_hw_t; + +#define xosc_hw ((xosc_hw_t *const)XOSC_BASE) +/// \end::xosc_hw[] + +#endif |