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Diffstat (limited to 'docs')
| -rw-r--r-- | docs/Config_Reference.md | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/docs/Config_Reference.md b/docs/Config_Reference.md index a06b928c..94379a75 100644 --- a/docs/Config_Reference.md +++ b/docs/Config_Reference.md @@ -4729,13 +4729,30 @@ data_ready_pin: #gain: 128 # Valid gain values are 128, 64, 32, 16, 8, 4, 2, 1 # The default is 128 +#pga_bypass: False +# Disable the internal Programmable Gain Amplifier. If +# True the PGA will be disabled for gains 1, 2, and 4. The PGA is always +# enabled for gain settings 8 to 128, regardless of the pga_bypass setting. +# If AVSS is used as an input pga_bypass is forced to True. +# The default is False. #sample_rate: 660 # This chip supports two ranges of sample rates, Normal and Turbo. In turbo -# mode the chips c internal clock runs twice as fast and the SPI communication +# mode the chip's internal clock runs twice as fast and the SPI communication # speed is also doubled. # Normal sample rates: 20, 45, 90, 175, 330, 600, 1000 # Turbo sample rates: 40, 90, 180, 350, 660, 1200, 2000 # The default is 660 +#input_mux: +# Input multiplexer configuration, select a pair of pins to use. The first pin +# is the positive, AINP, and the second pin is the negative, AINN. Valid +# values are: 'AIN0_AIN1', 'AIN0_AIN2', 'AIN0_AIN3', 'AIN1_AIN2', 'AIN1_AIN3', +# 'AIN2_AIN3', 'AIN1_AIN0', 'AIN3_AIN2', 'AIN0_AVSS', 'AIN1_AVSS', 'AIN2_AVSS' +# and 'AIN3_AVSS'. If AVSS is used the PGA is bypassed and the pga_bypass +# setting will be forced to True. +# The default is AIN0_AIN1. +#vref: +# The selected voltage reference. Valid values are: 'internal', 'REF0', 'REF1' +# and 'analog_supply'. Default is 'internal'. ``` ## Board specific hardware support |