diff options
| -rw-r--r-- | src/stm32/adc.c | 6 | ||||
| -rw-r--r-- | src/stm32/stm32f1.c | 2 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/stm32/adc.c b/src/stm32/adc.c index 03d599b2..9f1a6d53 100644 --- a/src/stm32/adc.c +++ b/src/stm32/adc.c @@ -35,7 +35,7 @@ static const uint8_t adc_pins[] = { #endif // ADC timing: -// stm32f103: ADC clock=9Mhz, Tconv=12.5, Tsamp=41.5, total=6.000us +// stm32f103: ADC clock=4.5Mhz, Tconv=12.5, Tsamp=41.5, total=12.000us // stm32f407: ADC clock=21Mhz, Tconv=12, Tsamp=84, total=4.571us // stm32f446: ADC clock=22.5Mhz, Tconv=12, Tsamp=84, total=4.267us @@ -83,7 +83,7 @@ gpio_adc_setup(uint32_t pin) if (!is_enabled_pclock(adc_base)) { enable_pclock(adc_base); adc_calibrate(adc); - uint32_t aticks = 4; // 4-6us sample time (depending on stm32 chip) + uint32_t aticks = 4; // 4-12us sample time (depending on stm32 chip) adc->SMPR1 = (aticks | (aticks << 3) | (aticks << 6) | (aticks << 9) | (aticks << 12) | (aticks << 15) | (aticks << 18) | (aticks << 21) @@ -119,7 +119,7 @@ gpio_adc_sample(struct gpio_adc g) adc->CR2 = ADC_CR2_SWSTART | CR2_FLAGS; need_delay: - return timer_from_us(10); + return timer_from_us(20); } // Read a value; use only after gpio_adc_sample() returns zero diff --git a/src/stm32/stm32f1.c b/src/stm32/stm32f1.c index e5c18a83..97a6ade4 100644 --- a/src/stm32/stm32f1.c +++ b/src/stm32/stm32f1.c @@ -140,7 +140,7 @@ clock_setup(void) cfgr = ((0 << RCC_CFGR_PLLSRC_Pos) | ((div2 - 2) << RCC_CFGR_PLLMULL_Pos)); } - cfgr |= RCC_CFGR_PPRE1_DIV2 | RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_ADCPRE_DIV4; + cfgr |= RCC_CFGR_PPRE1_DIV2 | RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_ADCPRE_DIV8; RCC->CFGR = cfgr; RCC->CR |= RCC_CR_PLLON; |