diff options
| -rw-r--r-- | src/sam4e8e/Makefile | 2 | ||||
| -rw-r--r-- | src/sam4e8e/afec.c | 218 | ||||
| -rw-r--r-- | src/sam4e8e/gpio.c | 210 | ||||
| -rw-r--r-- | src/sam4e8e/gpio.h | 1 |
4 files changed, 219 insertions, 212 deletions
diff --git a/src/sam4e8e/Makefile b/src/sam4e8e/Makefile index f9aa3f0c..19d270d6 100644 --- a/src/sam4e8e/Makefile +++ b/src/sam4e8e/Makefile @@ -21,7 +21,7 @@ src-y += ../lib/cmsis-sam4e/gcc/system_sam4e.c \ src-$(CONFIG_HAVE_GPIO_SPI) += sam4e8e/spi.c src-$(CONFIG_HAVE_GPIO_I2C) += sam4e8e/i2c.c src-$(CONFIG_SERIAL) += sam4e8e/serial.c generic/serial_irq.c -src-$(CONFIG_HAVE_GPIO) += sam4e8e/gpio.c +src-$(CONFIG_HAVE_GPIO) += sam4e8e/gpio.c sam4e8e/afec.c src-y += generic/crc16_ccitt.c generic/alloc.c src-y += generic/armcm_irq.c generic/timer_irq.c src-y += sam4e8e/main.c sam4e8e/timer.c diff --git a/src/sam4e8e/afec.c b/src/sam4e8e/afec.c new file mode 100644 index 00000000..f9a499bb --- /dev/null +++ b/src/sam4e8e/afec.c @@ -0,0 +1,218 @@ +// SAM4e8e Analog Front-End Converter (AFEC) support +// +// Copyright (C) 2018 Florian Heilmann <Florian.Heilmann@gmx.net> +// +// This file may be distributed under the terms of the GNU GPLv3 license. + +#include "autoconf.h" // CONFIG_CLOCK_FREQ +#include "command.h" // shutdown +#include "gpio.h" // gpio_adc_setup +#include "internal.h" // GPIO +#include "sam4e.h" // AFEC0 +#include "sched.h" // sched_shutdown + +static const uint8_t afec0_pins[] = { + //remove first channel, since it offsets the channel number: GPIO('A', 8), + GPIO('A', 17), GPIO('A', 18), GPIO('A', 19), + GPIO('A', 20), GPIO('B', 0), GPIO('B', 1), GPIO('C', 13), + GPIO('C', 15), GPIO('C', 12), GPIO('C', 29), GPIO('C', 30), + GPIO('C', 31), GPIO('C', 26), GPIO('C', 27), GPIO('C',0) +}; + +static const uint8_t afec1_pins[] = { + GPIO('B', 2), GPIO('B', 3), GPIO('A', 21), GPIO('A', 22), + GPIO('C', 1), GPIO('C', 2), GPIO('C', 3), GPIO('C', 4), + /* Artificially pad this array so we can safely iterate over it */ + GPIO('B', 2), GPIO('B', 2), GPIO('B', 2), GPIO('B', 2), + GPIO('B', 2), GPIO('B', 2), GPIO('B', 2), GPIO('B', 2) +}; + +#define ADC_FREQ_MAX 6000000UL +DECL_CONSTANT(ADC_MAX, 4095); + +static inline struct gpio_adc +gpio_pin_to_afec(uint8_t pin) +{ + int chan; + Afec* afec_device; + + for (chan=0; ; chan++) { + if (chan >= ARRAY_SIZE(afec0_pins)) + shutdown("Not a valid ADC pin"); + if (afec0_pins[chan] == pin) { + afec_device = AFEC0; + break; + } + if (afec1_pins[chan] == pin) { + afec_device = AFEC1; + break; + } + } + return (struct gpio_adc){.pin=pin, .chan=chan, .afec=afec_device}; +} + +static int +init_afec(Afec* afec) { + + // Enable PMC + if (afec == AFEC0) + PMC->PMC_PCER0 = 1 << ID_AFEC0; + else + PMC->PMC_PCER0 = 1 << ID_AFEC1; + + // If busy, return busy + if ((afec->AFE_ISR & AFE_ISR_DRDY) == AFE_ISR_DRDY) { + return -1; + } + + // Reset + afec->AFE_CR = AFE_CR_SWRST; + + // Configure afec + afec->AFE_MR = AFE_MR_ANACH_ALLOWED | \ + AFE_MR_PRESCAL (SystemCoreClock / (2 * ADC_FREQ_MAX) -1) | \ + AFE_MR_SETTLING_AST3 | \ + AFE_MR_TRACKTIM(2) | \ + AFE_MR_TRANSFER(1) | \ + AFE_MR_STARTUP_SUT64; + afec->AFE_EMR = AFE_EMR_TAG | \ + AFE_EMR_RES_NO_AVERAGE | \ + AFE_EMR_STM; + afec->AFE_ACR = AFE_ACR_IBCTL(1); + + // Disable interrupts + afec->AFE_IDR = 0xDF00803F; + + // Disable SW triggering + uint32_t mr = afec->AFE_MR; + + mr &= ~(AFE_MR_TRGSEL_Msk | AFE_MR_TRGEN | AFE_MR_FREERUN_ON); + mr |= AFE_MR_TRGEN_DIS; + afec->AFE_MR = mr; + + return 0; +} + +void +gpio_afec_init(void) { + + while(init_afec(AFEC0) != 0) { + (void)(AFEC0->AFE_LCDR & AFE_LCDR_LDATA_Msk); + } + while(init_afec(AFEC1) != 0) { + (void)(AFEC1->AFE_LCDR & AFE_LCDR_LDATA_Msk); + } + +} +DECL_INIT(gpio_afec_init); + +struct gpio_adc +gpio_adc_setup(uint8_t pin) +{ + struct gpio_adc adc_pin = gpio_pin_to_afec(pin); + Afec *afec = adc_pin.afec; + + //config channel + uint32_t reg = afec->AFE_DIFFR; + reg &= ~(1u << adc_pin.chan); + afec->AFE_DIFFR = reg; + reg = afec->AFE_CGR; + reg &= ~(0x03u << (2 * adc_pin.chan)); + reg |= 1 << (2 * adc_pin.chan); + afec->AFE_CGR = reg; + + // Configure channel + // afec_ch_get_config_defaults(&ch_cfg); + // afec_ch_set_config(adc_pin.afec, adc_pin.chan, &ch_cfg); + // Remove default internal offset from channel + // See Atmel Appnote AT03078 Section 1.5 + afec->AFE_CSELR = adc_pin.chan; + afec->AFE_COCR = (0x800 & AFE_COCR_AOFF_Msk); + + // Enable and calibrate Channel + afec->AFE_CHER = 1 << adc_pin.chan; + + reg = afec->AFE_CHSR; + afec->AFE_CDOR = reg; + afec->AFE_CR = AFE_CR_AUTOCAL; + + return adc_pin; +} + +enum { AFE_DUMMY=0xff }; +uint8_t active_channel_afec0 = AFE_DUMMY; +uint8_t active_channel_afec1 = AFE_DUMMY; + +static inline uint8_t +get_active_afec_channel(Afec* afec) { + if (afec == AFEC0) { + return active_channel_afec0; + } + return active_channel_afec1; +} + +static inline void +set_active_afec_channel(Afec* afec, uint8_t chan) { + if (afec == AFEC0) { + active_channel_afec0 = chan; + } else { + active_channel_afec1 = chan; + } +} + +// Try to sample a value. Returns zero if sample ready, otherwise +// returns the number of clock ticks the caller should wait before +// retrying this function. +uint32_t +gpio_adc_sample(struct gpio_adc g) +{ + Afec* afec = g.afec; + if (get_active_afec_channel(afec) == g.chan) { + if ((afec->AFE_ISR & AFE_ISR_DRDY) && (afec->AFE_ISR & (1 << g.chan))) { + // Sample now ready + return 0; + } else { + // Busy + goto need_delay; + } + } else if (get_active_afec_channel(g.afec) != AFE_DUMMY) { + goto need_delay; + } + + afec->AFE_CHDR = 0x803F; // Disable all channels + afec->AFE_CHER = 1 << g.chan; + + set_active_afec_channel(afec, g.chan); + + for (uint32_t chan = 0; chan < 16; ++chan) + { + if ((afec->AFE_ISR & (1 << chan)) != 0) + { + afec->AFE_CSELR = chan; + (void)(afec->AFE_CDR); + } + } + afec->AFE_CR = AFE_CR_START; + +need_delay: + return ADC_FREQ_MAX * 10000ULL / CONFIG_CLOCK_FREQ; // about 400 mcu clock cycles or 40 afec cycles +} + +// Read a value; use only after gpio_adc_sample() returns zero +uint16_t +gpio_adc_read(struct gpio_adc g) +{ + Afec *afec = g.afec; + set_active_afec_channel(g.afec, AFE_DUMMY); + afec->AFE_CSELR = g.chan; + return afec->AFE_CDR; +} + +// Cancel a sample that may have been started with gpio_adc_sample() +void +gpio_adc_cancel_sample(struct gpio_adc g) +{ + if (get_active_afec_channel(g.afec) == g.chan) { + set_active_afec_channel(g.afec, AFE_DUMMY); + } +} diff --git a/src/sam4e8e/gpio.c b/src/sam4e8e/gpio.c index 11516e44..3e2c9796 100644 --- a/src/sam4e8e/gpio.c +++ b/src/sam4e8e/gpio.c @@ -4,7 +4,6 @@ // // This file may be distributed under the terms of the GNU GPLv3 license. -#include "autoconf.h" // CONFIG_CLOCK_FREQ #include "board/irq.h" // irq_save #include "command.h" // shutdown #include "gpio.h" // gpio_out_setup @@ -172,212 +171,3 @@ gpio_in_read(struct gpio_in g) Pio *regs = g.regs; return !!(regs->PIO_PDSR & g.bit); } - -/**************************************************************** - * Analog Front-End Converter (AFEC) pins (see datasheet sec. 43.5) - ****************************************************************/ -static const uint8_t afec0_pins[] = { - //remove first channel, since it offsets the channel number: GPIO('A', 8), - GPIO('A', 17), GPIO('A', 18), GPIO('A', 19), - GPIO('A', 20), GPIO('B', 0), GPIO('B', 1), GPIO('C', 13), - GPIO('C', 15), GPIO('C', 12), GPIO('C', 29), GPIO('C', 30), - GPIO('C', 31), GPIO('C', 26), GPIO('C', 27), GPIO('C',0) -}; - -static const uint8_t afec1_pins[] = { - GPIO('B', 2), GPIO('B', 3), GPIO('A', 21), GPIO('A', 22), - GPIO('C', 1), GPIO('C', 2), GPIO('C', 3), GPIO('C', 4), - /* Artificially pad this array so we can safely iterate over it */ - GPIO('B', 2), GPIO('B', 2), GPIO('B', 2), GPIO('B', 2), - GPIO('B', 2), GPIO('B', 2), GPIO('B', 2), GPIO('B', 2) -}; - -#define ADC_FREQ_MAX 6000000UL -DECL_CONSTANT(ADC_MAX, 4095); - -inline struct gpio_adc -gpio_pin_to_afec(uint8_t pin) -{ - int chan; - Afec* afec_device; - - for (chan=0; ; chan++) { - if (chan >= ARRAY_SIZE(afec0_pins)) - shutdown("Not a valid ADC pin"); - if (afec0_pins[chan] == pin) { - afec_device = AFEC0; - break; - } - if (afec1_pins[chan] == pin) { - afec_device = AFEC1; - break; - } - } - return (struct gpio_adc){.pin=pin, .chan=chan, .afec=afec_device}; -} - -int -init_afec(Afec* afec) { - - // Enable PMC - if (afec == AFEC0) - PMC->PMC_PCER0 = 1 << ID_AFEC0; - else - PMC->PMC_PCER0 = 1 << ID_AFEC1; - - // If busy, return busy - if ((afec->AFE_ISR & AFE_ISR_DRDY) == AFE_ISR_DRDY) { - return -1; - } - - // Reset - afec->AFE_CR = AFE_CR_SWRST; - - // Configure afec - afec->AFE_MR = AFE_MR_ANACH_ALLOWED | \ - AFE_MR_PRESCAL (SystemCoreClock / (2 * ADC_FREQ_MAX) -1) | \ - AFE_MR_SETTLING_AST3 | \ - AFE_MR_TRACKTIM(2) | \ - AFE_MR_TRANSFER(1) | \ - AFE_MR_STARTUP_SUT64; - afec->AFE_EMR = AFE_EMR_TAG | \ - AFE_EMR_RES_NO_AVERAGE | \ - AFE_EMR_STM; - afec->AFE_ACR = AFE_ACR_IBCTL(1); - - // Disable interrupts - afec->AFE_IDR = 0xDF00803F; - - // Disable SW triggering - uint32_t mr = afec->AFE_MR; - - mr &= ~(AFE_MR_TRGSEL_Msk | AFE_MR_TRGEN | AFE_MR_FREERUN_ON); - mr |= AFE_MR_TRGEN_DIS; - afec->AFE_MR = mr; - - return 0; -} - -void -gpio_afec_init(void) { - - while(init_afec(AFEC0) != 0) { - (void)(AFEC0->AFE_LCDR & AFE_LCDR_LDATA_Msk); - } - while(init_afec(AFEC1) != 0) { - (void)(AFEC1->AFE_LCDR & AFE_LCDR_LDATA_Msk); - } - -} -DECL_INIT(gpio_afec_init); - -struct gpio_adc -gpio_adc_setup(uint8_t pin) -{ - struct gpio_adc adc_pin = gpio_pin_to_afec(pin); - Afec *afec = adc_pin.afec; - - //config channel - uint32_t reg = afec->AFE_DIFFR; - reg &= ~(1u << adc_pin.chan); - afec->AFE_DIFFR = reg; - reg = afec->AFE_CGR; - reg &= ~(0x03u << (2 * adc_pin.chan)); - reg |= 1 << (2 * adc_pin.chan); - afec->AFE_CGR = reg; - - // Configure channel - // afec_ch_get_config_defaults(&ch_cfg); - // afec_ch_set_config(adc_pin.afec, adc_pin.chan, &ch_cfg); - // Remove default internal offset from channel - // See Atmel Appnote AT03078 Section 1.5 - afec->AFE_CSELR = adc_pin.chan; - afec->AFE_COCR = (0x800 & AFE_COCR_AOFF_Msk); - - // Enable and calibrate Channel - afec->AFE_CHER = 1 << adc_pin.chan; - - reg = afec->AFE_CHSR; - afec->AFE_CDOR = reg; - afec->AFE_CR = AFE_CR_AUTOCAL; - - return adc_pin; -} - -enum { AFE_DUMMY=0xff }; -uint8_t active_channel_afec0 = AFE_DUMMY; -uint8_t active_channel_afec1 = AFE_DUMMY; - -inline uint8_t -get_active_afec_channel(Afec* afec) { - if (afec == AFEC0) { - return active_channel_afec0; - } - return active_channel_afec1; -} - -inline void -set_active_afec_channel(Afec* afec, uint8_t chan) { - if (afec == AFEC0) { - active_channel_afec0 = chan; - } else { - active_channel_afec1 = chan; - } -} - -// Try to sample a value. Returns zero if sample ready, otherwise -// returns the number of clock ticks the caller should wait before -// retrying this function. -uint32_t -gpio_adc_sample(struct gpio_adc g) -{ - Afec* afec = g.afec; - if (get_active_afec_channel(afec) == g.chan) { - if ((afec->AFE_ISR & AFE_ISR_DRDY) && (afec->AFE_ISR & (1 << g.chan))) { - // Sample now ready - return 0; - } else { - // Busy - goto need_delay; - } - } else if (get_active_afec_channel(g.afec) != AFE_DUMMY) { - goto need_delay; - } - - afec->AFE_CHDR = 0x803F; // Disable all channels - afec->AFE_CHER = 1 << g.chan; - - set_active_afec_channel(afec, g.chan); - - for (uint32_t chan = 0; chan < 16; ++chan) - { - if ((afec->AFE_ISR & (1 << chan)) != 0) - { - afec->AFE_CSELR = chan; - (void)(afec->AFE_CDR); - } - } - afec->AFE_CR = AFE_CR_START; - -need_delay: - return ADC_FREQ_MAX * 10000ULL / CONFIG_CLOCK_FREQ; // about 400 mcu clock cycles or 40 afec cycles -} - -// Read a value; use only after gpio_adc_sample() returns zero -uint16_t -gpio_adc_read(struct gpio_adc g) -{ - Afec *afec = g.afec; - set_active_afec_channel(g.afec, AFE_DUMMY); - afec->AFE_CSELR = g.chan; - return afec->AFE_CDR; -} - -// Cancel a sample that may have been started with gpio_adc_sample() -void -gpio_adc_cancel_sample(struct gpio_adc g) -{ - if (get_active_afec_channel(g.afec) == g.chan) { - set_active_afec_channel(g.afec, AFE_DUMMY); - } -} diff --git a/src/sam4e8e/gpio.h b/src/sam4e8e/gpio.h index 95c06002..addd41b0 100644 --- a/src/sam4e8e/gpio.h +++ b/src/sam4e8e/gpio.h @@ -31,7 +31,6 @@ struct gpio_adc { uint32_t chan; }; -struct gpio_adc gpio_pin_to_afec(uint8_t pin); struct gpio_adc gpio_adc_setup(uint8_t pin); uint32_t gpio_adc_sample(struct gpio_adc g); uint16_t gpio_adc_read(struct gpio_adc g); |