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| author | Matt Shepcar <matt@shepcar.co.uk> | 2021-01-24 15:24:11 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-01-24 10:24:11 -0500 |
| commit | ccaf58a02cf132cb43ad3f45f5200841044f66a8 (patch) | |
| tree | 21eb6f15496304c1fdad8eec8876c5c17bddb7a4 /src | |
| parent | b32166c8a02cbab455cf94c56da81f03304d299b (diff) | |
| download | kutter-ccaf58a02cf132cb43ad3f45f5200841044f66a8.tar.gz kutter-ccaf58a02cf132cb43ad3f45f5200841044f66a8.tar.xz kutter-ccaf58a02cf132cb43ad3f45f5200841044f66a8.zip | |
stm32f1: Fix for using 16MHz external crystal (#3814)
Signed-off-by: Matt Shepcar <matt@shepcar.co.uk>
Diffstat (limited to 'src')
| -rw-r--r-- | src/stm32/stm32f1.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/stm32/stm32f1.c b/src/stm32/stm32f1.c index a1c4c7fe..886b7b91 100644 --- a/src/stm32/stm32f1.c +++ b/src/stm32/stm32f1.c @@ -162,9 +162,14 @@ clock_setup(void) uint32_t cfgr; if (!CONFIG_STM32_CLOCK_REF_INTERNAL) { // Configure 72Mhz PLL from external crystal (HSE) - uint32_t div = CONFIG_CLOCK_FREQ / CONFIG_CLOCK_REF_FREQ; RCC->CR |= RCC_CR_HSEON; - cfgr = (1 << RCC_CFGR_PLLSRC_Pos) | ((div - 2) << RCC_CFGR_PLLMULL_Pos); + uint32_t div = CONFIG_CLOCK_FREQ / (CONFIG_CLOCK_REF_FREQ / 2); + cfgr = 1 << RCC_CFGR_PLLSRC_Pos; + if ((div & 1) && div <= 16) + cfgr |= RCC_CFGR_PLLXTPRE_HSE_DIV2; + else + div /= 2; + cfgr |= (div - 2) << RCC_CFGR_PLLMULL_Pos; } else { // Configure 72Mhz PLL from internal 8Mhz oscillator (HSI) uint32_t div2 = (CONFIG_CLOCK_FREQ / 8000000) * 2; |