stm32f4: Only enable peripherals once

Add is_enabled_pclock() and only initialize spi and adc once during
configuration.

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>

4 files changed, 35 insertions, 13 deletions

diff --git a/src/stm32f4/adc.c b/src/stm32f4/adc.c
index 00eac8f0..07d03003 100644
--- a/src/stm32f4/adc.c
+++ b/src/stm32f4/adc.c
@@ -34,15 +34,17 @@ gpio_adc_setup(uint32_t pin)
     }
 
     // Enable the ADC
-    enable_pclock(ADC1_BASE);
-    uint32_t aticks = 3; // 56 adc cycles
-    ADC1->SMPR1 = (aticks | (aticks << 3) | (aticks << 6) | (aticks << 9)
-                   | (aticks << 12) | (aticks << 15) | (aticks << 18)
-                   | (aticks << 21) | (aticks << 24));
-    ADC1->SMPR2 = (aticks | (aticks << 3) | (aticks << 6) | (aticks << 9)
-                   | (aticks << 12) | (aticks << 15) | (aticks << 18)
-                   | (aticks << 21) | (aticks << 24) | (aticks << 27));
-    ADC1->CR2 = ADC_CR2_ADON;
+    if (!is_enabled_pclock(ADC1_BASE)) {
+        enable_pclock(ADC1_BASE);
+        uint32_t aticks = 3; // 56 adc cycles
+        ADC1->SMPR1 = (aticks | (aticks << 3) | (aticks << 6) | (aticks << 9)
+                       | (aticks << 12) | (aticks << 15) | (aticks << 18)
+                       | (aticks << 21) | (aticks << 24));
+        ADC1->SMPR2 = (aticks | (aticks << 3) | (aticks << 6) | (aticks << 9)
+                       | (aticks << 12) | (aticks << 15) | (aticks << 18)
+                       | (aticks << 21) | (aticks << 24) | (aticks << 27));
+        ADC1->CR2 = ADC_CR2_ADON;
+    }
 
     gpio_peripheral(pin, GPIO_ANALOG, 0);
 
diff --git a/src/stm32f4/clock.c b/src/stm32f4/clock.c
index bbd58aa5..b5fd16f8 100644
--- a/src/stm32f4/clock.c
+++ b/src/stm32f4/clock.c
@@ -28,6 +28,23 @@ enable_pclock(uint32_t periph_base)
     }
 }
 
+// Check if a peripheral clock has been enabled
+int
+is_enabled_pclock(uint32_t periph_base)
+{
+    if (periph_base < APB2PERIPH_BASE) {
+        uint32_t pos = (periph_base - APB1PERIPH_BASE) / 0x400;
+        return RCC->APB1ENR & (1<<pos);
+    } else if (periph_base < AHB1PERIPH_BASE) {
+        uint32_t pos = (periph_base - APB2PERIPH_BASE) / 0x400;
+        return RCC->APB2ENR & (1<<pos);
+    } else if (periph_base < AHB2PERIPH_BASE) {
+        uint32_t pos = (periph_base - AHB1PERIPH_BASE) / 0x400;
+        return RCC->AHB1ENR & (1<<pos);
+    }
+    return 0;
+}
+
 // Return the frequency of the given peripheral clock
 uint32_t
 get_pclock_frequency(uint32_t periph_base)
diff --git a/src/stm32f4/internal.h b/src/stm32f4/internal.h
index f1c2fd66..062d7c65 100644
--- a/src/stm32f4/internal.h
+++ b/src/stm32f4/internal.h
@@ -14,6 +14,7 @@
 #define GPIO_ANALOG 3
 
 void enable_pclock(uint32_t periph_base);
+int is_enabled_pclock(uint32_t periph_base);
 uint32_t get_pclock_frequency(uint32_t periph_base);
 void clock_setup(void);
 void gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup);
diff --git a/src/stm32f4/spi.c b/src/stm32f4/spi.c
index a7e96874..f8852be9 100644
--- a/src/stm32f4/spi.c
+++ b/src/stm32f4/spi.c
@@ -19,10 +19,12 @@ spi_setup(uint32_t bus, uint8_t mode, uint32_t rate)
         shutdown("Invalid spi bus");
 
     // Enable SPI
-    enable_pclock(SPI2_BASE);
-    gpio_peripheral(GPIO('B', 14), GPIO_FUNCTION(5), 1);
-    gpio_peripheral(GPIO('B', 15), GPIO_FUNCTION(5), 0);
-    gpio_peripheral(GPIO('B', 13), GPIO_FUNCTION(5), 0);
+    if (!is_enabled_pclock(SPI2_BASE)) {
+        enable_pclock(SPI2_BASE);
+        gpio_peripheral(GPIO('B', 14), GPIO_FUNCTION(5), 1);
+        gpio_peripheral(GPIO('B', 15), GPIO_FUNCTION(5), 0);
+        gpio_peripheral(GPIO('B', 13), GPIO_FUNCTION(5), 0);
+    }
 
     // Calculate CR1 register
     uint32_t pclk = get_pclock_frequency(SPI2_BASE);